CN113725234B - Pixel driving circuit, preparation method thereof, array substrate and display device - Google Patents
Pixel driving circuit, preparation method thereof, array substrate and display device Download PDFInfo
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- CN113725234B CN113725234B CN202111016036.5A CN202111016036A CN113725234B CN 113725234 B CN113725234 B CN 113725234B CN 202111016036 A CN202111016036 A CN 202111016036A CN 113725234 B CN113725234 B CN 113725234B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Geometry (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of El Displays (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The disclosure provides a pixel driving circuit, a preparation method thereof, an array substrate and a display device, and relates to the technical field of display, wherein the pixel driving circuit is used for avoiding display afterimages and display bright spots and reducing power consumption. The pixel driving circuit includes a driving transistor and a switching transistor coupled to the driving transistor, the driving transistor including a first active layer having a first channel region, a first source region, and a first drain region; the switching transistor includes a second active layer having a second channel region, a second source region, and a second drain region; the semiconductor substrate of the second channel region is the same as the semiconductor substrate of the first channel region, the doping type is the same, and the doping concentration of the first channel region is larger than that of the second channel region.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a pixel driving circuit, a manufacturing method thereof, an array substrate, and a display device.
Background
At present, organic Light-emitting diode (OLED) display devices (OLED) have been widely used because they have advantages of self-luminescence, fast response speed, low power consumption, etc.
In the pixel driving circuit included in the OLED display device, the light emission of the OLED and the light emission brightness are generally controlled by a plurality of thin film transistors (Thin Film Transistor, abbreviated as TFTs). The formation of the thin film transistor is not separated from the semiconductor material, but is limited by the characteristics of the semiconductor material, so that the thin film transistor can have the problems of electric leakage, small on-current and the like, and finally the display picture of the display device has bright spots, afterimages and the like, so that the appearance of the display picture is poor, and the yield of the display device is adversely affected.
Disclosure of Invention
The embodiment of the invention provides a pixel driving circuit, a preparation method thereof, an array substrate and a display device, which are used for avoiding display afterimages and display bright spots and reducing power consumption.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical scheme:
in a first aspect, a pixel driving circuit is provided that includes a driving transistor and a switching transistor coupled to the driving transistor; the driving transistor includes a first active layer having a first channel region, a first source region, and a first drain region; the switching transistor includes a second active layer having a second channel region, a second source region, and a second drain region; the second channel region and the semiconductor substrate of the first channel region are the same, the doping type is the same, and the doping concentration of the first channel region is greater than that of the second channel region.
In some embodiments, the doping concentration of the first channel region is 1.375-2 times the doping concentration of the second channel region.
In some embodiments, the doping concentration of the second channel region is 5 x 10≡11/cm 2 ～8*10^11/cm 2 The doping concentration of the first channel region is 3 x 10 x 11/cm greater than that of the second channel region 2 ～5*10^11/cm 2 。
In some embodiments, the ions doped in the first channel region and the second channel region are any one of boron ions, aluminum ions, gallium ions, and indium ions.
In some embodiments, the first channel region has a smaller aspect ratio than the second channel region.
In some embodiments, the width of the first channel region is equal to the width of the second channel region, and the length of the first channel region is greater than the length of the second channel region.
In some embodiments, the doping concentration of the first channel region is less than the doping concentrations of the first source region and the first drain region; the doping concentration of the second channel region is less than the doping concentrations of the second source region and the second drain region.
In some embodiments, the semiconductor substrate is polysilicon.
In a second aspect, an array substrate is provided, including the pixel driving circuit described in any embodiment of the first aspect.
In a third aspect, a display device is provided, including an array substrate as described in any embodiment of the second aspect.
In a fourth aspect, a method for manufacturing a pixel driving circuit including a driving transistor and a switching transistor coupled to the driving transistor is provided, the method comprising: forming a semiconductor pattern on a substrate using a semiconductor substrate; doping the semiconductor pattern to obtain a doped semiconductor pattern, wherein the doped semiconductor pattern is provided with a first channel region of the driving transistor and a second channel region of the switching transistor; the semiconductor substrate of the first channel region and the semiconductor substrate of the second channel region are the same, the doping type is the same, and the doping concentration of the first channel region is larger than that of the second channel region.
In some embodiments, the doping the semiconductor pattern to obtain a doped semiconductor pattern includes: performing first doping on the semiconductor pattern to obtain an initial doped semiconductor pattern; and carrying out second doping on the part corresponding to the first channel region in the initial doped semiconductor pattern to obtain the doped semiconductor pattern.
In some embodiments, the second doping the portion of the initially doped semiconductor pattern corresponding to the first channel region to obtain the doped semiconductor pattern includes: and shielding the part except the first channel region in the initial doped semiconductor pattern by utilizing a metal mask plate, and carrying out second doping on the part corresponding to the first channel region in the initial doped semiconductor pattern.
In some embodiments, the method for manufacturing a pixel driving circuit further includes: and doping parts of the doped semiconductor pattern except the first channel region and the second channel region to form an active pattern layer including a first source region and a first drain region of the driving transistor, and a second source region and a second drain region of the switching transistor.
The doping concentration of the first channel region of the driving transistor is set to be larger than that of the second channel region of the switching transistor, so that the first channel region has stable carrier concentration, the defect number of carriers in the first channel region is reduced, the threshold voltage offset of the driving transistor is ensured to be uniform, the variation amplitude of the on current of different driving transistors is also uniform, short-term afterimages caused by different threshold voltage drift amounts can be avoided, and the display effect is improved. Meanwhile, the threshold voltage of the driving transistor can be shifted forward, and the driving transistor is easier to be started after the voltage is applied, so that the power consumption is reduced. In addition, the doping concentrations of the first channel region and the second channel region are respectively set, so that synchronous forward shift of the threshold voltage of the switching transistor and the threshold voltage of the driving transistor can be avoided, the forward shift degree of the threshold voltage of the switching transistor is ensured to be smaller, and the risk of bright spots is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a display panel provided in at least one embodiment of the present disclosure;
FIG. 2 is a block diagram of a substrate provided in accordance with at least one embodiment of the present disclosure;
fig. 3 is an equivalent circuit diagram of a pixel driving circuit provided in at least one embodiment of the present disclosure;
FIG. 4 is a timing diagram of a pixel driving circuit provided in at least one embodiment of the present disclosure;
fig. 5 is a block diagram of a transistor provided in at least one embodiment of the present disclosure;
fig. 6 is a block diagram of an active pattern layer in a pixel driving circuit according to at least one embodiment of the present disclosure;
FIG. 7 is an I-V relationship for a transistor provided in at least one embodiment of the present disclosure;
FIG. 8 is an I-V relationship for transistors having different channel region doping concentrations provided in accordance with at least one embodiment of the present disclosure;
FIG. 9 is a flow chart of a fabrication process of a pixel driving circuit according to at least one embodiment of the present disclosure;
fig. 10A to 10E are process flow diagrams for manufacturing a pixel driving circuit according to at least one embodiment of the present disclosure;
FIG. 11 is a flow chart of a process for preparing a doped semiconductor pattern provided in at least one embodiment of the present disclosure;
fig. 12 is a process flow diagram of a process for preparing a doped semiconductor pattern provided in at least one embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.
In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled (communicatively coupled)" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.
"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.
"plurality" means at least two.
The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.
In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.
Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
In recent years, the market share of OLED display devices is increasing, and the requirements of the consumer market for image quality and yield of OLED display devices are also increasing. The low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) technology is a new generation of thin film transistor manufacturing process, and an OLED display device using LTPS TFTs has faster response time, higher resolution and better display picture quality. Although LTPS technology has been greatly developed, when LTPS TFTs are manufactured in a large area, LTPS TFTs at different positions often have non-uniformity in electrical parameters such as threshold voltage and mobility, and such non-uniformity may be represented as brightness difference of an OLED display device and perceived by human eyes, resulting in bright spots, afterimages, and the like on a display screen of the display device.
In order to solve the above-described problems, some embodiments of the present disclosure provide a display device configured to display an image; for example, a still image, a moving image, or the like may be displayed.
Illustratively, the display device may be: any one of a display, a television, a billboard, a laser printer with a display function, a home appliance, a large-area wall, an information inquiry device (such as business inquiry devices of e-government departments, banks, hospitals, electric power departments and the like), a mobile phone, a personal digital assistant (Personal Digital Assistant, PDA), a digital camera, a portable video camera, a navigator and the like; but also micro-displays or products containing micro-displays, such as near-eye displays or wearable devices, etc., in particular AR/VR systems, smart glasses, head-mounted displays (Head Mounted Display, abbreviated to HMD) and Head-Up displays (abbreviated to HUD).
The display device may be a display panel or a product including a display panel and a driving circuit coupled to the display panel configured to drive the display panel to display an image, for example. The display panel may be an OLED (Organic Light Emitting Diode ) panel, a QLED (Quantum Dot Light Emitting Diodes, quantum Point light emitting diode) panel, a Micro LED (including Mini LED or Micro LED) panel, or the like.
Illustratively, referring to fig. 1, the display panel 10 has an Active Area (AA Area) and a peripheral Area S. Wherein the peripheral area S is located at least on one side of the display area. Illustratively, the peripheral region S may be disposed around the display region one turn.
Illustratively, with continued reference to FIG. 1, the display panel 10 may include a plurality of subpixels P located in the AA area. The plurality of subpixels P may be arranged in an array. For example, the sub-pixels P arranged in a row in the X direction are referred to as the same sub-pixel P, and the sub-pixels P arranged in a row in the Y direction are referred to as the same column of sub-pixels P. The plurality of subpixels P may include a first color subpixel, a second color subpixel, and a third color subpixel; for example, the first color, the second color, and the third color are three primary colors; for example, the first color, the second color, and the third color are red, green, and blue, respectively; that is, the plurality of subpixels P include red, green, and blue subpixels.
In some embodiments of the present disclosure, referring to fig. 1, a display panel 10 includes an array substrate 100 and a member to be driven (e.g., a light emitting device L), the array substrate 100 including a substrate 110 and at least one (e.g., a plurality of) pixel driving circuits 120 disposed on the substrate 110. The to-be-driven member is disposed on the array substrate 100, and is driven to work by the pixel driving circuit 120 in the array substrate 100.
Illustratively, the substrate 110 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate ) substrate, or the like. As yet another example, the substrate 110 may be a flexible substrate, for example, a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, or a PI (Polyimide) substrate, or the like. Referring to fig. 2, the substrate 110 may further include a substrate base PI and at least one film layer, e.g., a Barrier layer (Barrier), a Buffer layer (Buffer), etc., formed on the substrate base PI. Illustratively, with continued reference to fig. 2, the substrate 110 may include a plurality (e.g., two) of substrate units disposed in a stack, and an amorphous silicon layer may be disposed between adjacent two of the substrate units for increasing adhesion between the adjacent two of the substrate units. Each substrate unit may include: a substrate PI and a barrier layer disposed on the substrate PI.
Illustratively, referring to fig. 1, at least one subpixel P (e.g., each) in the display panel 10 includes a pixel driving circuit 120 and a light emitting device L. Wherein the pixel driving circuit 120 is coupled with the light emitting device L. The pixel driving circuit 120 is configured to drive the light emitting device L to emit light. Illustratively, the plurality of pixel driving circuits 120 are arranged in an array.
The embodiment of the present disclosure does not limit the specific structure of the pixel driving circuit 120, and may be designed according to practical situations. The pixel driving circuit 120 is illustratively composed of an electronic device such as a thin film transistor (Thin Film Transistor, TFT) and a storage capacitor (C). For example, the pixel driving circuit 120 may include two thin film transistors (one switching transistor and one driving transistor) and one storage capacitor, constituting a 2T1C structure; of course, the pixel driving circuit 120 may further include two or more thin film transistors (a plurality of switching transistors and one driving transistor) and at least one capacitor, for example, referring to fig. 3, the pixel driving circuit 120 may include one storage capacitor C and seven transistors (six switching transistors SW and one driving transistor DR) to constitute a 7T1C structure.
Illustratively, the type of thin film transistor is not overly limited. For example, the thin film transistor may be an Oxide thin film transistor (Oxide TFT), a low temperature polysilicon thin film transistor, or the like. The pixel driving circuit 120 may include only an oxide thin film transistor, only a low temperature polysilicon thin film transistor, and both an oxide thin film transistor and a low temperature polysilicon thin film transistor.
Illustratively, referring to fig. 3, taking the 7T1C structure as shown by the pixel driving circuit 120 as an example, a plurality of signal lines, for example, a gate line GL, a data line DL, a light emission control signal line EM, an initialization signal line Init, reset signal lines RST and RST', and the like are provided on the array substrate 100 in addition to the plurality of pixel driving circuits 120. The gate line GL may be used to transmit a gate driving signal; the data line DL is configured to provide a data signal (data current or data voltage) to the driving member to drive the driving member to operate; a drive control signal line (e.g., a light emission control signal line EM) may be used to transmit a drive control signal (e.g., a light emission control signal); the initialization signal line Init may be used to transmit an initialization signal; the reset signal lines RST and RST' may be used to transmit a reset signal.
For example, each of the pixel driving circuits 120 of the same row may be coupled with one gate line GL, one reset signal line RST', and one emission control signal line EM. Wherein, the reset signal line RST and the reset signal line RST' coupled to each pixel driving circuit 120 of the same row may be two signal lines, respectively transmitting different reset signals; the same reset signal may be transmitted through the same signal line. Illustratively, the pixel driving circuits 120 of the same column may be coupled with the same data line DL.
For example, referring to fig. 3, the 7 thin film transistors include a driving transistor DR, a data writing transistor T1, a compensation transistor T2, a reset transistor T3, light emission control transistors T4 and T5, and an anode reset transistor T6. The gates of the compensation transistor T2 and the data writing transistor T1 are used for receiving the gate driving signal, the gates of the light emitting control transistors T4 and T5 are used for receiving the gate driving signal, and the gates of the reset transistor T3 and the anode reset transistor T6 are used for receiving the reset signal.
For example, referring to fig. 3 and 4, first, in a reset phase, the reset transistor T3 and the anode reset transistor T6 are turned on in response to a reset signal, and an initialization signal is transmitted to the control electrode g of the driving transistor DR and the anode of the light emitting device L through the reset transistor T3 and the anode reset transistor T6, respectively, for the purpose of resetting the control electrode g of the driving transistor DR and the anode of the light emitting device L. Next, in the data writing stage, the compensation transistor T2 is turned on in response to the gate driving signal, the control electrode g of the driving transistor DR is coupled to the drain d, the driving transistor DR is in a diode-on state, and at the same time, the data writing transistor T1 is turned on in response to the gate driving signal, the data signal is written to the source s of the driving transistor DR through the data writing transistor T1, and the compensation signal obtained from the data signal and the threshold voltage of the driving transistor DR is applied to the control electrode g of the driving transistor DR. Thereafter, in the light emission stage, the light emission control transistors T4 and T5 are turned on in response to the light emission control signal, a current path between the first power supply voltage line VDD and the second power supply voltage terminal VSS is turned on, and a driving current generated based on a difference between a voltage of the control electrode g of the driving transistor DR and a first power supply voltage signal (a signal supplied from the first power supply voltage line VDD) is transmitted to the light emitting device L through the current path to drive the light emitting device L to emit light. Illustratively, one pole (e.g., anode) of the light emitting device L is coupled to the pixel driving circuit 120, and the other pole (e.g., cathode) of the light emitting device L is coupled to the second power voltage terminal VSS, which may be configured to transmit a dc voltage, such as a dc low voltage.
Illustratively, the light emitting device L may employ a light emitting diode (Light Emitting Diode, LED), an OLED or quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED), or the like. The light emitting device L includes a cathode and an anode, and a light emitting functional layer between the cathode and the anode. The light emitting functional layer may include, for example, an Emission layer (EML), a hole transport layer (Hole Transporting Layer, HTL) between the light emitting functional layer and the anode, and an electron transport layer (Election Transporting Layer, ETL) between the light emitting functional layer and the cathode. Of course, in some embodiments, a hole injection layer (Hole Injection Layer, HIL) may also be provided between the hole transport layer and the anode, and an electron injection layer (Election Injection Layer, EIL) may be provided between the electron transport layer and the cathode, as desired.
For example, the anode may be formed of a transparent conductive material having a high work function, and an electrode material thereof may include Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Oxide (IGO), gallium Zinc Oxide (GZO), zinc oxide (ZnO), indium oxide (In 2O 3), aluminum Zinc Oxide (AZO), carbon nanotubes, and the like; the cathode may be formed of a material having high conductivity and low work function, for example, and the electrode material may include an alloy such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl) or a metal element such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag). The material of the light emitting layer may be selected according to the color of light emitted therefrom. For example, the material of the light-emitting functional layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material. In at least one embodiment of the present disclosure, the light-emitting functional layer may employ a doping system, i.e., a doping material is mixed into the host light-emitting material to obtain a useful light-emitting material. For example, the host light emitting material may employ a metal compound material, an anthracene derivative, an aromatic diamine compound, a triphenylamine compound, an aromatic triamine compound, a biphenyldiamine derivative, a triarylamine polymer, or the like.
For simplicity of description, the thin film transistors other than the driving transistor in the pixel driving circuit are hereinafter referred to as switching transistors. Illustratively, referring to fig. 3, the data writing transistor T1, the compensation transistor T2, the reset transistor T3, the light emission control transistors T4 and T5, and the anode reset transistor T6 in the pixel driving circuit 120 are all switching transistors SW, and the pixel driving circuit 120 includes one driving transistor DR and at least one (e.g., 6) switching transistors SW.
Next, a specific structure of the thin film transistor in the pixel circuit will be described in detail taking the pixel driving circuit 120 as an example of the above-described 7T1C structure.
For example, referring to fig. 5, at least one (e.g., each) thin film transistor may include an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and source and drain electrodes disposed in the same layer, which are sequentially stacked on a substrate. The active layer comprises a source region, a drain region and a channel region arranged between the source region and the drain region, the source layer is coupled with the source region in the active layer, the drain layer is coupled with the drain region in the active layer, and the active layers of a plurality of transistors in the same pixel driving circuit form an active pattern layer.
In some embodiments, referring to fig. 3 and 6, the pixel driving circuit 120 includes an active pattern layer SP, and the pixel driving circuit 120 includes a driving transistor DR and a switching transistor SW coupled to each other. The driving transistor DR includes a first active layer 130, the first active layer 130 having a first source region 131, a first channel region 132, and a first drain region 133, the switching transistor SW includes a second active layer 140, the second active layer 140 having a second source region 141, a second channel region 142, and a second drain region 143, the second channel region 142 being the same as the semiconductor substrate of the first channel region 132. As described above, the switching transistor SW includes the data writing transistor T1, the compensation transistor T2, the reset transistor T3, the light emission control transistors T4 and T5, and the anode reset transistor T6, and in particular, the data writing transistor T1 includes the second active layer 140a, the second active layer 140a having the second source region 141a, the second channel region 142a, and the second drain region 143a; the compensation transistor T2 includes a second active layer 140b, the second active layer 140b having a second source region 141b, a second channel region 142b, and a second drain region 143b; the reset transistor T3 includes a second active layer 140c, the second active layer 140c having a second source region 141c, a second channel region 142c, and a second drain region 143c; the light emission control transistor T4 includes a second active layer 140d, the second active layer 140d having a second source region 141d, a second channel region 142d, and a second drain region 143d; the light emission control transistor T5 includes a second active layer 140e, the second active layer 140e having a second source region 141e, a second channel region 142e, and a second drain region 143e; the anode reset transistor T6 includes a second active layer 140f, the second active layer 140f having a second source region 141f, a second channel region 142f, and a second drain region 143f.
As an example, referring to fig. 3 and 6, the semiconductor substrate of the first channel region 132 and the semiconductor substrate of the second channel region 142 are the same, i.e., the semiconductor substrate of the first active layer 130 and the semiconductor substrate of the second active layer 140, i.e., the semiconductor substrate of the active pattern layer of the pixel driving circuit 120 is the same semiconductor material, and specifically, may be Indium Gallium Zinc Oxide (IGZO) and/or polysilicon, etc. For example, low Temperature Polysilicon (LTPS) may be used as the semiconductor substrate of the driving transistor DR and the switching transistor SW (i.e., the display panel 10 is an LTPS display panel 10), and for example, LTPS and IGZO may be used simultaneously, where the semiconductor substrate of the driving transistor DR and at least one (e.g., one) switching transistor SW is IGZO, and the active layer material of the other transistors in the pixel driving circuit 120 is LTPS (i.e., the display panel 10 is an LTPO display panel 10). The LTPS TFT may be an N-type metal-oxide-semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) transistor or a P-type (Positive channel Metal Oxide Semiconductor, PMOS) transistor. For simplicity, the following description will proceed with the scheme of the present disclosure taking the semiconductor substrates of the driving transistor DR and the switching transistor SW as low-temperature polysilicon and PMOS transistors as examples.
The low-temperature polysilicon substrate is composed of a plurality of p-Si crystal grains, grain boundaries among the p-Si crystal grains in the substrate contain a plurality of faults, dislocation and defects, a plurality of dangling bonds exist, carrier traps are easy to form, the carrier traps can capture carriers, the concentration of residual movable carriers is changed, threshold voltage drift is caused, and the drift amount is uneven. When different display pictures are displayed, as the threshold voltage drift amounts of the driving transistors DR are different in the pixel driving circuits 120 at different positions in the display panel and the variation ranges of the on currents of the different driving transistors DR are different, the display brightness of the display pictures is different and can be perceived by human eyes, which is indicated as afterimage of the display pictures.
When carriers are trapped by carrier traps at grain boundaries and exist in the traps for a long time, the threshold voltage of the driving transistor DR is caused to shift in a negative direction, thereby adversely affecting the display effect of the display panel. In the related art, the threshold voltage of the driving transistor DR is generally adjusted in the forward direction to avoid the occurrence of an afterimage on the display screen. For example, the materials and thicknesses of the active layer and the gate insulating layer may be changed, or the active layer may be heat treated to reduce grain boundary defects, or the active layer may be doped to positively shift the threshold voltage. Specifically, the threshold voltage of the transistor is shifted forward even if the absolute value of the threshold voltage value is smaller. For example, when the driving transistor DR and the switching transistor SW are PMOS transistors, the threshold voltages thereof have negative values, so that the threshold voltages of the driving transistor DR and the switching transistor SW are shifted forward, i.e., the threshold voltages thereof are closer to 0V; when the driving transistor DR and the switching transistor SW are both NMOS transistors, the threshold voltage is positive, so that the threshold voltage is shifted forward to be closer to 0V.
However, as described above, changing the materials and thicknesses of the active pattern layer and the gate insulating layer may adversely affect the stress matching of the entire array substrate, resulting in easy cracking or even breaking of the array substrate, and affecting the product yield. The active pattern layer is subjected to heat treatment, so that larger grain size can be obtained, defects among grains are reduced, but the substrate is required to be made of quartz or high-temperature-resistant glass with other characteristics, so that the practical use is not facilitated, and meanwhile, the active pattern layer and the substrate are easily stripped due to a high-temperature process, and the product yield is also influenced. In addition, the above two methods and the doping of the active layer are all the adjustments of the active pattern layers of all the pixel driving circuits 120, and the threshold voltages of the plurality of switching transistors SW are also shifted forward while the threshold voltages of the driving transistors DR are shifted forward.
Referring to fig. 7, a curve a is an I-V relationship curve of a transistor TA whose threshold voltage is not shifted forward, a curve B is an I-V relationship curve of a transistor TB whose threshold voltage is shifted forward, a threshold voltage of the transistor TA is VA, and a threshold voltage of the transistor TB is VB. When the voltages applied to the gates of the transistors TA and TB are V1, V1< VA and V1< VB, it can be seen that the leakage current IB of the transistor TB is larger than the leakage current IA of the transistor TA. It can be seen that the positive shift of the threshold voltage increases the leakage current of the transistors, that is, the leakage current of the driving transistor DR and the switching transistor SW increases by the above methods. Referring to fig. 3 and fig. 4, if any of the foregoing methods is adopted to make the threshold voltage of each transistor in the pixel driving circuit 120 forward shift, in the light emitting stage, the reset transistor T3 is in the off state, the driving transistor DR and the light emitting control transistors T4 and T5 are in the on state, and due to the forward shift of the threshold voltage, the leakage current of the reset transistor T3 increases, so that the pull-down degree of the N1 node potential increases, the voltage difference between the voltage of the control electrode g of the driving transistor DR and the first power voltage signal increases, the on current phase strain is large, and the increased on current is transmitted to the light emitting device L through the current path, so that the light emitting brightness of the light emitting device L increases, resulting in high brightness of the display screen, and affecting the display quality.
In some embodiments of the present disclosure, referring to fig. 3 and 6, the doping type of the first channel region 132 and the second channel region 142 is the same, and the doping concentration of the first channel region 132 is greater than the doping concentration of the second channel region 142. Exemplary doping types include P-type doping to dope trivalent impurity elements (e.g., boron, aluminum, gallium, indium, etc.) into a semiconductor substrate to form a P-type semiconductor, and N-type doping to dope pentavalent impurity elements (e.g., phosphorus, antimony, arsenic, etc.) into a semiconductor substrate to form an N-type semiconductor. The doping types of the first channel region 132 and the second channel region 142 are the same, i.e., the doping types of the first channel region 132 and the second channel region 142 are P-type doping, or the doping types of the first channel region 132 and the second channel region 142 are N-type doping. For example, the doping type of the first channel region 132 and the second channel region 142 are both P-type doping. As can be seen from the foregoing, doping the active pattern layer positively shifts the threshold voltages of the transistors in the pixel driving circuit 120, which is likely to cause high light spots. In the embodiment of the disclosure, the doping concentration of the first channel region 132 is greater than the doping concentration of the second channel region 142, that is, the doping concentration of the second active layer 140 of the switching transistor SW is less than the doping concentration of the first active layer 130 of the driving transistor DR when the active pattern layer of the pixel driving circuit 120 is formed. So that the threshold voltage of the driving transistor DR is shifted forward to a large extent and the threshold voltage of the switching transistor SW is shifted forward to a small extent. The semiconductor substrate may be doped by high temperature diffusion or ion implantation, for example. For example, in the embodiment of the present disclosure, doping of the semiconductor substrate may be achieved by ion implantation to form the first channel region 132 and the second channel region 142 having different doping concentrations. Illustratively, the first channel region 132 and the second channel region 142 may be doped respectively such that a doping concentration of the first channel region 132 is greater than a doping concentration of the second channel region 142 in the formed active layer pattern. Also for example, the first channel region 132 and the second channel region 142 may be doped first at the same time, and then the first channel region 132 may be doped second, so that the first channel region 132 and the second channel region 142 having different doping concentrations may be formed. Specifically, the specific process steps for implementing the above arrangement are not limited, and only at least one process step for doping the first channel region 132 and the second channel region 142 with different concentrations is limited.
As described above, the first channel region 132 of the driving transistor DR in each pixel driving circuit 120 is doped with a larger concentration, so that the carrier concentration of the first channel region 132 is increased, and thus, even if some carriers are captured by carrier traps at the grain boundary, the movable carrier concentration in the first channel region 132 can still be kept at a certain value, and in the pixel driving circuits 120 at different positions in the display panel 10, the threshold voltage shift amounts of the driving transistors DR are more uniform, and the variation ranges of the on-currents of different driving transistors DR are also more uniform, so that short-term afterimages caused by different threshold voltage shift amounts can be avoided, and the display effect is improved. Meanwhile, the impurity element ions are adopted to dope the first channel region 132 in a larger concentration, so that the impurity element ions can fill carrier traps to a certain extent, the effect of maintaining the uniformity of the threshold voltage offset can be achieved, and the risk of afterimage is further reduced. In addition, the threshold voltage of the driving transistor DR is forward shifted, macroscopically representing smaller voltage required to turn on the driving transistor DR, thereby contributing to reduction of power consumption.
In addition, as is clear from the foregoing, the greater the doping concentration, the greater the degree of forward shift in the threshold voltage of the transistor. The first channel region 132 and the second channel region 142 are doped respectively, so that the doping concentration of the first channel region 132 is larger than that of the second channel region 142, and the forward offset degree of the threshold voltage of the switch transistor SW is ensured to be smaller on the premise that the movable carrier concentration of the second channel region 142 is increased by doping so as to increase the on-current of the switch transistor SW, thereby avoiding the leakage current of the switch transistor SW from being greatly increased due to overlarge forward offset degree and reducing the risk of bright spots.
Illustratively, referring to fig. 3 and 6, the ions doped in the first channel region 132 and the second channel region 142 are any one of boron ions, aluminum ions, gallium ions, and indium ions. For example, the ions doped in the first channel region 132 and the second channel region 142 are boron ions. The radius of the boron ions is relatively close to that of the silicon atoms, so that the boron ions are injected into the semiconductor substrate through ion injection, the carrier concentration can be increased, carrier traps can be filled, and the damage to the semiconductor substrate is avoided on the premise that the threshold voltage drift degree of the transistor caused by carrier trap carrier capture is further reduced.
Illustratively, referring to fig. 3 and 6, the aspect ratio of the first channel region 132 is less than the aspect ratio of the second channel region 142. Specifically, the width W1 of the first channel region 132 is equal to the width W2 of the second channel region 142, and the length L1 of the first channel region 132 is greater than the length L2 of the second channel region 142. For example, the length L2 of the second channel region 142 in the switching transistor SW is 4 μm, the width W2 is 3 μm, the width-to-length ratio of the second channel region 142 is 3/4, the length L1 of the first channel region 132 in the driving transistor DR is 20 μm, the width W1 is 3 μm, and the width-to-length ratio of the first channel region 132 is 3/20. Specifically, the first channel region 132 has a larger channel length L1, so that leakage of the driving transistor DR can be avoided, and adverse effects such as threshold voltage reduction, drain-induced barrier reduction, carrier surface scattering, velocity saturation, ionization, and thermal electron effect on characteristics of the driving transistor DR due to short channel effect caused by too small channel length L1 can be avoided, so that sensitivity of characteristics of the driving transistor DR to variation of the channel length L1 is reduced, a more stable driving transistor DR is formed, uniformity of the driving transistors DR in the pixel driving circuits 120 at different positions of the display panel is improved, and short-term afterimages are avoided. On the premise of ensuring the stable characteristics of the driving transistor DR, the switching transistor SW is arranged to have smaller channel length L2, which is beneficial to increasing the integration level of the circuit and reducing the size of the device.
In some embodiments of the present disclosure, referring to fig. 3 and 6, the doping concentration of the first channel region 132 is 1.375-2 times the doping concentration of the second channel region 142. Specifically, the doping concentration of the second channel region 142 is 5×10≡11/cm 2 ～8*10^11/cm 2 The doping concentration of the first channel region 132 is 3 x 10≡11/cm greater than the doping concentration of the first channel region 132 2 ～5*10^11/cm 2 . Illustratively, the doping concentrations of the first channel region 132 and the second channel region 142 are at a surface of the substrate 110, which is away from the substrate, and may be secondarily separated by a time of flightA sub mass spectrometer (Time of Flight Secondary Ion Mass Spectrometry, TOF-SIMS for short) or other interface and membrane element analysis means.
For example, referring to fig. 3 and 6, the first channel region 132 and the second channel region 142 may be doped, respectively, that is, only one of the first channel region 132 and the second channel region 142 is doped in a first doping process, and the other of the first channel region 132 and the second channel region 142 is doped in a second doping process, so that a doping concentration of the first channel region 132 is less than a doping concentration of the second channel region 142 in the formed active layer pattern. For example, in the first doping process, only boron ions are doped into the second channel region 142 by ion implantation, the concentration of boron ions being 5×10≡11/cm 2 The doping concentration of the first channel region 132 is 2 times that of the second channel region 142, and in the second doping process, boron ions are doped only into the first channel region 132 by ion implantation, the concentration of the boron ions being 10 x 11/cm 2 The doping concentration of the first channel region 132 is 5 x 10 x 11/cm greater than the doping concentration of the second channel region 142 2 Is formed on the substrate.
As another example, referring to fig. 3 and 6, the first channel region 132 and the second channel region 142 are also doped, respectively, and the first channel region 132 and the second channel region 142 are doped simultaneously in a first doping process, and only the first channel region 132 is doped in a second doping process. For example, in the first doping process, boron ions are doped simultaneously into the first channel region 132 and the second channel region 142 by ion implantation, the concentration of boron ions being 5 x 10≡11/cm 2 The doping concentration of the first channel region 132 is 1.6 times that of the second channel region 142, and in the second doping process, only boron ions are doped into the first channel region 132 by ion implantation, the concentration of the boron ions being 3 x 10 x 11/cm 2 The doping concentration of the first channel region 132 is 3 x 10 x 11/cm greater than the doping concentration of the second channel region 142 2 Is formed on the substrate.
Referring to fig. 3, 6 and 8, the doping concentration of the first channel region 132 is greater than the doping concentration of the second channel region 142The I-V curves of the switching transistor SW and the driving transistor DR shown in fig. 8 are obtained. Specifically, in the first doping process, boron ions are doped into the first channel region 132 and the second channel region 142 simultaneously by ion implantation, the concentration of the boron ions being 5×10≡11/cm 2 Thereby obtaining an I-V curve S1 of the switching transistor SW after doping and an I-V curve D1 of the driving transistor DR after the first doping. In order to contrast, the second doping of the first channel region 132 is provided with a different concentration of boron ions, and in the second doping process of the first group, only boron ions are doped into the first channel region 132 by ion implantation, wherein the concentration of boron ions is 3 x 10≡11/cm 2 Obtaining a first group of driving transistor DR curves D21 and a first group of switching transistor SW curves S21; in a second doping process of the second group, only boron ions are doped into the first channel region 132 by ion implantation, the boron ions having a concentration of 5 x 10≡11/cm 2 A second set of drive transistor DR curves D22 and a second set of switch transistor SW curves S22 are obtained. The threshold voltage of the switching transistor SW corresponding to the curve S1 is VS1, the threshold voltage of the switching transistor SW corresponding to the first group of switching transistor SW curve S21 is VS21, the threshold voltage of the switching transistor SW corresponding to the second group of switching transistor SW curve S22 is VS22, the threshold voltage of the driving transistor DR corresponding to the curve D1 is VD1, the threshold voltage of the driving transistor DR corresponding to the first group of driving transistor DR curve D21 is VD21, and the threshold voltage of the driving transistor DR corresponding to the second group of driving transistor DR curve D22 is VD22. As shown, vs1=vs21=vs22, since only the first channel region 132 is doped in the second doping process, the doping concentration of the second channel region 142 remains unchanged, and accordingly the threshold voltage of the switching transistor SW remains unchanged; VD1 <VD21，VD1<VD22, it can be seen that the second doping of the driving transistor DR can shift the threshold voltage of the driving transistor DR forward; VD21<VD22, it can be seen that as the doping concentration of the second doping process increases, the threshold voltage forward shift of the driving transistor DR also increases accordingly.
It can be seen that, the corresponding arrangement of the embodiment of the present disclosure can maintain the threshold voltage of the switching transistor SW unchanged on the premise of realizing the forward shift of the threshold voltage of the driving transistor DR, so that the bright spot caused by the forward shift of the threshold voltage of the switching transistor SW can be avoided on the premise of reducing the afterimage and reducing the power consumption.
In the process of forming the transistor, the active layer portions located at two sides of the channel region need to be subjected to conductive treatment, specifically, the active layer portions located at two sides of the channel region can be subjected to conductive treatment by doping (e.g., ion implantation) to form a source region and a drain region of the transistor, and on the premise that the doping concentration of the formed source region and drain region is far greater than that of the channel region, the transistor can have higher implantation efficiency (i.e., emission efficiency). Therefore, referring to fig. 3 and 6, for example, the doping concentration of the first channel region 132 is set to be smaller than the doping concentrations of the first source region 131 and the first drain region 133, and the doping concentration of the second channel region 142 is set to be smaller than the doping concentrations of the second source region 141 and the second drain region 143, so that it is possible to ensure that both the driving transistor DR and the switching transistor SW have higher injection efficiency. Specifically, when the transistor is a PMOS transistor, the source region and the drain region of the transistor are both P-doped, whereas when the transistor is an NMOS transistor, N-doped is performed. For example, the switch transistor SW and the driving transistor DR are PMOS transistors, the doping types of the first source region 131, the first drain region 133, the second source region 141 and the second drain region 143 are the same, and are P-type doping, boron ions can be doped into the semiconductor substrate by ion implantation, and the doping concentration of the boron ions can be 8×10≡14/cm 2 ～1*10^15/cm 2 Between them. When the transistor types in the pixel driving circuit 120 are identical (i.e., are PMOS or NMOS transistors), the source and drain regions of the transistors may be formed by a single doping process, and the doping concentrations of the source and drain regions of the transistors may be the same. Illustratively, the doping types of the first channel region 132, the first source region 131, the first drain region 133, the second channel region 142, the second source region 141, and the second drain region 143 are the same, and the doping ions may be the same, for example, boron ions. The doping concentrations of both the first channel region 132 and the second channel region 142 are much less than those of the first channel regionThe doping concentrations of the source region 131, the first drain region 133, the second source region 141 and the second drain region 143 are low-doped to adjust the forward shift degree of the threshold voltages of the driving transistor DR and the switching transistor SW due to the low doping of the first channel region 132 and the second channel region 142; and the first source region 131, the first drain region 133, the second source region 141, and the second drain region 143 are heavily doped, so that the source region and the drain region of the transistor can be electrically conductive.
Since the doping concentration of the source region and the drain region is far greater than that of the first channel region 132 and the second channel region 142, the doping concentration of the first channel region 132 and the second channel region 142 is negligible compared to that of the source region and the drain region, when the active layer pattern is formed, the first active layer 130 and the second active layer 140 may be lightly doped directly, and then the first active layer 130 and the second active layer 140 may be heavily doped directly by the doping process to form the first source region 131, the first drain region 133, the second source region 141 and the second drain region 143, and at this time, the doping concentration of the first source region 131 and the first drain region 133 is greater than that of the second source region 141 and the second drain region 143.
Further embodiments of the present disclosure provide a method for manufacturing a pixel driving circuit, which can be used to manufacture the pixel driving circuit as described in any one of the foregoing embodiments. Referring to fig. 9, the method for manufacturing the pixel driving circuit includes:
s101, forming a semiconductor pattern on a substrate by using a semiconductor base material.
Illustratively, the semiconductor substrate may be low temperature polysilicon. Referring to fig. 10A, a low temperature polysilicon may be deposited on a substrate 210 using a method such as coating, magnetron sputtering, thermal evaporation, or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, abbreviated as PECVD) to form a semiconductor layer 220.
After forming the semiconductor layer using the semiconductor substrate, illustratively, referring to fig. 10B, the semiconductor layer 220 may be patterned through one patterning process (e.g., a yellow light process) to form the semiconductor pattern 230. Wherein the patterning process refers to a process capable of forming at least one pattern having a certain shape, the patterning step may include: coating photoresist, exposing, developing, etching, stripping photoresist, and the like.
Illustratively, referring to fig. 10B, the semiconductor pattern 230 includes at least one (e.g., one) first initial channel region 231B and first initial source and drain regions 231a and 231c located at both sides of the first initial channel region 231B, respectively, and at least one (e.g., a plurality of) second initial channel regions 232B and second initial source and drain regions 232a and 232c located at both sides of the second initial channel region 232B, respectively.
S102, doping the semiconductor pattern 230 to obtain a doped semiconductor pattern.
Specifically, referring to fig. 10D, the doped semiconductor pattern 250 has a first channel region 251b of a driving transistor (not shown) and a second channel region 252b of a switching transistor (not shown), and first transition source regions 251a and 251c located at both sides of the first channel region 251b, respectively, and second transition source regions 242a and 242c located at both sides of the second channel region 252b, respectively. The first channel region 251b is formed by the first initial channel region 231b through a doping process, the second channel region 252b is formed by the second initial channel region 232b through a doping process, the first transitional source region 251a and the first transitional drain region 251c are formed by the first initial source region 231a and the first initial drain region 231c through a doping process, and the second transitional source region 242a and the second transitional drain region 242c are formed by the second initial source region 232a and the second initial drain region 232c through a doping process, respectively. Since the semiconductor substrates of the first initial channel region 231b and the second initial channel region 232b are low-temperature polysilicon, the semiconductor substrates of the first channel region 251b and the second channel region 252b obtained by doping the first initial channel region 231b and the second initial channel region 232b respectively are the same. Illustratively, boron ions may be doped into the semiconductor substrate of the first initial channel region 231b and the second initial channel region 232b by ion implantation, so that the doping types of the first channel region 251b and the second channel region 252b are the same, and the doping concentration of the first channel region 251b is set to be greater than the doping concentration of the second channel region 252 b.
Illustratively, referring to fig. 11, doping the semiconductor pattern 230 to obtain a doped semiconductor pattern 250 includes:
s201, performing first doping on the semiconductor pattern 230 to obtain an initially doped semiconductor pattern.
Illustratively, referring to FIG. 10C, the semiconductor pattern 230 may be entirely doped by ion implantation, wherein the implanted ions are boron ions, the ion beam has an energy level of 10KeV and a doping concentration of 5 x 10≡11/cm 2 ～8*10^11/cm 2 . Specifically, the initially doped semiconductor pattern 240 has a first intermediate channel region 241b of a driving transistor (not shown) and a second channel region 242b of a switching transistor (not shown), and a first intermediate source region 241a and a first intermediate drain region 241c respectively located at both sides of the first intermediate channel region 241b, and a second transition source region 242a and a second transition drain region 242c respectively located at both sides of the second channel region 242 b. Wherein the first intermediate channel region 241b is formed by the first initial channel region 231b through the first doping, the first intermediate source region 241a and the first intermediate drain region 241c are formed by the first initial source region 231a and the first initial drain region 231c through the first doping, and the second transition source region 242a and the second transition drain region 242c are formed by the second initial source region 232a and the second initial drain region 232c through the first doping, respectively.
S202, performing second doping on the portion of the initially doped semiconductor pattern 240 corresponding to the first channel region 251b, so as to obtain a doped semiconductor pattern 250.
Referring to FIG. 10D, boron ions can be implanted into only the first middle channel region 241b and the first middle source region 241a and the first middle drain region 241c respectively located at both sides of the first middle channel region 241b by ion implantation, wherein the ion beam has an energy level of 10KeV and a doping concentration of 3 x 10≡11/cm 2 ～5*10^11/cm 2 A doped semiconductor pattern 250 is obtained. In the doped semiconductor pattern 250The first channel region 251b is formed by the second doping of the first intermediate channel region 241b, and the first transitional source region 251a and the first transitional drain region 251c are formed by the second doping of the first intermediate source region 241a and the first intermediate drain region 241c, respectively. For example, referring to fig. 12, the portion of the initially doped semiconductor pattern 240 except for the first channel region 251b (i.e., the first middle channel region 241b in the drawing) may be masked by a metal mask, and then the portion of the initially doped semiconductor pattern 240 corresponding to the first channel region 251b may be doped a second time, and the metal mask may be made of a metal material such as molybdenum, chromium, etc. having high rigidity and strength to completely isolate the implanted ions, so that the metal mask has a simpler structural design since only the corresponding portion of the first channel region 251b needs to be exposed. For another example, a portion of the initially doped semiconductor pattern 240 corresponding to the second channel region 242b may be masked with a metal mask, and then a portion of the initially doped semiconductor pattern 240 other than the second channel region 242b may be secondarily doped. Also for example, the second doping of the first intermediate channel region 241b may be achieved by forming a mask (e.g., a photomask) capable of exposing the first channel region 251b (i.e., the first intermediate channel region 241b in the drawing) on the initially doped semiconductor pattern 240, and the photomask may be subsequently removed by an ashing process and/or a stripping process.
Through the preparation process steps S201 to S202, the doping concentration of the first channel region 251b and the doping concentration of the second channel region 242b can be set, respectively, and the doped semiconductor pattern 250 in which the doping concentration of the first channel region 251b is greater than the doping concentration of the second channel region 242b can be obtained. In combination with the foregoing, the doping concentration of the first channel region 251b of the driving transistor is set to be greater than the doping concentration of the second channel region 242b of the switching transistor, so that the first channel region 251b has a relatively stable carrier concentration, and it is ensured that the threshold voltage offset of the driving transistor is relatively uniform, and the variation amplitude of the on-current of different driving transistors is relatively uniform, so that short-term afterimages caused by different threshold voltage offsets can be avoided, and the display effect is improved. Meanwhile, the threshold voltage of the driving transistor can be shifted forward, and the driving transistor is easier to be started after the voltage is applied, so that the power consumption is reduced. In addition, the doping concentrations of the first channel region 251b and the second channel region 242b are respectively set, so that synchronous forward shift of the threshold voltage of the switching transistor and the threshold voltage of the driving transistor can be avoided, the forward shift degree of the threshold voltage of the switching transistor is ensured to be smaller, and the risk of occurrence of bright spots is reduced.
S103, forming an active pattern layer comprising a first active layer and a second active layer.
Illustratively, referring to fig. 10E, portions of the doped semiconductor pattern 250 except for the first channel region 251b and the second channel region 242b may be doped to form a first source region 261a and a first drain region 261b, a second source region 262a and a second drain region 262c, resulting in first and second active layers 261 and 262, and an active pattern layer 260 including the first and second active layers 261 and 262. For example, referring to fig. 10E, the gate insulating layers and the gate layers of the driving transistor and the switching transistor may be formed first, so that the respective gate layers of the driving transistor and the switching transistor may serve as masks to block the first channel region 251b and the second channel region 242b, and then boron ions may be implanted into the first transition source region 251a, the first transition drain region 251c, the second transition source region 242a and the second transition drain region 242c by ion implantation to form the first source region 261a and the first drain region 261c, the second source region 262a and the second drain region 262c, and finally the first active layer 261 and the second active layer 262 may be obtained. Wherein, in the doping process for forming the source region and the drain region, the doping concentration can be 8 x 10≡14/cm 2 ～1*10^15/cm 2 Between them. For another example, doping of portions other than the first and second channel regions 251b and 242b may also be achieved by forming a mask (e.g., a photomask) capable of blocking the first and second channel regions on the doped semiconductor pattern layer, and after forming the first and second source regions 261a and 261c, the second source region 262a and the second drain region 262c, the photomask may be removed by an ashing process and/or a stripping process.
Illustratively, after forming the first active layer 261 and the second active layer 262, the fabrication process of the pixel driving circuit (not shown in the drawings) may further include forming a gate insulating layer, a gate layer, an interlayer insulating layer, and source and drain layers disposed in this order on a side of the active pattern layer (including the first active layer 261 and the second active layer 262) away from the substrate 210, and finally fabricating the pixel driving circuit.
The materials and shapes of the layers and the positional relationship between each other prepared by the preparation method can refer to the above-described embodiments of the pixel driving circuit, and the same technical effects can be produced, which are not described herein.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A pixel driving circuit, comprising:
a driving transistor including a first active layer having a first channel region, a first source region, and a first drain region; the doping concentration of the first channel region is smaller than the doping concentrations of the first source region and the first drain region; a switching transistor coupled with the driving transistor, the switching transistor including a second active layer having a second channel region, a second source region, and a second drain region; the doping concentration of the second channel region is smaller than the doping concentrations of the second source region and the second drain region;
the second channel region and the semiconductor substrate of the first channel region are the same in doping type, the doping concentration of the first channel region is greater than that of the second channel region, and the doping concentration of the first channel region is 1.375-2 times that of the second channel region;
the width-to-length ratio of the first channel region is smaller than that of the second channel region; the width of the first channel region is equal to the width of the second channel region, and the length of the first channel region is greater than the length of the second channel region.
2. The pixel driving circuit according to claim 1, wherein,
the doping concentration of the second channel region is 5 x 10≡11/cm 2 ～8*10^11/cm 2 The doping concentration of the first channel region is 3 x 10 x 11/cm greater than that of the second channel region 2 ～5*10^11/cm 2 。
3. The pixel driving circuit according to claim 1, wherein,
the ions doped in the first channel region and the second channel region are any one of boron ions, aluminum ions, gallium ions, and indium ions.
4. A pixel driving circuit according to any one of claims 1 to 3, wherein,
the semiconductor substrate is polysilicon.
5. An array substrate comprising the pixel driving circuit according to any one of claims 1 to 4.
6. A display device comprising the array substrate according to claim 5.
7. A method of manufacturing a pixel drive circuit according to claim 1, the pixel drive circuit comprising a drive transistor and a switching transistor coupled to the drive transistor, the method of manufacturing a pixel drive circuit comprising:
forming a semiconductor pattern on a substrate using a semiconductor substrate;
Doping the semiconductor pattern to obtain a doped semiconductor pattern, wherein the doped semiconductor pattern is provided with a first channel region of the driving transistor and a second channel region of the switching transistor;
the semiconductor substrate of the first channel region and the semiconductor substrate of the second channel region are the same, the doping type is the same, and the doping concentration of the first channel region is larger than that of the second channel region.
8. The method of manufacturing a pixel driving circuit according to claim 7, wherein doping the semiconductor pattern to obtain a doped semiconductor pattern comprises:
performing first doping on the semiconductor pattern to obtain an initial doped semiconductor pattern;
and carrying out second doping on the part corresponding to the first channel region in the initial doped semiconductor pattern to obtain the doped semiconductor pattern.
9. The method of manufacturing a pixel driving circuit according to claim 8, wherein performing second doping on a portion of the initially doped semiconductor pattern corresponding to the first channel region to obtain the doped semiconductor pattern comprises:
and shielding the part except the first channel region in the initial doped semiconductor pattern by utilizing a metal mask plate, and carrying out second doping on the part corresponding to the first channel region in the initial doped semiconductor pattern.
10. The method for manufacturing a pixel driving circuit according to claim 7, further comprising:
and doping parts of the doped semiconductor pattern except the first channel region and the second channel region to form an active pattern layer including a first source region and a first drain region of the driving transistor, and a second source region and a second drain region of the switching transistor.
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