CN113725226A

CN113725226A - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN113725226A
Application number: CN202111003076.6A
Authority: CN
Inventors: 张坤; 周文犀; 刘威; 夏志良
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-08-30
Filing date: 2021-08-30
Publication date: 2021-11-30
Anticipated expiration: 2041-08-30
Also published as: CN113725226B

Abstract

The application provides a three-dimensional memory and a manufacturing method thereof, wherein the method comprises the following steps: forming a peripheral circuit on one side of a semiconductor substrate; forming a sacrificial layer and a stacked structure on the other opposite side of the semiconductor substrate, wherein the stacked structure comprises a core region which comprises a plurality of channel structures penetrating through the stacked structure and extending to the semiconductor substrate; forming a gate gap penetrating through the stacked structure and extending into the sacrificial layer; and replacing the sacrificial layer with a conductive layer via the gate gap to electrically connect the plurality of channel structures. According to the three-dimensional memory provided by the application, the peripheral circuit, the semiconductor layer and the memory stacking structure are formed on two opposite sides of the same semiconductor substrate, so that the integration level of the device is improved; in addition, when the SWNN structure is formed, the part of the semiconductor substrate, in which the peripheral circuit is embedded, is separated from the part of the SWNN structure to be formed, so that the adaptability of the SWNN structure is improved.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology. In particular, the present application relates to a three-dimensional memory and a method of manufacturing the same.

Background

In a conventional three-dimensional memory manufacturing process, the peripheral circuits and the memory array (referred to as a "memory stack structure" herein) are usually formed on different substrates and then directly bonded in a face-to-face or back-to-back manner. The above manufacturing process has the following problems:

on the one hand, as the structure of the three-dimensional memory is continuously developed to a high layer number and a high density, the formation of the peripheral circuit and the memory stack structure on different substrates reduces the area utilization rate of the three-dimensional memory, thereby being not beneficial to improving the integration level of the device.

On the other hand, when the memory stack structure and the peripheral circuit are directly bonded, the bonding contacts of the memory stack structure and the peripheral circuit need to be aligned and bonded one by one, the distribution of the bonding contacts is limited by the memory structure, and the required accuracy of alignment is high.

It is to be appreciated that this background section is intended in part to provide a useful background for understanding the technology, however, it is not necessary for these matters to be within the knowledge or understanding of those skilled in the art prior to the filing date of the present application.

Disclosure of Invention

In order to solve the above problems, an aspect of the present application provides a semiconductor device manufacturing method, including: forming a peripheral circuit on one side of a semiconductor substrate; and forming a memory array on the other opposite side of the semiconductor substrate.

In one embodiment of the present application, forming the memory array includes: forming a sacrificial layer and a stacked structure corresponding to the peripheral circuit on the other opposite side of the semiconductor substrate, wherein the stacked structure comprises a core region including a plurality of channel structures penetrating through the stacked structure and extending to the semiconductor substrate; forming a gate gap extending through the stack structure and into the sacrificial layer; and replacing the sacrificial layer with a conductive layer via the gate gap to electrically connect the plurality of channel structures.

In one embodiment of the present application, after forming the peripheral circuit, an etch stop layer is formed on the semiconductor substrate and the peripheral circuit; and forming a second dielectric layer on the etching stop layer.

In one embodiment of the present application, forming the peripheral circuit includes: forming an isolation structure in the semiconductor substrate to define at least one active region; and forming at least one peripheral circuit device in the at least one active region to form the peripheral circuit.

In one embodiment of the present application, a semiconductor layer is formed on the sacrificial layer after the sacrificial layer is formed and before the stack structure is formed.

In one embodiment of the present application, the semiconductor substrate includes an N-type doped region, and the forming the stack structure includes: forming a stacked layer on the semiconductor layer; and forming the plurality of channel structures penetrating through the stacked layers and extending into the N-type doped region.

In one embodiment of the present application, forming the channel structure includes: forming the plurality of channel holes penetrating through the stacked layers and extending into the N-type doped region; and forming a storage film and a semiconductor channel on the side wall and the bottom of the channel hole.

In one embodiment of the present application, the stacked structure includes a step region located at least one side of the core region and a peripheral region located at least another side opposite to the step region, and the forming the stacked structure further includes: and filling the step region and the peripheral region with a first dielectric layer, wherein the top surface of the first dielectric layer is not lower than the top of the channel structure.

In one embodiment of the present application, forming the gate gap includes: removing a portion of the semiconductor layer along sidewalls of the gate gap to form a lateral recess; simultaneously depositing an insulating layer on the side wall of the gate gap and in the groove; and removing the insulating layer from the sidewalls of the gate gap.

In one embodiment of the present application, replacing the sacrificial layer with the conductive layer comprises: removing the sacrificial layer to form a cavity between the semiconductor layer and the semiconductor substrate; removing a portion of the storage film to expose a portion of the semiconductor channel along the sidewall; and depositing N-type doped polysilicon in the cavity to form the conductive layer.

In one embodiment of the present application, the method further comprises: forming an isolation layer along the side wall of the gate gap; and forming a conductive via on the isolation layer.

In one embodiment of the present application, the method further comprises: forming a word line contact in the step area; forming a first contact extending into the semiconductor substrate in the peripheral region; forming a first interconnect layer on the first dielectric layer that interconnects the word line contact and the first contact; and forming a through contact in the semiconductor substrate in contact with the first contact.

In one embodiment of the present application, the method further comprises: forming a first pad extraction layer on the first interconnect layer, including a first pad contact formed in a first passivation layer; wherein a top portion of the first pad contact is exposed from the first passivation layer to draw the word line contact and the first contact through the first interconnect layer.

In one embodiment of the present application, the method further comprises: forming a third dielectric layer on the second dielectric layer; forming a second contact point which is contacted with the through contact point and a third contact point which is contacted with the peripheral circuit in the third dielectric layer; and forming a second interconnect layer on the third dielectric layer that interconnects the second contact and the third contact.

In one embodiment of the present application, the method further comprises: forming a second pad extraction layer on the second interconnect layer, including a second pad contact formed in a second passivation layer; wherein a top portion of the second pad contact is exposed from the second passivation layer to bring the second and third contacts out through the second interconnect layer.

Based on the same inventive concept, another aspect of the present application provides a three-dimensional memory, including: a semiconductor substrate; a peripheral circuit structure located at one side of the semiconductor substrate; and a memory array located on the opposite side of the semiconductor substrate.

In one embodiment of the present application, the memory array comprises: a conductive layer on the opposite side of the semiconductor substrate; and a memory stack structure disposed on the conductive layer, the memory stack structure including a core region including a plurality of channel structures extending through the memory stack structure and to the semiconductor substrate; wherein the conductive layer is electrically connected to a portion of sidewalls of the plurality of channel structures.

In one embodiment of the present application, the semiconductor substrate further comprises an N-type doped region; wherein the channel structure extends into the N-type doped region.

In one embodiment of the present application, the conductive layer comprises an N-type doped semiconductor layer; the N-type doped semiconductor layer comprises N-type doped polycrystalline silicon.

In one embodiment of the present application, the storage stack structure includes: a stepped region located at least one side of the core region; a peripheral region located at least one opposite side of the stepped region; and a first dielectric layer filling the step region and the peripheral region and making a top surface of the first dielectric layer not lower than at least a top of the channel structure.

In one embodiment of the present application, the three-dimensional memory further comprises: an etch stop layer formed on the semiconductor substrate and the peripheral circuit; the second dielectric layer covers the etching stop layer; and a semiconductor layer disposed between the conductive layer and the storage stack structure.

In one embodiment of the present application, the peripheral circuit includes: an isolation structure formed in the semiconductor substrate to define at least one active region; and at least one peripheral circuit device formed in the at least one active region.

In one embodiment of the present application, the storage stack structure further comprises: a gate gap structure including an isolation layer on sidewalls of a gate gap and a conductive via on the isolation layer.

In one embodiment of the present application, the channel structure includes: a plurality of channel holes penetrating through the storage stack structure and extending into the N-type doped region; and a storage film and a semiconductor channel formed on the sidewall and bottom of the channel hole; wherein a portion of the memory film is removed such that the conductive layer is electrically connected with a portion of the semiconductor channel along the sidewall.

In one embodiment of the present application, the three-dimensional memory further comprises: word line contacts passing through the step regions; a first contact extending through the peripheral region and into the semiconductor substrate; a through contact in the semiconductor substrate and in contact with the first contact; and a first interconnect layer on the first dielectric layer and interconnected with the word line contact and the first contact.

In one embodiment of the present application, the three-dimensional memory further comprises: a first pad extraction layer on the first interconnect layer including a first pad contact disposed in a first passivation layer; wherein a top portion of the first pad contact is exposed from the first passivation layer to draw the word line contact and the first contact through the first interconnect layer.

In one embodiment of the present application, the three-dimensional memory further comprises: the third dielectric layer is positioned on the second dielectric layer; the second contact and the third contact are arranged in the third dielectric layer and are respectively in electric contact with the through contact and the peripheral circuit; and a second interconnect layer on the third dielectric layer and interconnected with the second contact and the third contact.

In one embodiment of the present application, the three-dimensional memory further includes a second pad extraction layer on the second interconnect layer, including a second pad contact disposed in the second passivation layer; wherein a top portion of the second pad contact is exposed from the second passivation layer to bring the second and third contacts out through the second interconnect layer.

In one embodiment of the present application, the three-dimensional memory is configured to generate a gate-induced-drain-leakage (GIDL) assisted body bias when performing an erase operation.

The peripheral circuit and the memory stacking structure of the three-dimensional memory are formed on the same semiconductor substrate, so that the area utilization rate and the integration level of the three-dimensional memory are improved. In addition, the manufacturing method does not need additional bonding steps, and further does not need to consider the distribution of bonding contacts in the interconnection structure of the three-dimensional memory, so that the interconnection structure can be simplified, and the integration level of the three-dimensional memory is further improved.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings, there is shown in the drawings,

FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a semiconductor substrate provided with a method of fabricating a three-dimensional memory according to one embodiment of the present application;

fig. 3 is a schematic cross-sectional view after forming a peripheral circuit and a second dielectric layer on one side of a semiconductor substrate according to a method of manufacturing a three-dimensional memory according to an embodiment of the present application;

FIG. 4 is a partially enlarged schematic diagram of the peripheral circuit of FIG. 2;

fig. 5 is a schematic cross-sectional view after forming a sacrificial layer, a semiconductor layer, and a stacked layer on the other side of a substrate according to a method of manufacturing a three-dimensional memory according to an embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming a channel structure;

FIG. 7 is a schematic cross-sectional view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming a step region;

FIG. 8 is a cross-sectional schematic view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming a dummy channel and a gate gap;

FIG. 9 is a schematic cross-sectional view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after replacing a sacrificial layer with a conductive layer;

fig. 10 is a cross-sectional view of a method of fabricating a three-dimensional memory according to an embodiment of the present application after forming a gate layer and a gate gap structure;

FIG. 11 is a cross-sectional schematic view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming a word line contact, a first contact, and a first interconnect layer;

FIG. 12 is a cross-sectional schematic view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming through silicon contacts;

FIG. 13 is a cross-sectional schematic view of a method of fabricating a three-dimensional memory according to one embodiment of the present application after forming second contacts, third contacts, and a second interconnect layer;

FIG. 14 is a cross-sectional schematic view of a three-dimensional memory according to one embodiment of the present application.

Fig. 15 is a schematic view illustrating an arrangement of step regions and core regions in a method of fabricating a three-dimensional memory according to an embodiment of the present application;

fig. 16 is a schematic view illustrating another arrangement of step regions and core regions in a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification.

Note that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" but also includes the meaning of "on" and having intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" but also can include the meaning of "above" or "over" and having no intermediate features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire superstructure or understructure, or may have a smaller extent than the understructure or superstructure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

A three-dimensional (3D) memory refers to a semiconductor memory having a vertically oriented string of memory cell transistors (referred to herein as a "memory stack structure") on a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate, as used herein, the term "stacking direction" refers to a direction nominally perpendicular to the substrate.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

The application provides a manufacturing method of a three-dimensional memory, which comprises the following steps: peripheral circuitry is formed on one side of a semiconductor substrate and a memory array is formed on an opposite side of the semiconductor substrate. Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application, where S2-S4 are methods of forming a memory array. As shown in fig. 1, a method 1000 of fabricating a three-dimensional memory includes:

s1: forming a peripheral circuit on one side of a semiconductor substrate;

s2: forming a sacrificial layer and a stacked structure on the other opposite side of the semiconductor substrate, the stacked structure including a core region including a plurality of channel structures extending through the stacked structure and to the semiconductor substrate;

s3: forming a gate gap extending through the stack structure and into the sacrificial layer;

s4: replacing the sacrificial layer with a conductive layer via the gate gap to connect the plurality of channel structures.

The above-mentioned steps S1-S4 will be described below with reference to schematic diagrams of respective stages of a method of manufacturing a three-dimensional memory shown in fig. 2-16, respectively. In describing the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not partially enlarged in general scale for convenience of illustration, and the diagrams are merely examples, which should not limit the scope of protection of the present application. In addition, a three-dimensional space ruler with length, width and depth is required in actual manufacturing. It should be understood that the operations shown in the method are not exhaustive and that other operations may be performed before, after, or in between any of the operations described.

S1：

As shown in fig. 2, the method for manufacturing a three-dimensional memory according to the present application starts with a semiconductor substrate 101, and the material for manufacturing the semiconductor substrate 101 may be any suitable semiconductor material, for example, a iii-v compound such as single crystal silicon, polycrystalline silicon, single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide.

In some embodiments, the semiconductor substrate 101 may be a doped polysilicon substrate, for example, a P-type doped polysilicon or an N-type doped polysilicon substrate; an N-type doped region (also referred to as an "N-well") and/or a p-type doped region (also referred to as a "p-well") may also be included in the semiconductor substrate 101, and when the semiconductor substrate 101 is an N-type doped polysilicon substrate, the N-type doped region may be any suitable portion thereof. It should be understood that the doping type and doping concentration of the semiconductor substrate 101 of the present application can be selected according to actual needs.

As shown in fig. 3, the semiconductor substrate 101 may have opposite sides, a direction perpendicular to the semiconductor substrate 101 denotes a Z direction, a first horizontal direction parallel to the semiconductor substrate 101 denotes an X direction, a second horizontal direction parallel to the semiconductor substrate 101 denotes a Y direction, and the first horizontal direction and the second horizontal direction are perpendicular to each other. The symbol of the combination of a circle and a cross is shown in the vicinity of the letter "Y", indicating that the Y direction in the figure is directed inward with respect to the drawing page of the figure.

As shown in fig. 3, the peripheral circuit 102 is formed on one side of the substrate, and the peripheral circuit 102 may be partially formed in the semiconductor substrate 101 or partially extend out of the semiconductor substrate 101 in the Z direction. In the 3D memory device, the peripheral circuit 102 is employed to perform logic operations and control and detect the switching state of each memory cell string through metal connection to realize storage and reading of data. The peripheral circuit 102 may include peripheral circuit devices, which may include, for example, high voltage devices for controlling high voltage signals and/or low voltage devices for improving read and write speeds, which may be composed of, for example, MOS transistors. As shown in fig. 3, in some embodiments, three adjacent high voltage devices 102-1, 102-2 and 102-3 may be used as a first high voltage device group and be spaced apart from a second high voltage device group consisting of three other adjacent high voltage devices 102-4, 102-5 and 102-6, and the first high voltage device group and the second high voltage device group together constitute a symmetric peripheral circuit. It should be understood that the peripheral circuit 102 provided herein may include any number and combination of structures for high voltage devices, low voltage devices, groups of high voltage devices, groups of low voltage devices, and any combination thereof.

As shown in fig. 4, peripheral circuitry 102 includes shallow trench isolation structures 1025 that may be used to isolate adjacent semiconductor devices, such as adjacent high voltage devices, and may also be used to define active regions. The step of forming the shallow trench isolation structure 1025 may include forming an opening in the semiconductor substrate 101 and filling with an insulating material. In some embodiments, the opening may be formed by an etching process, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, and the like, and the insulating material may be filled by a deposition process. The deposition process may include, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and combinations of any of the foregoing. The deposition process may also include a High density plasma chemical vapor deposition (HDP-CVD) process. The HDP process has excellent hole filling property, can reduce the generation of voids, and can fill gaps with large aspect ratio at relatively low temperature to densify the deposited film, and the cost is lower than that of the ALD deposition process.

In some embodiments, the filled insulating material includes one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and an oxynitride (e.g., silicon oxynitride) material. Alternatively, the top surface of the insulating material may be planarized using Chemical Mechanical Polishing (CMP).

As shown in fig. 4, the peripheral circuit 102 further includes, for example, a gate, a source, and a drain of the high-voltage device and/or the low-voltage device; taking the source and drain formation step of the high voltage device 102-5 as an example, the step may include ion doping the active region to form two lightly doped regions; ion implantation of the two lightly doped regions may continue after any suitable step to form, for example, the source 1023 or the drain 1022 of the MOS transistor.

As shown in fig. 4, taking the step of forming the gate of the high voltage device 102-5 as an example, the step may include forming a gate dielectric layer 1024 on the surface of the lightly doped region and the shallow trench isolation structure 1025 to separate the gate 1021 from the source 1023 and the drain 1022 of the MOS transistor. In some embodiments, the gate dielectric layer 1024 may include an oxide layer, which may be formed using a deposition process such as thermal oxidation, ALD, PVD, or CVD. Subsequently, a gate 1021 may be formed at a corresponding position on the surface of the gate dielectric layer 1024, the gate 1021 may be formed by a deposition process such as ALD, PVD, CVD, HDP-CVD, and the like, and the material of the gate 1021 may include polysilicon.

Referring to fig. 3 and 4, as an option, an etch stop layer 1026 may be formed on the semiconductor substrate 101 and the peripheral circuit 102 after the gate 1021 is formed, and a material for the etch stop layer 1026 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant dielectric material such as aluminum oxide or hafnium oxide, or the like. The possible subsequent etching process performed on the peripheral circuit 102 may be stopped at the etching stop layer 1026 to avoid the over-etching phenomenon from affecting the performance of the memory.

Referring again to fig. 3 and 4, in some embodiments, second dielectric layer 103 may be formed on etch stop layer 1026 covering peripheral circuitry 102 after forming etch stop layer 1026. The second dielectric layer 103 has a thickness that can isolate the peripheral circuit 102 from the outside and protect the peripheral circuit 102 from damage caused by subsequent processes. The material of the second dielectric layer 103 comprises silicon oxide, silicon nitride and silicon oxynitride, and any combination thereof, and the second dielectric layer 103 is formed by any suitable deposition process, such as CVD, PVD or ALD, and any combination thereof. Alternatively, the top surface of the second dielectric layer 103 (the surface away from the semiconductor substrate 101) may be subjected to a chemical mechanical polishing process (Buffer CMP) such as a low polishing rate to achieve planarization.

S2：

As shown in fig. 5, in some embodiments, a sacrificial layer 104 is formed on a side (opposite side) of the conductor substrate 101 facing away from the peripheral circuit 102, the sacrificial layer 104 may include a first barrier layer 104-1, a sub-sacrificial layer 104-3, and a second barrier layer 104-2 formed in sequence, and the material for the first barrier layer 104-1 and the second barrier layer 104-2 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant dielectric material such as aluminum oxide or hafnium oxide, and the like. Subsequent processing of sacrificial layer 104 may stop at barrier layers 104-1 and 104-2. The sub-sacrificial layer 104-3 may be formed by depositing polysilicon or any other suitable sacrificial material (e.g., carbon) that may be selectively removed later using one or more thin film deposition processes of CVD, PVD, ALD, or any combination thereof.

Alternatively, the semiconductor layer 113 may be formed on the sacrificial layer 104 after the sacrificial layer 104 is formed, and the semiconductor layer 113 may be formed by depositing any suitable semiconductor material (e.g., polysilicon) using one or more thin film deposition processes of CVD, PVD, ALD, or any combination thereof.

Referring again to fig. 5, after forming sacrificial layer 104 and semiconductor layer 113, a plurality of gate sacrificial layers 1051 and dielectric layers 1052 may be alternately formed on semiconductor layer 113 to form stacked layer 105. In some embodiments, gate sacrificial layer 1051 and dielectric layer 1052 have a higher etch selectivity ratio during the same etch process to ensure that dielectric layer 1052 is hardly removed when gate sacrificial layer 1051 is subsequently removed and replaced with a conductive material. Exemplary materials for forming gate sacrificial layer 1051 and dielectric layer 1052 may include silicon nitride and silicon oxide, respectively.

As shown in fig. 6 and 7, stack 105 may include a core region 106 and a stepped region 108 on at least one side of core region 106 and a peripheral region 109 on at least one side of stepped region 108 opposite core region 106. Fig. 7 shows a schematic cross-sectional structure with stepped regions 109 on both sides of the core region 106, and fig. 15 shows a schematic top view of the arrangement of the core region and the stepped regions in fig. 7, wherein the peripheral region 109 is not shown. In some embodiments, as shown in fig. 16, the stepped region 108 may be located on one side of the core region 106, that is, the stepped region 108 may be flanked by the core region.

In one embodiment of the present application, as shown in fig. 6, a plurality of channel structures 107 of the three-dimensional memory may be formed in the core region 106, and the plurality of channel structures 107 may extend through the stacked layer 105 and into the semiconductor substrate 101; alternatively, when the semiconductor substrate 101 includes an N-type doped region, the plurality of channel structures 105 may extend to the N-type doped region.

In some embodiments, the step of forming the channel structure 107 may include: a plurality of channel holes (not shown in fig. 6) are first formed through the stack and extending into the semiconductor layer 101 in the core region 106. Alternatively, when the semiconductor substrate 101 includes an N-type doped region, the plurality of channel holes may extend to the N-type doped region. The channel hole may be formed by, for example, a dry etching process or a combination of dry and wet etching processes. Illustratively, the channel hole may have a cylindrical or columnar shape in the direction of extension.

After the channel hole is formed, a channel structure 107 including a memory film 107-1 and a semiconductor channel 107-2 may be sequentially formed at the sidewall and the bottom of the channel hole. In some embodiments, the storage film 107-1 includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on the sidewalls and bottom of the channel hole. Wherein the blocking layer may reduce leakage of charge and the storage layer may trap charge that may tunnel into the semiconductor channel 107-2 via the tunneling layer and be transported in the semiconductor channel 107-2. The semiconductor channel 107-2 may be, for example, polysilicon, for facilitating charge transport.

In some embodiments, the material for the barrier layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide; materials for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, and the like. Materials for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric materials such as aluminum oxide or hafnium oxide, and the like. Alternatively, the semiconductor channel 107-2 and the memory film 107-1 may include a silicon-oxide-nitride-oxide (SONO) structure.

Illustratively, the memory film 107-1 and the semiconductor channel 107-2 may be formed in the channel hole by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In some embodiments, a dielectric layer may be filled in the remaining space of the channel hole and a channel plug may be formed on the top of the channel hole away from the semiconductor substrate 101 after the formation of the memory film 107-1 and the semiconductor channel 107-2.

As shown in fig. 7, the stepped region 108 includes a stepped structure, and an edge portion of each gate sacrificial layer 1051 of the stepped structure is exposed with respect to the gate sacrificial layer 1051 thereabove. The stepped structure may be formed by performing a set of processing steps on stack 105, which may include, for example, an etching process. In one embodiment, a buffer layer covering the top surface and sidewalls of the steps may be formed on the step structure, and the buffer layer may be formed on the top surface and sidewalls of each step of the step structure by one or more deposition processes, including CVD, PVD, ALD, or any combination thereof.

For example, the first dielectric layer 114 may be formed after the step region is formed and filled in the step region 108 and the peripheral region 109, and the first dielectric layer 114 may serve as a support structure when other processes are subsequently performed in the step region 108 and the peripheral region 109. The material of the first dielectric layer 114 may include silicon oxide, silicon nitride, and silicon oxynitride, and any combination thereof, and may be formed by any suitable deposition process, including, for example, CVD, PVD, or ALD, and combinations thereof. Alternatively, the top surface of the first dielectric layer 114 may be planarized using, for example, a lower polish rate CMP process to make the top surface of the first dielectric layer 114 at least no lower than the top of the channel structure 107.

As shown in fig. 8, after the step region is formed, a dummy channel 111 penetrating the stack layer 105 may be formed on the step structure, the dummy channel having no memory function, and the formation process is similar to that of the channel structure 107. For example, the dummy channel hole may be filled with a dielectric material after formation of the dummy channel hole, in order to provide structural support in subsequent operations of replacing the gate sacrificial layer 1051.

For convenience of description and distinction from the stack layer 105, the semiconductor structure over the semiconductor layer 113 on the other side of the semiconductor substrate 101 may be collectively referred to as a stack structure after forming the first dielectric layer 114 or forming the dummy channel 111. Illustratively, the stacked structure may be disposed on opposite sides of the semiconductor substrate 101 corresponding to the peripheral circuit 102, and alternatively, the core region 106 and the step region 108 of the stacked structure may be disposed corresponding to the peripheral circuit 102.

S3：

As shown in fig. 8, a gate gap 110 may be formed in the core region 106 through the stacked structure (or stacked layer 105) and extending to the top surface of the sacrificial layer 104 away from the semiconductor substrate 101, either before or after the dummy channel 111 is formed. Illustratively, the gate gap 110 may be formed using an anisotropic dry etching process, such as an ion mill etching, plasma etching, reactive ion etching, laser ablation, or the like. The etching is stopped near the top surface of sacrificial layer 104 by controlling the etching time.

In some embodiments, etching of a portion of the semiconductor layer 113 may continue along the sidewalls of the gate gap 110 in a direction parallel to the semiconductor substrate 101 to form a recess. The recess has a larger lateral dimension in a direction parallel to the semiconductor substrate 101 than the gate gap 110, which may increase the process window for operating at the bottom of the gate gap 110. The recess may be formed by a suitable etching process, such as a dry etching or wet process.

After the recess is formed, an insulating layer 115 is formed by a suitable deposition process in the recess and sidewalls of the gate gap 110. The deposition process may include, for example, CVD, PVD, ALD, and combinations of any of the foregoing deposition processes. The material of insulating layer 115 may be the same as the material of dielectric layer 1052. The insulating layer 115 may then be removed from the sidewalls of the gate gap 110, leaving a portion of the insulating layer 115 in the recess. In some embodiments, the insulating layer 115 of the sidewall can be removed by an etching process such as ion milling etching, plasma etching, reactive ion etching, laser ablation, and the like. As shown in fig. 9, the insulating layer 115 in the recess isolates the semiconductor layer 114 from the external environment, and protects the semiconductor layer 114 from being affected during the subsequent process operation on the sacrificial layer 104.

S4：

As shown in fig. 9, the sacrificial layer 104 is replaced with a conductive layer 104' via the gate gap 110 so that a plurality of semiconductor channels 107-2 can be electrically connected through the sidewalls of the channel structure 107. In some embodiments, in order to replace the sacrificial layer 104 with the conductive layer 104', the sacrificial layer 104 may be first removed to form a cavity between the semiconductor layer 113 and the semiconductor substrate 101, then a portion of the memory film 107-1 is removed to expose a portion of the semiconductor channel 107-2 along the sidewall of the channel hole, and a conductive material is deposited into the cavity to form the conductive layer 104'. Alternatively, the conductive material may comprise N-type doped polysilicon, such that the conductive layer 104' is formed as an N-type doped semiconductor layer. Illustratively, to deposit N-doped polysilicon into the cavity, the polysilicon may be in-situ doped to fill the cavity with a uniform doping concentration profile.

In some embodiments, the cavity may be formed by removing sacrificial layer 104 (shown in fig. 8) by wet etching and/or dry etching. Taking wet etching as an example, a tetramethylammonium hydroxide (TMAH) etchant may be applied to etch sacrificial layer 104 through gate gap 110. On one hand, since the semiconductor layer 113 forms a groove along the sidewall of the gate gap 110 and the insulating layer 115 is filled in the groove, the etchant can be isolated from the semiconductor layer 113, thereby preventing the etchant from etching the semiconductor layer 113. On the other hand, the first barrier layer 104-1 and the second barrier layer 104-2 define the etching range of the sacrificial layer 104, that is, the etching of the sacrificial layer 104 may be stopped at the interfaces of the first barrier layer 104-1 and the second barrier layer 104-2 and the sub-sacrificial layer 104-3.

In some embodiments, the exposed portion of the storage film 107-1 in the cavity can be removed to expose a portion of the semiconductor channel 107-2 along the sidewall of the channel hole. In some embodiments, portions of the blocking layer (e.g., comprising silicon oxide), the charge trapping layer (e.g., comprising silicon nitride), and the tunneling layer (e.g., comprising silicon oxide) are etched via the gate gap 110 and the cavity by applying an etchant (e.g., phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide). The etching may stop at the first barrier layer 104-1, the second barrier layer 104-2, and the semiconductor channel 107-2.

In some embodiments, a conductive material may be deposited into the cavity via the gate gap 110 using one or more film deposition processes (such as CVD, PVD, ALD, or any combination thereof) to form a conductive layer 104' in contact with the exposed portions of the semiconductor channel 107-2. According to some embodiments, the topography (e.g., cleanliness) of the semiconductor trench, 107-2 does not affect the formation of the conductive layer 104 'since the conductive layer 104' is formed by deposition as opposed to epitaxial growth from the semiconductor trench 107-2.

Referring again to fig. 9, the conductive layer 104' may directly contact the semiconductor channel 107-2 (sidewall "SEG") from the sidewalls of the channel hole, as compared to conventional etching of the SONO structure at the bottom of the channel hole and selective epitaxial growth of silicon (bottom "SEG") to electrically connect the semiconductor channel 107-2. Therefore, the risk of SONO etching caused by the increase of the layer number, such as etching through holes, large alignment margin (alignment margin), large pressure change and the like, can be reduced, and the process window of the 3D memory is increased. When the channel structure 107 extends into the N-type doped region and the conductive layer 104' is N-type polysilicon, the sidewall "SEG" forms a SWNN (Side Wall N-poly/N-Sub) structure. In some embodiments, the SWNN (Side Wall N-poly/N-Sub) structure may generate a gate-induced-drain-leakage (GIDL) assisted body bias voltage when performing an erase operation on the 3D memory device, and is therefore also referred to as a "GIDL erase".

In addition, when the peripheral circuit 102 is formed on the same side of the stacked structure, especially when the peripheral circuit 102 includes high voltage devices, the isolation structure between the high voltage devices extending into the semiconductor substrate 101 will prevent the SWNN structure from being formed. According to the SWNN structure, the peripheral circuit, the semiconductor layer and the storage stacking structure are formed on two opposite sides of the semiconductor substrate, and when the SWNN structure is formed, the part, deep into the peripheral circuit, of the semiconductor substrate is isolated from the part, to be formed, of the SWNN structure, so that the adaptability of the SWNN structure is improved.

As shown in fig. 10, after replacing the sacrificial layer 104 with the conductive layer 104', the replacement of the gate sacrificial layer 1051 with the gate layer 1051' via the gate gap 110 may continue. Illustratively, the gate sacrificial layer 1051 can be removed by applying an etchant through the gate gaps 110 to form a plurality of lateral recesses, and then the gate layer 1051' can be deposited into the lateral recesses by depositing one or more conductive materials using one or more film deposition processes (such as PVD, CVD, ALD, or any combination thereof), which can include, for example, tungsten.

Referring again to fig. 10, after the gate sacrificial layer 1051 is replaced with the gate layer 1051, a gate gap structure 110' may be formed in the gate gap 110. In some embodiments, spacers (not shown) may be formed along sidewalls of the gate gaps 110 and a conductive material may be filled on the spacers to form conductive vias (not shown). Wherein the isolation layer may comprise an insulating material, and may be used to electrically isolate adjacent memory cells; the fill layer may include a conductive material and may serve as an extraction channel for the common source line electrical connection.

The peripheral circuit 102 and the stacked structure are formed on two opposite sides of the same semiconductor substrate 101, heat generated in the processes of the step region 108, the channel structure 107, the gate gap structure 110' and the like is transferred to the peripheral circuit 102 through the excellent heat transfer effect of the semiconductor substrate 101, conductive particles doped in a source electrode and a drain electrode in a high-voltage device can be annealed to realize thermal activation, and the heat utilization rate in the preparation process of the memory device can be improved.

As shown in fig. 11-13, a connection structure for the memory stack structure to transfer electrical signals to and from peripheral circuits, such as a word line contact 112, a first contact 119, a first interconnect layer 116, a through silicon contact 118, a second interconnect layer 117, etc., may be formed after the gate gap structure 110' is formed.

Referring to fig. 11, openings for the first contact 119 and the word line contact 112 may be formed in the peripheral region 109 and the step region 108, respectively, by, for example, a dry etching process or a combination of dry and wet etching processes; the opening can then be filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material filling the opening may comprise, for example, tungsten, cobalt, copper, aluminum, and any combination thereof. In some embodiments, another conductive material (e.g., titanium nitride TiN) may be deposited in the opening as a contact layer prior to depositing the conductive material.

In some embodiments, a first interconnect layer 116, which may be a back-end-of-line (BEOL) structure, may be formed on the first dielectric layer 114 to interconnect the word line contacts 112 and the first contacts 119.

Referring to fig. 12, in an embodiment, a Through silicon contact 118 (TSC) penetrating into the semiconductor layer 113 may be formed from the same side of the semiconductor substrate 101 as the peripheral circuit 102, and a forming process of the TSC may be the same as the word line contact 112 and the first contact 119, which is not described herein. The TSC may be in electrical contact with a first contact 119 extending into the semiconductor layer 113 for routing electrical signals, and an insulating shield may also be formed on the sidewalls of the TSC to reduce the coupling effect of the TSC to adjacent devices.

Referring to fig. 13, a third dielectric layer 103 'may be formed on the second dielectric layer 103, and the material of the third dielectric layer 103' may be the same as that of the second dielectric layer 103, which is not described herein again. A second contact to the TSC and a third contact to the active area of the peripheral circuitry 102 may be formed in the third dielectric layer 103'. The formation process of the third contact may be the same as for the word line contact 112 and the first contact 119, wherein the opening of the third contact may stop at the etch stop layer 1026 on the source, drain and gate. In some embodiments, a second interconnect layer 117 may be formed on the third dielectric layer 103' to interconnect the second and third contacts. The second interconnect layer 117 may be a back-end-of-line (BEOL) structure.

Alternatively, a first pad extraction layer may be formed on the first interconnect layer 116, including a first passivation layer and a first pad contact formed in the first passivation layer. Wherein the first passivation layer may serve as an outermost layer for passivating and protecting the 3D memory, the top of the first pad contact may be exposed from the first passivation layer to lead the word line contact 112 and the first contact 119 out through the first interconnect layer 116. The first pad contact may comprise a conductive material, which may be included in, for example, W, Co, Cu, Al, silicide, and any combination thereof.

Alternatively, a second pad extraction layer 200 (shown in fig. 14) may be formed on the second interconnect layer 117, including a second passivation layer and a second pad contact formed therein, wherein a top portion of the second pad contact may expose the second passivation layer to extract the second and third contacts through the second interconnect layer 117. The materials of the second passivation layer and the second pad contact may be the same as those of the first passivation layer and the first pad contact, respectively, and are not described herein again. It should be understood that the first pad drawing layer and the second pad drawing layer may be formed only one of them, and may also be formed on the first interconnect layer 116 and the second interconnect layer 117 at the same time.

Embodiments of the present application further provide a three-dimensional memory 100 including a semiconductor substrate, peripheral circuits on one side of the semiconductor substrate, and a memory array on an opposite side of the semiconductor substrate. As shown in fig. 14, in some examples, the three-dimensional memory 100 includes: a semiconductor substrate 101, a peripheral circuit structure 102', a conductive layer 104', and a storage stack structure 105 '; the peripheral circuit structure 102' and the memory stack structure 105' are disposed on opposite sides of the semiconductor substrate 101, the conductive layer 104' is formed on the semiconductor substrate 101, and the memory stack structure 105' is disposed on the conductive layer 104 '.

As shown in fig. 14, in one embodiment of the present application, a peripheral circuit structure 102' includes a peripheral circuit 102, an etch stop layer 1026, a second dielectric layer 103; wherein, an etching stop layer 1026 is formed on the peripheral circuit 102 and the semiconductor substrate 101, and the second dielectric layer 103 covers the etching stop layer 1026. The subsequent etching process performed on the peripheral circuit structure 102' to form the contact of the active region may stop at the etching stop layer 1026, thereby avoiding the over-etching phenomenon from affecting the performance of the memory. Alternatively, the second dielectric layer 103 may have a thickness to isolate the peripheral circuit 102 from the outside and protect the peripheral circuit 102 from damage caused by subsequent processes. Illustratively, the material of the second dielectric layer 103 includes silicon oxide, silicon nitride, and silicon oxynitride, and any combination thereof.

In one embodiment of the present application, the peripheral circuit 102 may include peripheral circuit devices, which may include, for example, a high voltage device for controlling a high voltage signal and a low voltage device for improving a read/write speed, and the high voltage device and the low voltage device may be composed of, for example, MOS transistors. In some embodiments, the plurality of adjacent high-voltage devices may be arranged as a first high-voltage device group and spaced apart from a second high-voltage device group consisting of a plurality of adjacent high-voltage devices, and the first high-voltage device group and the second high-voltage device group together constitute a symmetric peripheral circuit. It should be understood that the peripheral circuit structure 102' provided herein may include any number and combination of structures for high voltage devices, low voltage devices, groups of high voltage devices, groups of low voltage devices, and any combination thereof.

Illustratively, peripheral circuitry 102 includes shallow trench isolation structures 1025 to define active regions where high voltage devices and/or low voltage devices may be formed. Peripheral circuit 102 also includes gates, sources and drains for high voltage devices and/or low voltage devices, and a gate dielectric layer separating the sources and drains from the gates.

As shown in fig. 14, in one embodiment of the present application, the memory stack structure 105' includes a core region 106, a terrace region 108, and a peripheral region 109, the terrace region 108 being located on at least one side of the core region 106, the peripheral region 109 being located on at least another opposite side of the terrace region 108; in some embodiments, the core region 106 has stepped regions 109 on both sides, and in other embodiments, the stepped regions 108 may be located on one side of the core region 106, that is, the stepped regions 108 may be core regions on both sides. For example, the core region 106 may include a plurality of channel structures 107 extending through the memory stack structure 105 'and into the semiconductor substrate 101, and the conductive layer 104' is electrically connected to a portion of sidewalls of the plurality of channel structures 107.

In some embodiments, the semiconductor substrate 101 may be a doped polysilicon substrate, for example, may be a P-type doped polysilicon or an N-type doped polysilicon substrate; an N-type doped region (also referred to as an "N-well") and/or a p-type doped region (also referred to as a "p-well") may also be included in the semiconductor substrate 101, and when the semiconductor substrate 101 is an N-type doped polysilicon substrate, the N-type doped region may be any suitable portion thereof.

As shown in fig. 14, in one embodiment of the present application, the channel structure 107 includes a memory film 107-1 and a semiconductor channel 107-2 sequentially formed on the sidewall and the bottom of the channel hole; in some embodiments, the storage film 107-1 includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed on the sidewalls and bottom of the channel hole. Wherein the blocking layer may reduce leakage of charge and the storage layer may trap charge that may tunnel into the semiconductor channel 107-2 via the tunneling layer and be transported in the semiconductor channel 107-2. The semiconductor channel 107-2 may comprise a semiconductor material, such as polysilicon, for facilitating charge transport.

In some examples, a portion of the storage film 107-1 is exposed such that a portion of the semiconductor channel 107-2 along the sidewall of the channel hole contacts the conductive layer 104' to enable electrical connection of the plurality of channels. Illustratively, the conductive layer 104 'includes an N-type doped semiconductor layer, and when the N-type doped semiconductor layer is N-type doped polysilicon and the channel structure 107 extends into the N-type doped region, the conductive layer 104' forms an SWNN (Side Wall N-poly/N-Sub) structure. In some embodiments, the SWNN (Side Wall N-poly/N-Sub) structure may generate a gate-induced-drain-leakage (GIDL) assisted body bias when performing an erase operation on the 3D memory device, and is therefore also referred to as a "GIDL erase".

As shown in fig. 14, in one embodiment of the present application, memory stack structure 105' further forms alternating gate layers 1051' and dielectric layers 1052 in core region 106 and mesa region 108, with gate layers 1051' forming memory cells where they intersect with memory channel 107. In some embodiments, the memory stack structure 105 'further includes a dummy channel 111 formed in the step region 108, the dummy channel having no memory function and providing structural support when forming the gate layer 1051'.

As shown in fig. 14, in one embodiment of the present application, the memory stack structure 105 'further includes a semiconductor layer 113 and a gate gap structure 110'. Wherein the semiconductor layer 113 may be disposed between the conductive layer 104 'and the storage stack structure 105'; the gate gap structure 110' may include an isolation layer (not shown) formed on sidewalls of the gate gap and a conductive via (not shown) formed on the isolation layer. Wherein the isolation layer may comprise an insulating material, and may be used to electrically isolate adjacent memory cells; the fill layer may include a conductive material and may serve as an extraction channel for the common source line electrical connection.

In one embodiment of the present application, referring to fig. 14, the storage stack structure 105' further includes a first dielectric layer 114 filling the step region 108 and the peripheral region 109, the top surface of which is at least not lower than the top of the channel structure for supporting structures for other processes subsequently performed on the step region 108 and the peripheral region 109. Illustratively, the material of the first dielectric layer 114 includes silicon oxide, silicon nitride, and silicon oxynitride, and any combination thereof.

In one embodiment of the present application, referring to fig. 14, the three-dimensional memory 100 further includes a word line contact 112, a first contact 119, a through silicon contact 118, and a first interconnect layer 116. Wherein the word line contact 112 is formed in the stepped region 108, the first contact 119 is formed in the peripheral region 109 and extends into the semiconductor substrate 101, and the through silicon contact 118 is formed in the semiconductor substrate 101. Illustratively, the through silicon contact 118 may be in electrical contact with a first contact 119 that penetrates into the semiconductor layer 113 for drawing electrical signals out. To reduce the coupling effect of the TSC with adjacent devices, an insulating shielding layer may also be formed on the sidewalls of the TSC.

Illustratively, a first interconnect layer 116 may be formed on the first dielectric layer 114 and interconnected with the word line contacts 112 and the first contacts 119, which may alternatively be a back-end-of-line (BEOL) structure.

As shown in fig. 14, in one embodiment of the present application, the three-dimensional memory 100 further includes a third dielectric layer 103 'and second and third contacts formed in the third dielectric layer 103'; the third dielectric layer 103 'is formed on the second dielectric layer 103, and the material of the third dielectric layer 103' may be the same as that of the second dielectric layer 103, which is not described herein again. Illustratively, a second contact may be in contact with through silicon contact 118 to draw an electrical signal, and a third contact may be in contact with an active area of peripheral circuitry 102.

Illustratively, the second interconnect layer 117 may be formed on the third dielectric 103' and interconnected with the second contact and the third contact, and the second interconnect layer 117 may alternatively be a back-end-of-line (BEOL) structure.

Alternatively, the three-dimensional memory 100 further includes a first pad extraction layer that may be formed on the first interconnect layer 116, including a first passivation layer and a first pad contact formed in the first passivation layer. Wherein the first passivation layer may serve as an outermost layer for passivating and protecting the 3D memory, the top of the first pad contact may be exposed from the first passivation layer to lead the word line contact 112 and the first contact 119 out through the first interconnect layer 116. The first pad contact may comprise a conductive material, which may be included in, for example, W, Co, Cu, Al, silicide, and any combination thereof.

Alternatively, referring to fig. 14, the three-dimensional memory 100 may include a second pad extraction layer 200 formed on the second interconnection layer 117, including a second passivation layer and a second pad contact formed therein, wherein a top of the second pad contact may expose the second passivation layer to extract the second contact and the third contact through the second interconnection layer 117. The materials of the second passivation layer and the second pad contact may be the same as those of the first passivation layer and the first pad contact, respectively, and are not described herein again.

It should be understood that the first pad extraction layer and the second pad extraction layer described in the present application may be formed only on one of them, or may be formed on both the first interconnect layer 116 and the second interconnect layer 117.

The peripheral circuit and the memory stack structure of the conventional three-dimensional memory are usually formed on different substrates, so that the utilization area of the three-dimensional memory is increased, and the improvement of the integration level of the three-dimensional memory is not facilitated. In addition, an additional bonding step is required to align and bond the peripheral circuit and the memory stack structure, and the alignment accuracy is high.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of fabricating a three-dimensional memory, comprising:

forming a peripheral circuit on one side of a semiconductor substrate; and

a memory array is formed on the opposite side of the semiconductor substrate.

2. The method of manufacturing of claim 1, wherein forming the memory array comprises:

forming a sacrificial layer and a stacked structure corresponding to the peripheral circuit on the other opposite side of the semiconductor substrate, wherein the stacked structure comprises a core region including a plurality of channel structures penetrating through the stacked structure and extending to the semiconductor substrate;

forming a gate gap extending through the stack structure and into the sacrificial layer; and

replacing the sacrificial layer with a conductive layer via the gate gap to electrically connect the plurality of channel structures.

3. The manufacturing method according to claim 2, further comprising: after the formation of the peripheral circuits,

forming an etching stop layer on the semiconductor substrate and the peripheral circuit; and

and forming a second dielectric layer on the etching stop layer.

4. The manufacturing method according to claim 2, the forming the peripheral circuit comprising:

forming an isolation structure in the semiconductor substrate to define at least one active region; and

forming at least one peripheral circuit device in the at least one active region to form the peripheral circuit.

5. The manufacturing method according to claim 2, further comprising: forming a semiconductor layer on the sacrificial layer after forming the sacrificial layer and before forming the stack structure.

6. The method of manufacturing of claim 5, the semiconductor substrate comprising an N-type doped region, wherein forming the stack structure comprises:

forming a stacked layer on the semiconductor layer; and

forming the plurality of channel structures penetrating through the stack layer and extending into the N-type doped region.

7. The method of manufacturing of claim 6, wherein forming the channel structure comprises:

forming the plurality of channel holes penetrating through the stacked layers and extending into the N-type doped region; and

and forming a storage film and a semiconductor channel on the side wall and the bottom of the channel hole.

8. The method of manufacturing according to claim 2, the stacked structure including a stepped region on at least one side of the core region and a peripheral region on at least another side of the stepped region opposite, the forming the stacked structure further comprising:

and filling the step region and the peripheral region with a first dielectric layer, wherein the top surface of the first dielectric layer is not lower than the top of the channel structure.

9. The method of manufacturing of claim 7, wherein forming the gate gap comprises:

removing a portion of the semiconductor layer along sidewalls of the gate gap to form a lateral recess;

simultaneously depositing an insulating layer on the side wall of the gate gap and in the groove; and

and removing the insulating layer on the side wall of the gate gap.

10. The method of manufacturing of claim 9, wherein replacing the sacrificial layer with the conductive layer comprises:

removing the sacrificial layer to form a cavity between the semiconductor layer and the semiconductor substrate;

removing a portion of the storage film to expose a portion of the semiconductor channel along the sidewall; and

depositing N-type doped polysilicon within the cavity to form the conductive layer.

11. The manufacturing method according to claim 10, further comprising:

forming an isolation layer along the side wall of the gate gap; and

forming a conductive via on the isolation layer.

12. The manufacturing method according to claim 8, further comprising:

forming a word line contact in the step area;

forming a first contact extending into the semiconductor substrate in the peripheral region;

forming a first interconnect layer on the first dielectric layer that interconnects the word line contact and the first contact; and

forming a through contact in the semiconductor substrate in contact with the first contact.

13. The manufacturing method according to claim 12, further comprising:

forming a first pad extraction layer on the first interconnect layer, including a first pad contact formed in a first passivation layer; wherein a top portion of the first pad contact is exposed from the first passivation layer to draw the word line contact and the first contact through the first interconnect layer.

14. The manufacturing method according to any one of claims 12 or 13, further comprising:

forming a third dielectric layer on the second dielectric layer;

forming a second contact point which is contacted with the through contact point and a third contact point which is contacted with the peripheral circuit in the third dielectric layer; and

and forming a second interconnection layer on the third dielectric layer, wherein the second interconnection layer is interconnected with the second contact and the third contact.

15. The manufacturing method according to claim 13, further comprising:

forming a second pad extraction layer on the second interconnect layer, including a second pad contact formed in a second passivation layer; wherein a top portion of the second pad contact is exposed from the second passivation layer to bring the second and third contacts out through the second interconnect layer.

16. A three-dimensional memory, comprising:

a semiconductor substrate;

a peripheral circuit structure located at one side of the semiconductor substrate; and

and the memory array is positioned on the other opposite side of the semiconductor substrate.

17. The three-dimensional memory according to claim 16, wherein the memory array comprises:

a conductive layer on the opposite side of the semiconductor substrate; and

a memory stack structure disposed on the conductive layer, the memory stack structure including a core region including a plurality of channel structures extending through the memory stack structure and to the semiconductor substrate;

wherein the conductive layer is electrically connected to a portion of sidewalls of the plurality of channel structures.

18. The three-dimensional memory according to claim 17, wherein the semiconductor substrate further comprises an N-type doped region; wherein the channel structure extends into the N-type doped region.

19. The three-dimensional memory according to claim 18, wherein the conductive layer comprises an N-type doped semiconductor layer; the N-type doped semiconductor layer comprises N-type doped polycrystalline silicon.

20. The three-dimensional memory according to claim 17, wherein the storage stack structure comprises:

a stepped region located at least one side of the core region;

a peripheral region located at least one opposite side of the stepped region; and

and the first dielectric layer fills the step region and the peripheral region, and the top surface of the first dielectric layer is at least not lower than the top of the channel structure.

21. The three-dimensional memory of claim 20, further comprising:

an etch stop layer formed on the semiconductor substrate and the peripheral circuit;

the second dielectric layer covers the etching stop layer; and

a semiconductor layer disposed between the conductive layer and the storage stack structure.

22. The three-dimensional memory according to claim 17, wherein the peripheral circuit comprises:

an isolation structure formed in the semiconductor substrate to define at least one active region; and

at least one peripheral circuit device formed in the at least one active region.

23. The three-dimensional memory according to claim 17, wherein the storage stack structure further comprises: a gate gap structure including an isolation layer on sidewalls of a gate gap and a conductive via on the isolation layer.

24. The three-dimensional memory according to claim 18, wherein the channel structure comprises:

a plurality of channel holes penetrating through the storage stack structure and extending into the N-type doped region; and

the storage film and the semiconductor channel are formed on the side wall and the bottom of the channel hole;

wherein a portion of the memory film is removed such that the conductive layer is electrically connected with a portion of the semiconductor channel along the sidewall.

25. The three-dimensional memory of claim 21, further comprising:

word line contacts passing through the step regions;

a first contact extending through the peripheral region and into the semiconductor substrate;

a through contact in the semiconductor substrate and in contact with the first contact; and

a first interconnect layer on the first dielectric layer and interconnected with the word line contact and the first contact.

26. The three-dimensional memory of claim 25, further comprising:

a first pad extraction layer on the first interconnect layer including a first pad contact disposed in a first passivation layer; wherein a top portion of the first pad contact is exposed from the first passivation layer to draw the word line contact and the first contact through the first interconnect layer.

27. The three-dimensional memory of claim 25 or 26, further comprising:

the third dielectric layer is positioned on the second dielectric layer;

the second contact and the third contact are arranged in the third dielectric layer and are respectively in electric contact with the through contact and the peripheral circuit; and

and the second interconnection layer is positioned on the third dielectric layer and is interconnected with the second contact and the third contact.

28. The three-dimensional memory of claim 27, further comprising:

a second pad extraction layer on the second interconnect layer including a second pad contact disposed in the second passivation layer; wherein a top portion of the second pad contact is exposed from the second passivation layer to bring the second and third contacts out through the second interconnect layer.

29. The three-dimensional memory according to any one of claims 16-28, wherein the three-dimensional memory is configured to generate a gate-induced-drain-leakage (GIDL) assisted body bias voltage when performing an erase operation.