CN113725088B - Manufacturing method of chip packaging structure - Google Patents
Manufacturing method of chip packaging structure Download PDFInfo
- Publication number
- CN113725088B CN113725088B CN202010230888.3A CN202010230888A CN113725088B CN 113725088 B CN113725088 B CN 113725088B CN 202010230888 A CN202010230888 A CN 202010230888A CN 113725088 B CN113725088 B CN 113725088B
- Authority
- CN
- China
- Prior art keywords
- conductive
- layer
- conductive part
- forming
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920003023 plastic Polymers 0.000 claims abstract description 48
- 239000004033 plastic Substances 0.000 claims abstract description 48
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 247
- 229910052802 copper Inorganic materials 0.000 claims description 50
- 239000010949 copper Substances 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- 238000000465 moulding Methods 0.000 claims description 30
- 239000011241 protective layer Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 28
- 229920001940 conductive polymer Polymers 0.000 claims description 21
- 239000002131 composite material Substances 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 238000004049 embossing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000011368 organic material Substances 0.000 claims description 4
- 229910010272 inorganic material Inorganic materials 0.000 claims description 2
- 239000011147 inorganic material Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 43
- 239000000463 material Substances 0.000 description 37
- 239000002245 particle Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000007788 liquid Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 229920005989 resin Polymers 0.000 description 9
- 239000011347 resin Substances 0.000 description 9
- 239000012790 adhesive layer Substances 0.000 description 8
- 238000000227 grinding Methods 0.000 description 8
- -1 polybutylene terephthalate Polymers 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 7
- 239000007787 solid Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229920002577 polybenzoxazole Polymers 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 239000012785 packaging film Substances 0.000 description 4
- 229920006280 packaging film Polymers 0.000 description 4
- 239000005022 packaging material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229920000098 polyolefin Polymers 0.000 description 4
- 229920002635 polyurethane Polymers 0.000 description 4
- 239000004814 polyurethane Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 239000004734 Polyphenylene sulfide Substances 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229920000767 polyaniline Polymers 0.000 description 3
- 229920000069 polyphenylene sulfide Polymers 0.000 description 3
- 229920000128 polypyrrole Polymers 0.000 description 3
- 229920000123 polythiophene Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000005038 ethylene vinyl acetate Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920002521 macromolecule Polymers 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001707 polybutylene terephthalate Polymers 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- 241001133184 Colletotrichum agaves Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a manufacturing method of a chip packaging structure, wherein an electric connector is arranged on a bare chip, the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, the second conductive part comprises a first sub-conductive part and a second sub-conductive part, and the first conductive part is electrically connected to the back surface of the bare chip; the bare chip and the electric connecting piece are encapsulated by a first plastic encapsulation layer, and the first conductive part, the second conductive part and the active surface of the bare chip of the electric connecting piece are exposed outside the first plastic encapsulation layer; the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer are provided with a circuit layer, the circuit layer comprises a rewiring layer, part of the rewiring layer is electrically connected with the first sub-conductive part and the first inner bonding pad, and part of the rewiring layer is electrically connected with the second sub-conductive part and the back grounding inner bonding pad. The back surface grounding at the specific electric connection point position of the active surface of the bare chip is realized by using the electric connector. Heat can be dissipated at the heat-generating region on the active side of the die where heat is easily accumulated.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a manufacturing method of a chip packaging structure.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly miniaturized, intelligent, high-performance and high-reliability. The packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product. In a power chip (power module), it is necessary to back ground specific electrical connection point locations of the active surface of the die.
In view of the above, the present invention provides a new method for manufacturing a chip package structure for packaging a power chip.
Disclosure of Invention
The invention aims to provide a manufacturing method of a chip packaging structure for packaging a power chip.
In order to achieve the above object, the present invention provides a method for manufacturing a chip package structure, including:
providing a carrier plate and a plurality of bare chips, wherein each bare chip comprises an active surface and a back surface which are opposite, and the active surface is provided with a first inner bonding pad, a second inner bonding pad and a protective layer which covers the first inner bonding pad and the second inner bonding pad; the first inner bonding pad is positioned in a heating area of the bare chip, and the second inner bonding pad at least comprises one back grounding inner bonding pad; fixing the active surface of each bare chip on the carrier plate;
Providing a plurality of electric connectors, wherein the electric connectors comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, and the second conductive part comprises a first sub-conductive part and a second sub-conductive part; each electric connector is arranged on each bare chip, the first conductive part is electrically connected to the back surface of each bare chip, and the second conductive part is arranged on the surface of the carrier plate;
forming a first plastic sealing layer which is used for embedding each bare chip and each electric connecting piece on the surface of the carrier plate; thinning the first plastic sealing layer until the first conductive parts of the electric connecting pieces are exposed; removing the carrier plate;
forming a circuit layer on the active surface of each bare chip, the second conductive part of each electric connector and the first plastic sealing layer to form a packaging intermediate structure containing a plurality of bare chips, wherein the circuit layer comprises a rewiring layer, a part of the rewiring layer is electrically connected with the first sub-conductive part and the first inner bonding pad, and a part of the rewiring layer is electrically connected with the second sub-conductive part and the back grounding inner bonding pad;
and cutting the packaging intermediate structure to form a plurality of chip packaging structures, wherein each chip packaging structure comprises a bare chip.
Optionally, a plurality of electrical connectors are provided disposed on a first support plate.
Optionally, the first conductive part, the connecting part and the first sub-conductive part of the electrical connector are in an H shape; and/or the first conductive part, the connecting part and the second sub-conductive part of the electric connector are H-shaped; and/or the electrical connection is formed by at least one of cutting, stamping, etching, embossing; and/or the first sub-conductive part comprises two or more.
Optionally, the method further comprises: and forming a first oxidation resistant layer on the first conductive part of each electric connecting piece exposing the first plastic sealing layer.
Optionally, forming a circuit layer on the active surface of each of the dies, the second conductive portion of each of the electrical connectors, and the first molding layer includes:
forming the rewiring layer on the first inner bonding pad, the second inner bonding pad, the protective layer, the first plastic sealing layer between the bare chips and the second conductive part of the electric connector;
and forming a conductive stud on the rewiring layer.
Optionally, the rewiring layer comprises two or more layers, and/or the rewiring layer is a fan-out line.
Optionally, the method further comprises: and forming a solder ball on the conductive convex column, wherein the solder ball is an outer pin.
Optionally, the method further comprises: and forming a second oxidation resistance layer on the conductive convex column.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer on the conductive convex columns and between the adjacent conductive convex columns, wherein the second dielectric layer is made of inorganic materials;
the second dielectric layer is polished until the conductive stud is exposed.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive stud on the metal block of the rewiring layer;
and forming a second dielectric layer between adjacent conductive convex columns, wherein the upper surface of the second dielectric layer is flush with the upper surface of the conductive convex column, and the second dielectric layer is made of an organic material.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a second dielectric layer on the rewiring layer;
forming a plurality of third openings in the second dielectric layer, the third openings exposing the metal blocks of the rewiring layer;
forming a conductive material layer on the second dielectric layer and in the third opening;
And polishing the conductive material layer until the second dielectric layer is exposed, wherein the conductive material layer in the third opening forms a conductive convex column.
Optionally, forming the conductive stud on the rewiring layer includes:
forming a conductive convex column on the metal block of the rewiring layer, and forming a second plastic sealing layer embedding the conductive convex column on the rewiring layer;
and thinning the second plastic sealing layer until the conductive convex columns are exposed.
Optionally, a conductive layer is disposed on the back surface of the die, and/or a conductive adhesive is disposed between the first conductive portion and the back surface of the die.
Optionally, the conductive paste comprises a nano copper/conductive polymer composite.
Optionally, in the nano copper/conductive polymer composite, the conductive polymer is: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide, and/or the particle size of the nano copper is less than 800nm.
Optionally, the particle size of the nano copper ranges from 200nm to 500nm.
Optionally, the material of the protective layer is at least one of insulating resin material, silicon dioxide and silicon nitride. The protection layer can play an insulating role, and in the process of forming the first plastic sealing layer and grinding the first plastic sealing layer, the hardness can be enough to protect the first inner bonding pad, the second inner bonding pad and the electric interconnection structure in the bare chip from being damaged, and the invention is not limited to the specific material of the protection layer.
Optionally, in the step of fixing the active surface of each die to the carrier, the protective layer has a plurality of first openings therein, a part of the first openings expose a partial area of the first inner pad, and a part of the first openings expose a partial area of the second inner pad; or forming a first opening in the protective layer in the step of forming the circuit layer, wherein part of the first openings expose part of areas of the first inner bonding pads, and part of the first openings expose part of areas of the second inner bonding pads.
Compared with the prior art, the invention has the beneficial effects that:
arranging an electric connector on the bare chip, wherein the electric connector comprises a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, the second conductive part comprises a first sub-conductive part and a second sub-conductive part, the first conductive part is electrically connected to the back surface of the bare chip, and the second conductive part and the active surface of the bare chip are basically in the same plane; the bare chip and the electric connecting piece are encapsulated by a first plastic encapsulation layer, and the first conductive part, the second conductive part and the active surface of the bare chip of the electric connecting piece are exposed outside the first plastic encapsulation layer; the active surface of the bare chip, the second conductive part of the electric connector and the first plastic sealing layer are provided with a circuit layer, the circuit layer comprises a rewiring layer, part of the rewiring layer is electrically connected with the first sub-conductive part and the first inner bonding pad, and part of the rewiring layer is electrically connected with the second sub-conductive part and the back grounding inner bonding pad. The back surface grounding at the specific electric connection point position of the active surface of the bare chip is realized by using the electric connector. In addition, the first conductive part of the electric connector is exposed outside the chip packaging structure, and heat in a heating area where heat is easily accumulated on the active surface of the bare chip can be dissipated, so that the heat dissipation performance of the chip is improved, the continuous and efficient operation of the chip can be ensured, and the problem of service life influence caused by overheat of the chip can be solved.
Drawings
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
FIG. 2 is a top view of an electrical connector;
FIG. 3 is a flow chart of a method of fabricating the chip package structure of FIG. 1;
fig. 4 to 15 are schematic views of intermediate structures corresponding to the flow in fig. 3;
fig. 16 is a top view of an electrical connector in a method for manufacturing a chip package structure according to a second embodiment of the present invention.
To facilitate an understanding of the present invention, all reference numerals appearing in the present invention are listed below:
die 11 electrical connector 12
Die active side 11a die back side 11b
First inner pad 110a and second inner pad 110b
The first opening 111a of the protection layer 111
First conductive portion 12a of first molding layer 10
Second conductive portion 12b connecting portion 12c
The first sub-conductive part 120a and the second sub-conductive part 120b
Outer pin 13a of circuit layer 13
Second molding layer 133 of metal block 131a
Second oxidation resistant layer 134 of conductive stud 132
First antioxidation layer 121 chip package structure 1a
Carrier plate 2 packaging intermediate structure 1
First support plate 3 second support plate 4
First dielectric layer 131b second dielectric layer 132b
Rewiring layer 131 backside ground inner pad 110c
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 1 is a schematic cross-sectional view of a chip package structure according to a first embodiment of the present invention.
Referring to fig. 1, a chip package structure 1a includes:
a die 11, the die 11 including an active surface 11a and a back surface 11b opposite to each other, the active surface 11a having a first inner pad 110a, a second inner pad 110b, and a protective layer 111, the first inner pad 110a being located at a heat generating area of the die 11, the second inner pad 110b including at least one back ground inner pad 110c; the protective layer 111 has a plurality of first openings 111a, a part of the plurality of first openings 111a exposing a partial region of the first inner pad 110a, and a part of the plurality of first openings 111a exposing a partial region of the second inner pad 110 b;
an electrical connector 12, the electrical connector 12 includes a first conductive portion 12a, a second conductive portion 12b, and a connecting portion 12c connecting the first conductive portion 12a and the second conductive portion 12b, the second conductive portion 12b includes a first sub-conductive portion 120a and a second sub-conductive portion 120b; the first conductive portion 12a is electrically connected to the back surface 11b of the die 11;
A first molding layer 10 that encapsulates the die 11 and the electrical connection member 12, and the first conductive portion 12a, the second conductive portion 12b, and the active surface 11a of the die 11 of the electrical connection member 12 are exposed outside the first molding layer 10;
a circuit layer 13, wherein the circuit layer 13 is positioned on the active surface 11a of the bare chip 11, the second conductive part 12b of the electric connector 12 and the first plastic sealing layer 10; the circuit layer 13 includes a rewiring layer 131, wherein a part of the rewiring layer 131 electrically connects the first sub-conductive part 120a and the first inner pad 110a, and a part of the rewiring layer 131 electrically connects the second sub-conductive part 120b and the back grounding inner pad 110c.
The die 11 may include a variety of devices formed on a semiconductor substrate and electrical interconnect structures electrically connected to the respective devices. The second inner pad 110b of the die active surface 11a is connected to an electrical interconnect structure for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110c is for electrical connection with the back surface 11b of the die 11. Die 11 may be a power chip. The first inner pad 110a may be located near a channel region of the power chip.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride. Examples of the insulating resin material include polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), and the like.
Fig. 2 is a top view of an electrical connector. Referring to fig. 2, the electrical connector 12 includes a first conductive portion 12a and four second conductive portions 12b. Of the four second conductive portions 12b, three are first sub-conductive portions 120a and one is a second sub-conductive portion 120b. The first conductive portion 12a, the connection portion 12c, and the first sub-conductive portion 120a of the electrical connector 12 are rectangular in plan view. The first conductive portion 12a, the connection portion 12c, and the second sub-conductive portion 120b of the electrical connector 12 are also rectangular in plan view. In other embodiments, the second conductive portion 12b may include at least one first sub-conductive portion 120a and one second sub-conductive portion 120b.
Referring to fig. 1, the electrical connector 12 is convex in vertical cross section for receiving the die 11. The material of the electrical connector 12 may be a metal with good electrical conductivity and a certain hardness, such as copper. A first oxidation preventing layer 121 may be disposed on the first conductive part 12a exposed outside the first molding layer 10.
In the embodiment shown in fig. 1, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c may be obtuse angles.
In some embodiments, a conductive paste may be disposed between the first conductive portion 12a and the back surface 11b of the die 11 to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, the first conductive portion 12a may be in direct contact with the back surface 11b of the die 11 to make electrical connection therebetween.
In some embodiments, the backside 11b of the die 11 may also be provided with a conductive layer. The material of the conductive layer may be copper. A titanium layer may also be provided between the copper layer and the back surface 11b of the die 11 to improve adhesion between the back surface 11b of the die and the copper layer.
In the embodiment shown in fig. 1, there is no gap between the connection portion 12c of the electrical connector 12 and the die 11, and in other embodiments, there may also be a gap between the two, so that the first plastic sealing layer 10 enters, thereby improving the connection firmness between the electrical connector 12 and the die 11.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like.
The rewiring layer 131 is a fan-out line (fan-out).
In the embodiment shown in fig. 1, the rewiring layer 131 includes a metal block 131a and a second molding layer 133 between adjacent metal blocks 131a, with one layer. In other embodiments, the rewiring layer 131 may include two or more layers. Among the plurality of metal blocks 131a, in addition to electrically connecting the second sub-conductive part 120b with the back ground inner pad 110c, and electrically connecting the first sub-conductive part 120a with the first inner pad 110a, a part of the plurality of metal blocks 131a are electrically connected with one or more second inner pads 110b for achieving other functions, and/or a part of the plurality of metal blocks 131a are electrically connected with one or more first inner pads 110a.
In the embodiment shown in fig. 1, the conductive stud 132 is the outer lead 13a. The conductive stud 132 may be made of a metal such as copper, and may have a second oxidation resistant layer 134 thereon. In other embodiments, solder balls may be disposed on the conductive studs 132, and the solder balls are the outer pins 13a.
Referring to fig. 1, the chip package structure 1a implements the rear surface 11b grounding at a specific electrical connection point position (rear ground inner pad 110 c) of the die active surface 11a by using the electrical connector 12. In addition, the first conductive part 12a of the electrical connector 12 is exposed outside the chip packaging structure 1a, and the heat in the heating area where the heat is easily accumulated on the active surface 11a of the bare chip can be dissipated, so that the heat dissipation performance of the chip is improved, the continuous and efficient operation of the chip can be ensured, and the problem of service life influence caused by overheat of the chip can be solved.
An embodiment of the present invention provides a method for manufacturing the chip package structure 1a in fig. 1. Fig. 3 is a flow chart of a method of fabrication. Fig. 4 to 15 are schematic views of intermediate structures corresponding to the flow in fig. 3.
First, referring to step S1 in fig. 3, fig. 4 and fig. 5, a carrier 2 and a plurality of dies 11 are provided, each die 11 includes an active surface 11a and a back surface 11b, the active surface 11a has a first inner pad 110a, a second inner pad 110b, and a protective layer 111 covering the first inner pad 110a and the second inner pad 110b, the first inner pad 110a is located in a heat-generating area of the die 11, and the second inner pad 110b includes at least one back-grounded inner pad 110c; the active surface 11a of each die 11 is fixed to the carrier plate 2. Wherein fig. 4 is a top view of a carrier plate and a plurality of dies; fig. 5 is a cross-sectional view taken along line AA in fig. 4.
The die 11 is formed for a singulated wafer including a wafer active side having inner pads 110 and an insulating layer (not shown) protecting the inner pads 110, and a wafer back side. The die 11 is formed after dicing, and accordingly, the die 11 includes a die active surface 11a and a die backside surface 11b, the die active surface 11a having an inner pad 110 and an insulating layer protecting the inner pad 110. The protective layer 111 is applied on the active surface 11a of the die, and the protective layer 111 may be applied by: the protective layer 111 is applied on the wafer active surface before dicing the wafer into the die 11, and dicing the wafer with the protective layer 111 into the die 11 with the protective layer 111 may be: after the wafer is diced into dies 11, a protective layer 111 is applied over the dies 11.
The die 11 may include a variety of devices formed on a semiconductor substrate and electrical interconnect structures electrically connected to the respective devices. The second inner pad 110b of the die active surface 11a is connected to an electrical interconnect structure for inputting/outputting electrical signals of the respective devices. The back ground inner pad 110c is for electrical connection with the back surface 11b of the die 11. Die 11 may be a power chip. The first inner pad 110a may be located near a channel region of the power chip.
The structure and function of each die 11 may be the same or different.
The protective layer 111 is made of an insulating material, and may be at least one of an insulating resin material, silicon dioxide, and silicon nitride.
The insulating resin material, such as polyimide, epoxy, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), etc., may be laminated on the first inner pad 110a, the second inner pad 110b, and the insulating layer between the first inner pad 110a and the second inner pad 110b by a) lamination process, or b) coated on the first inner pad 110a, the second inner pad 110b, and the insulating layer between the first inner pad 110a and the second inner pad 110b, post-cured, or c) cured on the first inner pad 110a, the second inner pad 110b, and the insulating layer between the first inner pad 110a and the second inner pad 110b by an injection molding process.
When the material of the protective layer 111 is silicon dioxide or silicon nitride, the first inner pad 110a, the second inner pad 110b, and the insulating layer between the first inner pad 110a and the second inner pad 110b may be formed by a deposition process.
Referring to fig. 5, the protective layer 111 has a plurality of first openings 111a therein, a partial number of the first openings 111a exposing a partial region of the first inner pad 110a, and a partial number of the first openings 111a exposing a partial region of the second inner pad 110 b. In some embodiments, the first inner pad 110a and the second inner pad 110b on the die 11 may be embedded in the protective layer 111, and the first opening 111a is fabricated in a process of forming the wiring layer 13 (see fig. 12).
In the embodiment shown in fig. 5, a first opening 111a exposes a partial region of a first inner pad 110a (or a second inner pad 110 b). In other embodiments, one first opening 111a may also expose a partial region of two or more first inner pads 110a (or second inner pads 110 b).
The number of the die 11 may be two, three, all the die after dicing of one wafer, or even all the die after dicing of a plurality of wafers, and the present invention is not limited to the number of the die 11.
The wafer may be thinned from the back side prior to dicing to reduce the thickness of the die 11.
The carrier plate 2 is a hard plate and may include a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
An adhesive layer may be disposed between the carrier plate 2 and the die 11, so as to fix the carrier plate and the die. Specifically, an entire adhesive layer may be coated on the surface of the carrier plate 2, and the plurality of dies 11 may be placed on the adhesive layer. The adhesive layer may be made of an easily peelable material so as to peel the carrier plate 2 and the die 11 apart, for example, a thermally separable material which can be made to lose adhesiveness by heating or a UV separable material which can be made to lose adhesiveness by ultraviolet irradiation.
Next, referring to step S2 in fig. 3, and as shown in fig. 2 and fig. 6, a plurality of electrical connectors 12 are provided, the electrical connectors 12 including a first conductive portion 12a, a second conductive portion 12b, and a connection portion 12c connecting the first conductive portion 12a and the second conductive portion 12b, the second conductive portion 12b including a first sub-conductive portion 120a and a second sub-conductive portion 120b; referring to fig. 7, each electrical connector 12 is disposed on each die 11, the first conductive portion 12a is electrically connected to the back surface 11b of the die 11, and the second conductive portion 12b is disposed on the surface of the carrier 2.
The material of the electrical connector 12 may be a metal with good electrical conductivity and a certain hardness, such as copper.
Referring to fig. 2, the electrical connector 12 may include one first conductive portion 12a and four second conductive portions 12b. Of the four second conductive portions 12b, three are first sub-conductive portions 120a and one is a second sub-conductive portion 120b. The first conductive portion 12a, the connection portion 12c, and the first sub-conductive portion 120a of the electrical connector 12 are rectangular in plan view. The first conductive portion 12a, the connection portion 12c, and the second sub-conductive portion 120b of the electrical connector 12 are also rectangular in plan view. In other embodiments, the second conductive portion 12b includes at least one first sub-conductive portion 120a and one second sub-conductive portion 120b.
Referring to fig. 6, a plurality of electrical connectors 12 may be disposed on a first support plate 3. The electrical connector 12 may be convex in vertical cross-section to accommodate the die 11. The convexity can be formed by at least one of cutting, stamping, etching, embossing, and can be mass-produced in a batch to reduce cost.
In the embodiment shown in fig. 6, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are right angles. In some embodiments, the angles between the first conductive portion 12a and the second conductive portion 12b and the connection portion 12c are obtuse angles.
The first support plate 3 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
An adhesive layer may be provided between the first conductive portion 12a of the electrical connector 12 and the first support plate 3, so as to achieve fixation therebetween. Specifically, an entire adhesive layer may be coated on the surface of the first support plate 3, and the first conductive portions 12a of the plurality of electrical connectors 12 may be disposed on the adhesive layer. The adhesive layer may be made of an easily peelable material for peeling the electrical connection member 12 from the first support plate 3, for example, a heat-peelable material which can be made to lose its tackiness by heating or a UV-peelable material which can be made to lose its tackiness by ultraviolet irradiation.
Referring to fig. 7, the first support plate 3 and the carrier plate 2 are aligned, each electrical connector 12 is disposed on each die 11, the first conductive portion 12a is located on the back surface 11b of the die 11, and the second conductive portion 12b is located on the surface of the carrier plate 2.
In some embodiments, a conductive paste may be disposed between the first conductive portion 12a and the back surface 11b of the die 11 to electrically connect the two. The conductive paste may include a nano copper/conductive polymer composite. The nano copper/conductive polymer composite material is a composite material formed by adding nano copper particles into a conductive polymer and uniformly dispersing nano copper in the conductive polymer. The composite material is a solid, flat sheet-like structure, preferably the same shape and size as the surface of the die backside 11 b.
Specifically, the nano copper/conductive polymer composite material is first placed on the back surface 11b of the die, and then the electrical connection pieces 12 arranged on the first support plate 3 are transferred to predetermined positions on the carrier plate 2, and the first conductive portions 12a of the electrical connection pieces 12 cover the composite material on the back surface 11b of the die. Heating the bare chip 11, the nano copper/conductive polymer composite material and the electric connector 12 on the carrier plate 2 to a temperature above the glass transition temperature of the conductive polymer material; at this time, the conductive polymer material is changed from a solid to a semi-liquid having a certain viscosity, bonding the die backside 11b with the first conductive portion 12 a.
In the nano-copper/conductive polymer composite, the conductive polymer may be: at least one of polypyrrole, polythiophene, polyaniline and polyphenylene sulfide. The conductive polymer is formed by changing an insulator into a conductor through chemical or electrochemical doping by a macromolecule with conjugated pi-bond, has good conductive property, and the conductivity is further enhanced after nano copper is added.
Copper is one of the most excellent metal materials, and when the copper scale is reduced to the nanometer level, the copper material has high specific surface area, high surface activity and more excellent electric and heat conduction characteristics. Preferably, the nano copper is spherical, and the particle size is less than 800nm; further preferably, the particle diameter of the nano copper is in the range of 200nm to 500nm. This is because: the specific surface area of the nano copper material is increased along with the reduction of the particle size of the material, and the electric conduction and heat conduction properties of the material are enhanced; when the particle size is reduced to below 800nm, the material has excellent electric and heat conduction characteristics; however, when the particle size is reduced to below 200nm, the manufacturing cost of the nano material is increased remarkably, the packaging economic benefit is affected, and when the particle size of the nano copper is reduced to below 200nm, the surface energy of the nano copper particles is increased, larger particles are easily formed by agglomeration among the particles, and the electric conductivity and the heat conductivity of the composite material are damaged.
Preferably, the nano-copper is added in an amount of more than 5wt% in the nano-copper/conductive polymer composite.
In some embodiments, the first conductive portion 12a may be in direct contact with the back surface 11b of the die 11 to make electrical connection therebetween.
In some embodiments, the backside 11b of the die 11 may also be provided with a conductive layer. The conductive layer may be formed before dicing the die 11.
In the embodiment shown in fig. 7, there is no gap between the connection portion 12c of the electrical connector 12 and the die 11, and in other embodiments, there may be a gap between the two to allow molding compound to enter.
After that, the first support plate 3 is removed. The first support plate 3 may be removed by a conventional removal method such as laser lift-off and UV irradiation.
Then, referring to step S3 in fig. 3, fig. 8 and fig. 9, a first molding layer 10 is formed on the surface of the carrier 2 to embed each die 11 and each electrical connector 12; referring to fig. 10, the first molding layer 10 is thinned until the first conductive portions 12a of the respective electrical connectors 12 are exposed; referring to fig. 11, the carrier plate 2 is removed. Wherein, fig. 8 is a top view of the first plastic sealing layer, and the first plastic sealing layer shows perspective effect; fig. 9 is a cross-sectional view taken along the line BB in fig. 8.
The material of the first plastic layer 10 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. Correspondingly, the packaging can be performed by filling liquid plastic packaging material between each bare chip 11 and each electric connector 12 and then curing the liquid plastic packaging material at high temperature through a plastic packaging mold.
The first plastic layer 10 may be thinned by mechanical grinding, such as grinding with a grinding wheel.
The protective layer 111 may prevent the first and second inner pads 110a and 110b and the electrical interconnection structure within the die 11 from being damaged during the formation of the first molding layer 10 and the grinding of the first molding layer 10.
Referring to fig. 11, after removing the carrier 2, the second conductive portion 12b of the electrical connector 12 is substantially in the same plane as the active surface 11a of the die 11. In addition, a second support plate 4 may be disposed on the first molding layer 10 and the first conductive portion 12a of each electrical connector 12. The second support plate 4 may support the die 11 embedded in the first plastic layer 10 in a subsequent process.
The second support plate 4 is a hard plate and may include a glass plate, a ceramic plate, a metal plate, etc.
Next, referring to step S4 in fig. 3 and fig. 12, a circuit layer 13 is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10 to form the package intermediate structure 1 including a plurality of dies 11, the circuit layer 13 includes a rewiring layer 131, a portion of the rewiring layer 131 electrically connects the first sub-conductive portion 120a and the first inner pad 110a, and a portion of the rewiring layer 131 electrically connects the second sub-conductive portion 120b and the back ground inner pad 110c.
In the present embodiment, forming the wiring layer 13 includes the following steps S41 to S42.
Step S41: a rewiring layer 131 is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10, and a portion of the rewiring layer 131 electrically connects the first sub-conductive portion 120a and the first inner pad 110a, and a portion of the rewiring layer 131 electrically connects the second sub-conductive portion 120b and the back-grounded inner pad 110c.
The rewiring layer 131 is a fan-out line (fan-out).
Step S42: conductive studs 132 are formed on the rewiring layer 131. The conductive stud 132 is the outer lead 13a.
In one alternative, step S41 of forming the rewiring layer 131 includes steps S410 to S413.
Step S410: a photoresist layer is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In this step S410, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the adhesive tape and applied to the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first plastic sealing layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S411: the photoresist layer is exposed and developed, and the photoresist layer is maintained in a first predetermined region, which is complementary to the region where the metal block 131a of the re-wiring layer 131 to be formed is located.
Of the plurality of metal blocks 131a, a part of the number of metal blocks 131a is located so as to electrically connect the first sub-conductive part 120a with the first inner pad 110a, and a part of the number of metal blocks 131a is located so as to electrically connect the second sub-conductive part 120b with the back ground inner pad 110c. In addition, there are also a partial number of metal blocks 131a positioned so as to electrically connect one or more second inner pads 110b for implementing other functions.
This step S411 patterns the photoresist layer. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S412: the metal layer is filled in a complementary region of the first predetermined region to form a metal block 131a of the rewiring layer 131.
This step S412 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature.
Specifically, before forming the photoresist Layer in step S410, a Seed Layer (Seed Layer) may be formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding Layer 10 by physical vapor deposition or chemical vapor deposition. The seed layer may serve as a power supply layer for electroplating copper or aluminum.
Step S413: ashing removes the photoresist layer remaining in the first predetermined area.
And after ashing, removing the seed crystal layer in the first preset area through dry etching or wet etching.
The metal block 131a of the re-wiring layer 131 may be planarized on the upper surface by a polishing process, for example, a chemical mechanical polishing method.
The metal blocks 131a of the rewiring layer 131 in this step S41 are arranged according to design requirements, and the distribution of the rewiring layers 131 on the respective dies 11 may be the same or different.
This step S42 may include steps S420-S425.
Step S420: a photoresist layer is formed on the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In this step S420, in an alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film may be peeled off from the adhesive tape and applied to the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first plastic sealing layer 10. Alternatively, the photoresist layer may be formed by coating a liquid photoresist and then curing by heating.
Step S421: the photoresist layer is exposed and developed, and the photoresist in the second preset area is reserved. The second predetermined region is complementary to a region where the conductive stud 132 is to be formed.
In this embodiment, the second predetermined area is located such that at least one conductive stud 132 can lead out the metal block 131a electrically connecting the second sub-conductive portion 120b and the back ground inner pad 110 c. In some embodiments, the metal block 131a electrically connecting the second sub-conductive portion 120b and the back-grounded inner pad 110c may not be led out through the conductive bump 132.
The photoresist layer is patterned in this step S421. In other alternatives, other easily removable sacrificial materials may be used in place of the photoresist layer.
Step S422: and filling the complementary region of the second predetermined region with a metal layer to form the conductive stud 132.
This step S422 may be accomplished using an electroplating process. The copper or aluminum electroplating process is mature. A Seed Layer (Seed Layer) may also be deposited as a power Layer prior to electroplating copper or aluminum.
Step S423: ashing removes the photoresist layer remaining in the second predetermined area.
The conductive posts 132 may be planarized by a polishing process, such as chemical mechanical polishing.
Step S424: referring to fig. 12, a second molding layer 133 embedding the conductive stud 132 is formed on the conductive stud 132, the metal block 131a, the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10.
In one alternative, the step S424 includes: firstly, attaching a semi-solid plastic packaging film on the conductive convex column 132, the metal block 131a, the protective layer 111, the second conductive part 12b of each electric connector 12 and the first plastic packaging layer 10; then, placing the structure to be molded, which is stuck with the semi-solid plastic packaging film, on a lower die body, and closing the high-temperature upper die body; when the upper die body is used for hot-pressing the plastic packaging film, the semi-solid plastic packaging film is changed into a liquid plastic packaging material, and after flowing, the plastic packaging material is continuously heated to change from a liquid state into a solid state to form a second plastic packaging layer 133; the mold is removed.
In another alternative, the second plastic layer 133 formed in the step S424 is formed by an injection molding process. Specifically, firstly, placing a structure to be molded on a lower die body, and closing a high-temperature upper die body; injecting normal-temperature liquid plastic package material into the high-temperature mold cavity; the normal temperature liquid molding compound flows while changing from liquid to solid second molding layer 133 due to heat.
The second molding layer 133 can improve electrical insulation properties between adjacent conductive studs 132 and metal blocks 131 a.
Step S425: still referring to fig. 12, the second molding layer 133 is thinned until the conductive posts 132 are exposed.
The second plastic layer 133 may be thinned by mechanical grinding, such as grinding with a grinding wheel.
In some embodiments, step S41 may include S410'-S413'.
Step S410': referring to fig. 13, a first dielectric layer 131b is formed on the active surface 11a of each die 11, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10. The material of the first dielectric layer 131b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition.
In step S411', a plurality of second openings are formed in the first dielectric layer 131b, a portion of the plurality of second openings exposes the first inner pad 110a, and a portion of the plurality of second openings exposes the second inner pad 110b. The second opening is a region where the metal block 131a is to be formed. The second opening may be formed by dry etching using the patterned photoresist as a mask.
In step S412', a conductive material layer is formed on the first dielectric layer 131b and in the second opening. The conductive material layer can be made of copper or aluminum, and is formed by physical vapor deposition or chemical vapor deposition.
In step S413', the conductive material layer is polished until the first dielectric layer 131b is exposed, and the conductive material layer in the second opening forms the metal block 131a.
In still other embodiments, two or more rewiring layers 131 may be formed.
In some embodiments, step S42 may include S420'-S422'.
Step S420': referring to fig. 13, conductive studs 132 are formed on the metal block 131a and the first dielectric layer 131b (or the protective layer 111, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10).
Step S421': a second dielectric layer 132b is formed on the conductive studs 132 and between adjacent conductive studs 132. The second dielectric layer 132b may be silicon dioxide or silicon nitride, and is formed by physical vapor deposition or chemical vapor deposition.
In step S422', the second dielectric layer 132b is polished until the conductive bump 132 is exposed.
In other embodiments, a second dielectric layer 132b is formed between adjacent conductive pillars 132, and an upper surface of the second dielectric layer 132b is flush with an upper surface of the conductive pillar 132, and the second dielectric layer 132b is made of an organic material. The organic material may be polyimide with good fluidity, and is cured after heating.
In still other embodiments, a second molding layer 133 is formed over the conductive studs 132 and between adjacent conductive studs 132, and the second molding layer 133 is thinned until the conductive studs 132 are exposed.
In still other embodiments, a second dielectric layer 132b is formed on the metal block 131a, the second conductive portion 12b of each electrical connector 12, and the first molding layer 10, a third opening exposing the metal block 131a is formed in the second dielectric layer 132b, a conductive material is filled in the third opening, and the conductive material is polished until the second dielectric layer 132b is exposed. The conductive material filled in the third opening forms a conductive stud 132.
a) In the alternative, referring to fig. 12 and 13, the conductive stud 132 is the outer lead 13a.
b) Alternatively, referring to fig. 14, after the conductive stud 132 is exposed, a second oxidation preventing layer 134 is further formed on the conductive stud 132.
The second oxidation resistant layer 134 may include: b1 Tin layer, or b 2) nickel layer and gold layer stacked from bottom to top, or b 3) nickel layer, palladium layer and gold layer stacked from bottom to top. The second oxidation resistant layer 134 may be formed using an electroplating process. The conductive bump 132 may be made of copper, and the second oxidation resistant layer 134 may prevent copper oxidation, thereby preventing deterioration of electrical connection performance caused by copper oxidation.
c) Optionally, after exposing the conductive bump 132, a solder ball is further formed on the conductive bump 132 for flip-chip mounting the chip package structure 1a (see fig. 1).
After the outer leads are formed, the second support plate 4 is removed as shown with reference to fig. 15.
The second support plate 4 may be removed by conventional removal methods such as laser lift-off and UV irradiation.
After removing the second support plate 4, a first oxidation preventing layer 121 may be further formed on the exposed first conductive portion 12 a. The material and the forming method of the first oxidation preventing layer 121 refer to the material and the forming method of the second oxidation preventing layer 134.
Thereafter, referring to step S5 in fig. 3, fig. 15 and fig. 1, the package intermediate structure 1 is cut to form a plurality of chip package structures 1a, and each chip package structure 1a includes one die 11.
Fig. 16 is a top view of an electrical connector in a method for manufacturing a chip package structure according to a second embodiment of the present invention. Referring to fig. 16, the chip package structure in this embodiment is substantially the same as the chip package structure 1a in fig. 1, except that: the connection portion 12c of the electrical connector 12 is partially removed, and the first conductive portion 12a, the connection portion 12c, and the first sub-conductive portion 120a of the electrical connector 12 are H-shaped in plan view, and the first conductive portion 12a, the connection portion 12c, and the second sub-conductive portion 120b of the electrical connector 12 are also H-shaped in plan view.
In the thermal expansion and contraction process of the electrical connector 12 and the first plastic sealing layer 10, the removed area of the connecting portion 12c can provide a deformation accommodating space. Preferably, the first conductive portion 12a has a size larger than that of the second conductive portion 12 b.
Accordingly, the method for manufacturing the chip package structure in this embodiment is substantially the same as that of fig. 1 to 15, and the only difference is that: in step S2, a part of the material is removed from the connection portion 12c of the electrical connector 12, and the first conductive portion 12a, the connection portion 12c, and the first sub-conductive portion 120a of the electrical connector 12 are H-shaped in plan view, and the first conductive portion 12a, the connection portion 12c, and the second sub-conductive portion 120b of the electrical connector 12 are also H-shaped in plan view. The removal of portions of material may be formed by at least one of cutting, stamping, etching, embossing.
In some embodiments, in the electrical connector 12, a part of the first conductive portions 12a, the connection portions 12c and the first sub-conductive portions 120a may have an H shape in a plan view, a part of the first conductive portions 12a, the connection portions 12c and the first sub-conductive portions 120a may have a rectangular shape in a plan view, a part of the first conductive portions 12a, the connection portions 12c and the second sub-conductive portions 120b may have an H shape in a plan view, and a part of the first conductive portions 12a, the connection portions 12c and the second sub-conductive portions 120b may have a rectangular shape in a plan view.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (12)
1. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
providing a carrier plate and a plurality of bare chips, wherein each bare chip comprises an active surface and a back surface which are opposite, and the active surface is provided with a first inner bonding pad, a second inner bonding pad and a protective layer which covers the first inner bonding pad and the second inner bonding pad; the first inner bonding pad is positioned in a heating area of the bare chip, and the second inner bonding pad at least comprises one back grounding inner bonding pad; fixing the active surface of each bare chip on the carrier plate;
providing a plurality of electric connectors, wherein the electric connectors comprise a first conductive part, a second conductive part and a connecting part for connecting the first conductive part and the second conductive part, and the second conductive part comprises a first sub-conductive part and a second sub-conductive part; each electric connector is arranged on each bare chip, the first conductive part is electrically connected to the back surface of each bare chip, and the second conductive part is arranged on the surface of the carrier plate; the first conductive part, the connecting part and the first sub-conductive part of the electric connector are H-shaped, and the size of the connecting part is respectively smaller than the size of the first conductive part connected with the first sub-conductive part and the size of the first sub-conductive part in the direction perpendicular to the direction that the edge of the connecting part connected with the first sub-conductive part is far away from the edge of the first conductive part and far away from the same connecting part and perpendicular to the direction that the active surface is directed towards the back surface; and/or the first conductive part, the connecting part and the second sub-conductive part of the electric connector are H-shaped, and the size of the connecting part is respectively smaller than the size of the first conductive part and the size of the second sub-conductive part connected with the first conductive part and the second conductive part in the direction perpendicular to the direction that the edge of the connecting part connected with the second sub-conductive part is far away from the edge of the first conductive part and far away from the same connecting part and perpendicular to the direction that the active surface is directed towards the back surface;
Forming a first plastic sealing layer which is used for embedding each bare chip and each electric connecting piece on the surface of the carrier plate; thinning the first plastic sealing layer until the first conductive parts of the electric connecting pieces are exposed; removing the carrier plate;
forming a circuit layer on the active surface of each bare chip, the second conductive part of each electric connector and the first plastic sealing layer to form a packaging intermediate structure containing a plurality of bare chips, wherein the circuit layer comprises a rewiring layer, a part of the rewiring layer is electrically connected with the first sub-conductive part and the first inner bonding pad, and a part of the rewiring layer is electrically connected with the second sub-conductive part and the back grounding inner bonding pad;
and cutting the packaging intermediate structure to form a plurality of chip packaging structures, wherein each chip packaging structure comprises a bare chip.
2. The method of claim 1, wherein the plurality of electrical connectors are disposed on a first support plate.
3. The method of manufacturing a chip package according to claim 1, wherein the electrical connection is formed by at least one of cutting, stamping, etching, embossing; and/or the first sub-conductive part comprises two or more.
4. The method of manufacturing a chip package structure according to claim 1, further comprising: and forming a first oxidation resistant layer on the first conductive part of each electric connecting piece exposing the first plastic sealing layer.
5. The method of manufacturing a chip package according to claim 1, wherein forming a circuit layer on the active surface of each die, the second conductive portion of each electrical connector, and the first molding layer comprises:
forming the rewiring layer on the first inner bonding pad, the second inner bonding pad, the protective layer, the first plastic sealing layer between the bare chips and the second conductive part of the electric connector;
and forming a conductive stud on the rewiring layer.
6. The method of claim 5, wherein the rewiring layer comprises two or more layers.
7. The method of manufacturing a chip package structure according to claim 5, further comprising: and forming a solder ball on the conductive convex column, wherein the solder ball is an outer pin.
8. The method of manufacturing a chip package structure according to claim 5, further comprising: and forming a second oxidation resistance layer on the conductive convex column.
9. The method of manufacturing a chip package structure according to claim 5, wherein forming conductive studs on the rewiring layer comprises:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer on the conductive convex columns and between the adjacent conductive convex columns, wherein the second dielectric layer is made of inorganic materials;
polishing the second dielectric layer until the conductive posts are exposed;
or comprises:
forming a conductive stud on the metal block of the rewiring layer;
forming a second dielectric layer between adjacent conductive convex columns, wherein the upper surface of the second dielectric layer is flush with the upper surface of the conductive convex column, and the second dielectric layer is made of an organic material;
or comprises:
forming a second dielectric layer on the rewiring layer;
forming a plurality of third openings in the second dielectric layer, the third openings exposing the metal blocks of the rewiring layer;
forming a conductive material layer on the second dielectric layer and in the third opening;
polishing the conductive material layer until the second dielectric layer is exposed, wherein the conductive material layer in the third opening forms a conductive convex column;
or comprises:
forming a conductive convex column on the metal block of the rewiring layer, and forming a second plastic sealing layer embedding the conductive convex column on the rewiring layer;
And thinning the second plastic sealing layer until the conductive convex columns are exposed.
10. The method according to claim 1, wherein a conductive layer is disposed on a back surface of the die, and/or a conductive paste is disposed between the first conductive portion and the back surface of the die.
11. The method of claim 10, wherein the conductive paste comprises a nano-copper/conductive polymer composite.
12. The method of manufacturing a chip package according to claim 1, wherein in the step of fixing the active surface of each die to the carrier, the protective layer has a plurality of first openings therein, a part of the first openings expose a partial area of the first inner pads, and a part of the first openings expose a partial area of the second inner pads; or forming a first opening in the protective layer in the step of forming the circuit layer, wherein part of the first openings expose part of areas of the first inner bonding pads, and part of the first openings expose part of areas of the second inner bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010230888.3A CN113725088B (en) | 2020-03-27 | 2020-03-27 | Manufacturing method of chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010230888.3A CN113725088B (en) | 2020-03-27 | 2020-03-27 | Manufacturing method of chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113725088A CN113725088A (en) | 2021-11-30 |
| CN113725088B true CN113725088B (en) | 2024-02-27 |
Family
ID=78671085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010230888.3A Active CN113725088B (en) | 2020-03-27 | 2020-03-27 | Manufacturing method of chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113725088B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116387169B (en) * | 2023-06-05 | 2023-09-05 | 甬矽半导体(宁波)有限公司 | Packaging method and packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020055687A (en) * | 2000-12-29 | 2002-07-10 | 마이클 디. 오브라이언 | Semiconductor package |
| US9768133B1 (en) * | 2016-09-22 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
| CN206931590U (en) * | 2017-06-21 | 2018-01-26 | 中芯长电半导体（江阴）有限公司 | Fan-out-type wafer level packaging structure |
| CN206931562U (en) * | 2017-06-21 | 2018-01-26 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure |
| CN110729258A (en) * | 2019-03-11 | 2020-01-24 | Pep创新私人有限公司 | Chip packaging method and chip structure |
-
2020
- 2020-03-27 CN CN202010230888.3A patent/CN113725088B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020055687A (en) * | 2000-12-29 | 2002-07-10 | 마이클 디. 오브라이언 | Semiconductor package |
| US9768133B1 (en) * | 2016-09-22 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method of forming the same |
| CN206931590U (en) * | 2017-06-21 | 2018-01-26 | 中芯长电半导体（江阴）有限公司 | Fan-out-type wafer level packaging structure |
| CN206931562U (en) * | 2017-06-21 | 2018-01-26 | 中芯长电半导体（江阴）有限公司 | Fan-out-type list die package structure |
| CN110729258A (en) * | 2019-03-11 | 2020-01-24 | Pep创新私人有限公司 | Chip packaging method and chip structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113725088A (en) | 2021-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107887346B (en) | Integrated fan-out package | |
| CN210006732U (en) | Chip packaging structure | |
| US10276545B1 (en) | Semiconductor package and manufacturing method thereof | |
| CN111883521B (en) | Multi-chip 3D packaging structure and manufacturing method thereof | |
| CN112151466B (en) | Chip packaging structure and manufacturing method thereof | |
| CN104051334A (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| CN112349608A (en) | Manufacturing method of chip packaging structure | |
| CN113725088B (en) | Manufacturing method of chip packaging structure | |
| CN113871307A (en) | IPM packaging structure and manufacturing method thereof | |
| CN113725181B (en) | Chip packaging structure | |
| CN113725180B (en) | Chip packaging structure and manufacturing method thereof | |
| CN113611692B (en) | MCM packaging structure and manufacturing method thereof | |
| CN113725089B (en) | Manufacturing method of chip packaging structure | |
| CN113725182B (en) | Chip packaging structure | |
| CN113725183B (en) | Chip packaging structure and manufacturing method thereof | |
| CN215299231U (en) | Chip packaging structure | |
| CN210182380U (en) | Semiconductor packaging structure | |
| US20220399207A1 (en) | Semiconductor encapsulation method and semiconductor encapsulation structure | |
| CN113611615A (en) | Manufacturing method of chip packaging structure | |
| CN209929301U (en) | Semiconductor packaging structure | |
| CN114446918A (en) | MCM encapsulation structure and manufacturing method thereof | |
| CN112349601A (en) | Manufacturing method of chip packaging structure | |
| CN112133695B (en) | System-in-package structure and manufacturing method thereof | |
| CN113571435B (en) | Method for forming chip packaging structure | |
| CN112582282B (en) | Semiconductor packaging method and semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |