CN116387169B

CN116387169B - Packaging method and packaging structure

Info

Publication number: CN116387169B
Application number: CN202310652509.3A
Authority: CN
Inventors: 何正鸿
Original assignee: Yongsi Semiconductor Ningbo Co ltd
Current assignee: Yongsi Semiconductor Ningbo Co ltd
Priority date: 2023-06-05
Filing date: 2023-06-05
Publication date: 2023-09-05
Anticipated expiration: 2043-06-05
Also published as: CN116387169A

Abstract

The disclosure provides a packaging method and a packaging structure, and relates to the technical field of semiconductor packaging. The packaging method comprises the steps of providing a first heat dissipation structure; mounting a first chip; the first heat dissipation structure is arranged on the periphery of the first chip in a surrounding mode; coating the first chip to form a protective body; wherein the first bonding pad exposes the protective body; forming a first conductive post in the protective body; wherein the first conductive column penetrates through the protective body; a dielectric layer and a wiring layer are arranged on one side of the first chip far away from the first bonding pad; the wiring layer is electrically connected with the first conductive column, and the dielectric layer wraps the wiring layer; forming a metal layer on the dielectric layer, wherein the metal layer is electrically connected with the wiring layer; a second chip and/or a third chip are/is attached to one side of the first chip, which is provided with the first bonding pad; the second chip is electrically connected with the first chip and the first conductive column respectively, and/or the third chip is electrically connected with the first chip and the first conductive column respectively. The method is beneficial to improving the integration level of the packaging structure and improving the heat dissipation performance.

Description

Packaging method and packaging structure

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging method and a packaging structure.

Background

In the existing packaging structure, a new design mode of a chiplet technology is adopted, a plurality of chiplets with different functions are required to be packaged together, and the layering phenomenon is easily generated between a wiring layer and a dielectric layer due to the fact that the thermal expansion coefficients, young modulus and the like of various materials in the packaging structure are inconsistent. In order to solve this problem, a sand blast roughening treatment is usually performed on the wiring layer or the pad, but when the roughness of the wiring layer becomes coarse, the precision in patterning the pattern is lowered, and if the shape precision of the wiring pattern in the signal transmission path is lowered, an unstable phenomenon of the signal transmission characteristics is caused, and the signal transmission loss increases. In addition, in the package structure, the higher the integration level of the chip is, the more difficult the heat dissipation is.

The existing 2.5D packaging technology is to package chips onto a silicon interposer as a multi-chip packaging scheme, and needs to perform a silicon perforation and wiring process, and the process steps are complicated.

Disclosure of Invention

The invention aims at providing a packaging method and a packaging structure, which are capable of improving bonding force and improving heat dissipation performance of the packaging structure, wherein the delamination phenomenon in the packaging structure is relieved.

Embodiments of the invention may be implemented as follows:

in a first aspect, the present invention provides a packaging method, including:

s1: providing a first heat dissipation structure;

s2: mounting a first chip; the first heat dissipation structure is arranged on the periphery of the first chip in a surrounding mode; a first bonding pad is arranged on one side of the first chip;

s3: coating the first chip to form a protective body; wherein the first bonding pad exposes the protective body;

s4: forming a first conductive post within the protective body; wherein the first conductive post penetrates through the protective body;

s5: a dielectric layer and a wiring layer are arranged on one side, far away from the first bonding pad, of the first chip; the wiring layer is electrically connected with the first conductive column, and the dielectric layer wraps the wiring layer; the first heat dissipation structure is connected with the dielectric layer;

s6: forming a metal layer on the dielectric layer, wherein the metal layer is electrically connected with the wiring layer;

s7: a second chip and/or a third chip are/is attached to one side, provided with the first bonding pad, of the first chip; wherein the second chip is electrically connected with the first chip and the first conductive column respectively, and/or the third chip is electrically connected with the first chip and the first conductive column respectively;

S8: and plastic packaging the second chip and/or the third chip to form a first packaging body.

In an alternative embodiment, step S1 includes:

providing a first carrier, and attaching the first heat dissipation structure on the first carrier;

the step S2 comprises the following steps: attaching the first chip to the first carrier or attaching the first chip to the first heat dissipation structure;

step S4, removing the first carrier;

before step S5, a second carrier is attached to a side of the first heat dissipation structure, which is close to the first chip.

In an alternative embodiment, the first heat dissipation structure comprises a bottom wall and a side wall protruding from the bottom wall, and the bottom wall and the side wall enclose a heat dissipation groove; the step S2 comprises the following steps:

and attaching the first chip to the bottom wall.

In an alternative embodiment, the first heat dissipation structure further includes a support block, where the support block is disposed on a side of the bottom wall away from the side wall; the step S5 comprises the following steps:

a dielectric layer and a wiring layer are arranged on one side of the bottom wall, provided with the supporting block; wherein, the supporting block is buried in the medium layer.

In an alternative embodiment, the dielectric layers include a first dielectric layer, a second dielectric layer, and a third dielectric layer, and the wiring layers include a first wiring layer and a second wiring layer; the step S5 comprises the following steps:

S51: a first dielectric layer is arranged on one side of the bottom wall far away from the first chip;

s52: covering a photomask plate on the first dielectric layer to form a patterned opening, and forming a first wiring layer in the patterned opening; wherein, the photomask plate is placed on the supporting block;

s53: a second dielectric layer is arranged on the first wiring layer;

s54: covering a photomask plate on the second dielectric layer to form a patterned opening, and forming a second wiring layer in the patterned opening; wherein, the photomask plate is placed on the supporting block; the second wiring layer is electrically connected with the first wiring layer;

s55: a third dielectric layer is arranged on the second wiring layer; forming a groove in the third dielectric layer, and forming a metal layer in the groove; the metal layer and the second wiring layer are electrically connected.

In an alternative embodiment, in step S55, the metal layer and the support block are electrically connected.

In an alternative embodiment, the support block is grounded; the method further comprises the steps of:

s9: and an electromagnetic shielding layer is arranged on the first packaging body, and the electromagnetic shielding layer is electrically connected with the side wall.

In an alternative embodiment, step S4 includes:

a first groove is formed in the protective body, a through hole is formed in the bottom of the first groove, and the through hole penetrates through the protective body and the bottom wall;

A first conductive post is formed within the via.

In an alternative embodiment, in step S3:

adopting plastic packaging material to plastic package the first chip to form a protective body;

or the mounting plate forms a protective body; wherein, the panel is equipped with logical groove to make first chip is located in the logical inslot.

In an alternative embodiment, the method further comprises:

grinding to remove the bottom wall and the supporting block after the step S4;

in step S5, the wiring layer is electrically connected with the side wall;

in step S7, an end of the sidewall away from the wiring layer is ground, so that the end of the sidewall away from the wiring layer is flush with the first pad; and attaching the second chip or the third chip on the side wall.

In an alternative embodiment, connecting ribs are arranged between the first heat dissipation structures.

In an alternative embodiment, the method further comprises:

s10: a first substrate and a second heat dissipation structure attached to the first substrate are arranged on one side, far away from the first packaging body, of the metal layer; wherein, the fourth chip and the fifth chip are mounted in the second heat dissipation structure; the fourth chip and the fifth chip are respectively and electrically connected with the metal layer;

forming a second conductive post; one end of the second conductive post is electrically connected with the first substrate, and the other end of the second conductive post is electrically connected with the metal layer.

In an alternative embodiment, the first substrate is made using steps S5 and S6.

In an alternative embodiment, the method further comprises:

forming a first insulating layer on the outer sides of the second chip and the third chip;

forming a first shielding layer on the outer side of the first insulating layer, wherein the first shielding layer is electrically connected with the side wall of the first heat dissipation structure;

forming a second insulating layer outside the first shielding layer;

and forming a second shielding layer on the outer side of the second insulating layer, wherein the second shielding layer is electrically connected with the side wall of the second heat dissipation structure.

In an alternative embodiment, the method further comprises:

a second packaging body is arranged, and the first heat dissipation structure, the fourth chip and the fifth chip are packaged in a plastic mode by the second packaging body;

and a third shielding layer is arranged on the outer side of the second packaging body, and the third shielding layer is electrically connected with the side wall of the second heat dissipation structure.

In an alternative embodiment, the method further comprises:

providing a second substrate; wherein the second substrate is provided with a containing groove;

mounting the semi-finished products obtained in the steps S1 to S7 in the accommodating groove; wherein the metal layer is electrically connected with the second substrate;

attaching a first device to a second substrate; and/or attaching a second device on the second substrate and the protective body of the semi-finished product, wherein one end of the second device is connected to the second substrate, and the other end of the second device is electrically connected with the first conductive post of the semi-finished product.

In a second aspect, the present invention provides a packaging structure, which is manufactured by the packaging method according to any one of the foregoing embodiments.

In an alternative embodiment, the method comprises:

a substrate;

a first chip; the first chip is connected to the substrate;

the first heat dissipation structure comprises a side wall, the side wall is connected with the substrate, and the side wall is arranged on the periphery of the first chip in a surrounding mode;

a protective body; the protection body is connected with the substrate, the protection body is provided with a through groove, and the first chip is positioned in the through groove;

the second chip is attached to one side, away from the substrate, of the first chip; the second chip is electrically connected with the substrate and the first chip respectively.

In an alternative embodiment, the semiconductor device further comprises a first conductive post penetrating through the protective body, wherein one end of the first conductive post is electrically connected with the second chip, and the other end of the first conductive post is electrically connected with the substrate.

In an alternative embodiment, the semiconductor package further comprises a rewiring layer, wherein the rewiring layer is arranged on one side of the first conductive post, which is far away from the substrate, and is electrically connected with the first conductive post; the first chip and the second chip are respectively connected with the rewiring layer.

In an alternative embodiment, one end of the side wall is connected to or penetrates the substrate, and the other end is flush with or higher than the side of the first chip away from the substrate.

The first heat dissipation structure further comprises a heat dissipation block, and the heat dissipation block is arranged on the periphery of the first chip in a surrounding mode; the side wall is arranged on a layer of the heat dissipation block far away from the first chip; one end of the heat dissipation block is connected with or penetrates through the substrate, and the other end of the heat dissipation block is flush with or higher than one side, away from the substrate, of the first chip.

In an alternative embodiment, the side walls and the heat sink are different in height; and/or the plurality of heat sinks may be different in height.

In an alternative embodiment, the first heat dissipating structure further includes a bottom wall, the bottom wall and the side wall are connected, and the bottom wall and the side wall form a heat dissipating groove; the bottom wall is connected with the substrate, and the first chip is arranged on the bottom wall; the first conductive post penetrates through the protective body and the bottom wall.

In an alternative embodiment, the first heat dissipation structure further includes a support block, where the support block is disposed on a side of the bottom wall away from the side wall; the support blocks are embedded in or penetrate through the substrate.

In an alternative embodiment, the support block is connected to a ground line of the substrate; the first heat dissipation structure is made of metal;

the packaging structure further comprises a shielding layer and a first packaging body, wherein the first packaging body covers the second chip and the first heat dissipation structure, and the shielding layer is arranged on one side, far away from the substrate, of the first packaging body; the shielding layer is electrically connected with the side wall.

In an alternative embodiment, the heat dissipation device further comprises a first substrate and a second heat dissipation structure arranged on the first substrate;

the second heat dissipation structure comprises a heat dissipation groove surrounded by a bottom wall and a side wall; a fourth chip is arranged in the heat dissipation groove; the substrate is arranged on one side of the fourth chip far away from the first substrate; the fourth chip is electrically connected with the substrate; the base is electrically connected to the first substrate.

In an alternative embodiment, a second conductive post is also included; one end of the second conductive column is connected with the base, and the other end of the second conductive column is connected with the first substrate.

In an alternative embodiment, a first insulating layer is provided on the outer side of the second chip; a first shielding layer is arranged on the outer side of the first insulating layer, and the first shielding layer is electrically connected with the side wall of the first heat dissipation structure;

The outside of first shielding layer is equipped with the second insulating layer, the outside of second insulating layer is equipped with the second shielding layer, the second shielding layer with the lateral wall electricity of second heat radiation structure is connected.

In an alternative embodiment, the package further comprises a second package body, wherein the second package body encapsulates the first heat dissipation structure and the fourth chip;

In an alternative embodiment, the semiconductor package further comprises a second substrate, wherein the second substrate is provided with a containing groove;

the substrate is arranged in the accommodating groove; wherein the base is electrically connected with the second substrate;

the first device is attached to the second substrate; and/or attaching a second device to the second substrate and the protective body, wherein one end of the second device is connected to the second substrate, and the other end of the second device is electrically connected to the first conductive post on the protective body.

The beneficial effects of the embodiment of the invention include, for example:

according to the packaging method and the packaging structure provided by the embodiment of the invention, the heat dissipation structure is attached to the substrate, so that the heat dissipation performance of the structure can be improved. Meanwhile, the heat dissipation structure is connected with the dielectric layer, so that the bonding force between layers in the structure is improved, and the layering phenomenon of the structure is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic illustration of a first process of a packaging method according to an embodiment of the present invention;

FIG. 2 is an enlarged schematic view of a portion of FIG. 1 at A;

FIG. 3 is a second schematic process diagram of the packaging method according to the embodiment of the invention;

FIG. 4 is a third process diagram of a packaging method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a fourth process of the packaging method according to the embodiment of the present invention;

fig. 6 is a schematic structural diagram of a first heat dissipation structure according to an embodiment of the present invention;

fig. 7 is a schematic view of a package structure manufactured by a packaging method according to a second embodiment of the present invention;

fig. 8 is a schematic diagram of a first package structure according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a second package structure according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a second embodiment of a second process of the package structure according to the present invention;

fig. 11 is a schematic diagram of a third package structure according to an embodiment of the present invention;

fig. 12 is a schematic view of a fourth package structure according to an embodiment of the present invention;

fig. 13 is a schematic view of a fifth package structure according to an embodiment of the present invention;

fig. 14 is a schematic view of a sixth package structure according to an embodiment of the present invention;

fig. 15 is a schematic view of a seventh package structure according to an embodiment of the present invention;

fig. 16 is a schematic view of an eighth package structure according to an embodiment of the present invention;

fig. 17 is a schematic diagram of a ninth package structure according to an embodiment of the present invention.

Icon: 110-a first heat dissipation structure; 111-a bottom wall; 113-sidewalls; 115-supporting blocks; 116-heat dissipation grooves; 117-heat sink; 1171-a first heat sink block; 1173-a second heat sink block; 118-connecting ribs; 101-a first carrier; 102-an adhesive film layer; 103-a second carrier; 105-photomask plate; 107-a third carrier; 120-a first chip; 121-a first bonding pad; 130-a protective body; 140-first conductive pillars; 141-a first groove; 143-a through hole; 145-metal connection ends; 150-a dielectric layer; 151-a first dielectric layer; 152-patterning the openings; 153-a second dielectric layer; 155-a third dielectric layer; 156-groove; 160-wiring layers; 161-a first wiring layer; 163-a second wiring layer; 165-a metal layer; 171-a second chip; 173-a third chip; 175-a second pad; 176-third bond pad; 180-a first package; 181-electromagnetic shielding layer; 183-rewiring layer; 185-seventh chip; 190-substrate; 210-a first substrate; 220-a second heat dissipating structure; 230-a second conductive post; 231-fourth chip; 233-fifth chip; 241-a first insulating layer; 242-a first shielding layer; 243-a second insulating layer; 244-a second shielding layer; 245-a second package; 246-a third shielding layer; 310-a second substrate; 311-accommodating grooves; 321-a first component; 323-sixth chip; 325-second component.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.

It should be noted that the features of the various embodiments of the invention may be combined with each other without conflict.

In the prior art, layering phenomenon between a wiring layer and a dielectric layer is solved. In general, the wiring layer or the pad is subjected to sandblasting roughening treatment, but when the roughness of the wiring layer is roughened, the precision in patterning the pattern is lowered, and if the shape precision of the wiring pattern in the signal transmission path is lowered, the unstable phenomenon of the signal transmission characteristics is caused, and the signal transmission loss is increased. For example: in the transmission path of the 40GHz ultrahigh frequency signal, the longer the extension ratio of the path transmission path of the wiring layer is, the larger the transmission loss caused by the phenomenon that skin effect current generated by the wiring layer tends to flow on the surface of the wiring is when the wiring layer is roughened to improve the bonding force between the wiring layer and the dielectric layer, and the inductance effect is formed between the wiring layers by the current, so that the parasitic inductance generates the leakage phenomenon, and the phenomena of short circuit, overheating and the like between the wiring layers are caused.

In order to overcome at least one defect in the prior art, the embodiment provides a packaging method and a packaging structure, which can improve the binding force between a wiring layer and a dielectric layer, prevent layering and are beneficial to improving the heat dissipation performance of the packaging structure.

First embodiment

Referring to fig. 1 to 5, the present embodiment provides a packaging method, which includes:

s1: a first heat dissipation structure 110 is provided. Optionally, a first carrier 101 is provided, and a first heat dissipation structure 110 is mounted on the first carrier 101. The first heat dissipation structure 110 includes a supporting block 115, a bottom wall 111, and a side wall 113 protruding from the bottom wall 111, where the bottom wall 111 and the side wall 113 enclose a heat dissipation groove 116. The support block 115 is provided on a side of the bottom wall 111 remote from the side wall 113.

The adhesive film layer 102 may be rotationally sprayed on the first carrier 101 in an adhesive manner, the first heat dissipation structure 110 is fixedly adhered on the first carrier 101 through the adhesive film layer 102, the adhesive film layer 102 may be made of a polymer material such as epoxy resin, and the material may be separated from the first carrier 101 by irradiating UV light. The material of the first carrier 101 may be glass, silicon nitride, metal, or other materials, which plays a supporting role. Optionally, an end of the support block 115 remote from the bottom wall 111 is attached to the first carrier 101.

S2: mounting a first chip 120; the first heat dissipation structure 110 is disposed around the first chip 120; a first pad 121 is provided on one side of the first chip 120.

Optionally, a glue layer is spin-coated on the bottom wall 111, which is a low temperature heat curable glue. The first chip 120 is attached to the bottom wall 111 by an adhesive layer. Wherein the first bonding pad 121 of the first chip 120 faces upward. I.e. the side of the first chip 120 remote from the first pad 121 is adhered to the bottom wall 111.

S3: coating the first chip 120 to form a protective body 130; wherein the first pad 121 exposes the protective body 130.

Optionally, the periphery of the first chip 120 is filled and wrapped with the plastic sealing liquid by using an injection molding mode of a plastic sealing mold, so as to form a protective body 130 of plastic sealing material, namely a plastic sealing body. And (5) baking and dehumidifying the plastic package body again. In this process, the first heat dissipation structure 110 can improve the supporting strength in the plastic package, and prevent the warpage phenomenon caused by the internal stress of the plastic package in the curing process when the first carrier 101 on the back is released. In addition, the supporting blocks 115 of the first heat dissipation structure 110 can also promote the bonding force between the adhesive film layer 102 on the first carrier 101 and the bottom wall 111, that is, promote the bonding force between the first heat dissipation structure 110 and the first carrier 101, so that the structure is more stable.

It should be noted that the protecting body 130 completely covers the first chip 120 and the bottom wall 111, and partially covers the side wall 113. Wherein the first pad 121 exposes the protective body 130. In some embodiments, the protection body 130 may be disposed only in the heat dissipation groove 116 of the first heat dissipation structure 110, which is not limited herein. Optionally, the material of the protecting body 130 is powder molding compound prepared by mixing epoxy resin as matrix resin, high-performance phenolic resin as curing agent, filler such as silica micropowder and the like, and various additives.

S4: forming a first conductive pillar 140 within the protective body 130; the first conductive pillar 140 penetrates the protective body 130.

Optionally, a slot or hole is formed in the protective body 130, and a conductive medium is filled in the slot or hole to form the first conductive pillar 140. The manner of grooving or hole formation includes, but is not limited to, laser grooving, etching into grooves, machining into grooves, and the like. In this embodiment, a first groove 141 is formed on the protective body 130, a through hole 143 is formed at the bottom of the first groove 141, and the through hole 143 penetrates through the protective body 130 and the bottom wall 111; first conductive pillars 140 are formed within the vias 143. Specifically, a first groove 141 is formed on the protective body 130 by using a laser grooving method, the first groove 141 having a diameter D1 and a depth H1. A through hole 143 is formed at the bottom of the first groove 141, and the diameter of the through hole 143 is D2, and D2 is smaller than D1. The through hole 143 penetrates the protector 130 and the bottom wall 111. The first carrier 101 at the bottom serves as a stop layer for the opening of the via 143. Then, the first conductive post 140 is formed in the through hole 143 with the diameter D2 by using an electroplating process or a dispensing process, and then, the metal connection end 145 is formed on the upper end surface of the first conductive post 140 by using an electroplating process, and the upper end surface is the end surface of the first conductive post 140 far away from the bottom wall 111. The metal connection terminal 145 may be used as a bonding pad, and the metal connection terminal 145 includes a seed layer made of a multi-layer composite metal formed by copper and at least one of nickel, palladium and gold, so as to improve bonding force and solderability.

The first groove 141 is formed first, and then the through hole 143 is formed, so that the height of the first conductive column 140 can be reduced, and the depth of the through hole 143 can be reduced, thereby reducing the depth-to-width ratio of the through hole 143, reducing the difficulty of the process and improving the quality of the opening. Meanwhile, the first groove 141 is formed first, so that part of structural stress can be released in advance, the precision and quality of the formed through hole 143 are improved, and hidden cracks or damage is prevented. The metal connection terminal 145 is provided with a seed layer, which can improve the bonding force between the first conductive post 140 and the metal connection terminal 145, and the bonding force between the metal connection terminal 145 and the surface-mounted chip.

It will be appreciated that in some embodiments, the protective body 130 may also be a silicon plate. Optionally, the mounting silicon plate material forms the protective body 130; wherein, the plate is provided with a through groove, so that the first chip 120 is positioned in the through groove. Electrical connection posts are formed after the through holes in the silicon plate, which also enable vertical interconnection between the chip and wiring layer 160, or wiring layer 160 and wiring layer 160, or chip-to-chip. If the silicon plate is adopted for perforation, an etching process is utilized for perforation, an insulating layer is deposited on the hole wall to promote the binding force between the electric connection column and the hole wall of the silicon plate, and the insulating layer is utilized for preventing leakage current phenomenon and the like of the electric connection column.

In this embodiment, the protecting body 130 is preferably molded with the following advantages. First, the molding material has better insulativity and hygroscopicity than the silicon plate, can avoid the problems of corrosion, leakage current and the like in the process, reduces the process of depositing an insulating layer, and has simpler process. Second, in the silicon plate etching process, a long time etching for deeper through-silicon vias will result in a charge on the metal etch stop layer of shallower through-silicon vias, and this phenomenon may cause arcing to cause damage to the metal pillars and dishing of the silicon plate surface, resulting in non-uniformity of the wiring layer 160, etc. For the process of depositing an insulating layer on the hole wall, particularly for the hole structure with higher depth-to-width ratio and smaller diameter, the process has great difficulty, and the phenomena of hole blocking, metal column hollowness and the like are easy to occur. In addition, the silicon plate is used as a transfer substrate, the thermal expansion coefficient of the metal column material (such as copper) in the silicon perforation is different from that of the silicon plate, the phenomenon of cracking of the hole wall in the silicon perforation is easy to occur in the reliability process, and the phenomena of breakage, cracking and the like of the silicon material are extremely easy to occur after the silicon material is subjected to mechanical external force. The protective body 130 of the molding compound can better solve the defects, can effectively play a role in protection, and avoids phenomena such as breakage, cracks and the like of the silicon plate material after mechanical external force exists.

Alternatively, in some embodiments, the first conductive post 140 is formed by attaching the metal heat sink 117, and the metal heat sink 117 is embedded in and penetrates the protective body 130.

S5: a dielectric layer 150 and a wiring layer 160 are disposed on a side of the first chip 120 away from the first pad 121; wherein, the wiring layer 160 is electrically connected with the first conductive pillar 140, and the dielectric layer 150 wraps the wiring layer 160; the first heat dissipation structure 110 is connected to the dielectric layer 150.

Optionally, a second carrier 103 is provided, a film layer is rotationally sprayed on the protective body 130, the second carrier 103 is attached to the film layer, the second carrier 103 is separated from the protective body 130 by using a film, the protective body 130 and the second carrier 103 can be separated by irradiating UV light, and the film layer can be made of high polymer materials such as epoxy resin. The second carrier 103 may be glass, silicon nitride, metal, or the like. The second carrier 103 serves as a support. It can be understood that, since the first heat dissipation structure 110 is provided in this embodiment, the side wall 113 of the first heat dissipation structure 110 is higher than the protecting body 130. When the second carrier 103 is mounted, the second carrier 103 is mounted on the side wall 113, and the side wall 113 also plays a supporting role.

In the overturning structure, the second carrier 103 faces downwards, and the first carrier 101 faces upwards. UV light is irradiated on the back surface of the first carrier 101 to separate the first carrier 101 and the first heat dissipation structure 110. In this embodiment, the first carrier 101 is separated from the support block 115. Plasma cleaning is performed again, and the surface of the first carrier 101 is bombarded with plasma to remove residual glue, so that the supporting block 115 is leaked. In this state, the support block 115 faces upward.

Optionally, the dielectric layer 150 includes a first dielectric layer 151, a second dielectric layer 153, and a third dielectric layer 155, and the wiring layer 160 includes a first wiring layer 161 and a second wiring layer 163; the step S5 comprises the following steps:

s51: a first dielectric layer 151 is disposed on a side of the bottom wall 111 remote from the first chip 120. Namely, the dielectric layer 150 and the wiring layer 160 are provided on the side of the bottom wall 111 where the support block 115 is provided; optionally, support blocks 115 are embedded in dielectric layer 150. The first dielectric layer 151 is coated using a chemical vapor deposition process (CVD) or a spin-on coating.

S52: a photomask 105 is covered on the first dielectric layer 151 to form a patterned opening 152, and a first wiring layer 161 is formed in the patterned opening 152; wherein the photomask plate is placed on the supporting block 115. Optionally, after forming the patterned opening 152, the first dielectric layer 151 is baked, so that the first dielectric layer 151 is changed from semi-solid state to solid state, and the structure is more stable. Then, metal is electroplated in the patterned opening 152, and copper is used as the metal to form the first wiring layer 161. In the process, the photomask 105 is covered on the supporting block 115, the height of the supporting block 115 is utilized to prevent the photomask 105 from directly contacting the first dielectric layer 151, and the supporting block 115 can prevent the photomask 105 from being adhered to the first dielectric layer 151 and prevent the supporting block 115 from playing a partition role, so that the phenomena of overlarge forming line width of the pattern layer, distortion of the pattern layer and the like are caused by the interference and diffraction of a light source in the photomask process on the pattern layer of the photomask 105 due to the fact that the first dielectric layer 151 is in a semi-solidified state. The provision of the support blocks 115 is advantageous in improving wiring accuracy and quality.

S53: a second dielectric layer 153 is provided over the first wiring layer 161. The second dielectric layer 153 is coated by a Chemical Vapor Deposition (CVD) process or a spin-on process to protect the first wiring layer 161.

S54: the photomask 105 is covered on the second dielectric layer 153, and the second dielectric layer 153 is baked by exposing and developing to form a patterned opening 152, so that the second dielectric layer 153 is changed from semi-solid state to solid state, and the structure is more stable. And metal is plated in the patterned opening 152, with copper, to form the second wiring layer 163. Wherein the photomask plate is placed on the supporting block 115; the second wiring layer 163 and the first wiring layer 161 are electrically connected. The support blocks 115 also serve a supporting, isolating function in the process, similar to the function in step S52.

S55: a third dielectric layer 155 is provided on the second wiring layer 163. Optionally, the third dielectric layer 155 is coated using a chemical vapor deposition process (CVD) or spin-on coating to protect the second wiring layer 163.

In the process, the wiring process is performed on the surface of the hole, and the packaging integration level is improved by using the wiring process, so that the insulation characteristic of the protective body 130 is effectively utilized, and the leakage phenomenon, the skin effect, the parasitic inductance and the like of the first conductive column 140 are avoided.

S6: a metal layer 165 is formed on the dielectric layer 150, and the metal layer 165 and the wiring layer 160 are electrically connected.

Optionally, a groove 156 is formed in the third dielectric layer 155, and a metal layer 165 is formed in the groove 156; the metal layer 165 and the second wiring layer 163 are electrically connected. The third dielectric layer 155 is grooved or perforated by laser drilling or etching. A metal layer 165 is electroplated in the recess 156, which is copper layer, to form a bonding pad. Optionally, the recess 156 is filled with copper, i.e., the bottom end of the pad is a copper pillar. And forming a UBM layer on the surface of the copper pillar, wherein the UBM layer can be made of titanium or titanium-tungsten. The UBM layer is a surface bump protruding from the third dielectric layer 155. The solder ball welding property of the UBM layer can be improved by forming the UBM layer, the bonding force between the bonding pad and the solder ball is improved, and the reliability is improved.

It should be noted that, the materials of the first dielectric layer 151, the second dielectric layer 153, and the third dielectric layer 155 may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, and the like, and the metal connection end 145 connects the chip pad with the first conductive pillar 140, so as to realize an electrical conduction function.

In some embodiments, the metal layer 165 and the support block 115 may be electrically connected. I.e., the surface of the third dielectric layer 155 is flush with the end surface of the support block 115, a UBM layer is formed on the third dielectric layer 155 at a position corresponding to the support block 115 so that the metal layer 165 and the support block 115 are electrically connected. It is easy to understand that the supporting block 115 is made of metal, and the whole first heat dissipation structure 110 is made of metal. In this way, the UBM layer corresponding to the supporting block 115 is conveniently grounded, so that the supporting block 115 is grounded, the shielding function is conveniently realized later, and static electricity is introduced outside the packaging structure.

UV light is irradiated on the back surface of the second carrier 103 to separate the sidewall 113 and the second carrier 103 and the protector 130 and the second carrier 103. Plasma cleaning is performed again, and the surface of the second carrier 103 is bombarded by plasma to remove the residual glue, so that the side wall 113 of the first heat dissipation structure 110, the first bonding pad 121 of the first chip 120 and the metal connection end 145 of the end face of the first conductive post 140 on the protection body 130 are leaked.

S7: a second chip 171 and/or a third chip 173 are attached to a side of the first chip 120 where the first bonding pad 121 is provided; wherein the second chip 171 is electrically connected to the first chip 120 and the first conductive pillar 140, respectively, and/or the third chip 173 is electrically connected to the first chip 120 and the first conductive pillar 140, respectively.

Optionally, the structure is flipped. The notch of the heat dissipation groove 116 faces upward, i.e., the first pad 121 of the first chip 120 faces upward. The second chip 171 and the third chip 173 are mounted on the first chip 120 and the protective body 130 using a flip-chip process. It is understood that the second chip 171 and the third chip 173 may be attached only one, that is, the number and kind of attached chips may be flexibly set according to practical situations, which is not particularly limited herein. In this embodiment, the second chip 171 and the third chip 173 are attached at the same time. The second chip 171 and the third chip 173 include a second pad 175 and a third pad 176, respectively. The second pad 175 is soldered to the first pad 121 of the first chip 120, and the third pad 176 is soldered to the first conductive post 140. Alternatively, the second chip 171 and the third chip 173 may be disposed in bilateral symmetry, so that the structure is more stable and the stress distribution is more uniform. In this package structure, the first chip 120 is electrically connected to the wiring layer 160 through the second chip 171 and the third chip 173. The device has the advantages of small volume, compact structure, high chip density and rich functional integration. And the transmission path is short, and the loss is low.

It will be appreciated that the second chip 171 and the first chip 120 may be directly soldered or may be indirectly electrically connected through other mediums. Similarly, the third chip 173 and the first chip 120 may be directly soldered or may be indirectly electrically connected through other mediums. For example, other media may be indirectly electrically connected by wire bonding, or by providing a redistribution layer 183 (see fig. 11).

S8: the second chip 171 and/or the third chip 173 are molded to form a first package 180.

And filling the periphery of the chip with plastic package liquid by using a printing mode or a plastic package mold injection mode again to form a first package 180. It is understood that the first package 180 performs plastic package protection for the second chip 171 and the third chip 173. Of course, if only the second chip 171 or the third chip 173 is provided, the first package 180 performs plastic package protection on the second chip 171 or the third chip 173.

Ball placement is performed on the metal layer 165 over the dielectric layer 150. The first package 180 is cut into individual products, and the packaging process is completed. The packaging method belongs to 2.5D packaging, and a 2.5D packaging structure is manufactured.

In connection with fig. 6, it should be noted that, in some embodiments, the connection ribs 118 are disposed between the plurality of first heat dissipation structures 110, and the connection ribs 118 may connect the plurality of first heat dissipation structures 110 into a whole. Thus, the whole board is convenient to mount, and the packaging efficiency is higher. In addition, the connecting ribs 118 can also improve the strength of the first heat dissipation structure 110, so that the structure is more stable in the packaging process. And the first heat dissipation structure 110 can serve as a carrier to effectively support, so that the steps of providing the first carrier 101, removing the first carrier 101 and the like in the process can be omitted, the cost is reduced, and the packaging efficiency is improved. In a subsequent process of cutting into individual products, the connecting ribs 118 are cut out again.

In the packaging method, the first heat dissipation structure 110 includes a bottom wall 111, a side wall 113 and a supporting block 115, and the side wall 113 and the bottom wall 111 form a heat dissipation groove 116 at the upper part of the packaging structure, so as to improve heat dissipation performance. The chip is positioned in the heat dissipation groove 116, and has compact structure, small overall size, high packaging integration level and good heat dissipation performance. The sidewall 113 is also advantageous to promote the coupling force between the first package body 180 and the protective body 130, and the coupling force between the protective body 130 and the dielectric layer 150. Secondly, the arrangement of the supporting blocks 115 can improve the heat dissipation performance, and can play a role in supporting and isolating in the manufacturing process of the wiring layer 160, so that the wiring precision and quality are improved. In addition, the supporting block 115 is also advantageous to improve the coupling force of the wiring layer 160 and the dielectric layer 150. The first heat dissipation structure 110 serves as a whole, plays a good supporting and stabilizing role in the packaging structure, is more stable and reliable in structure and high in structural strength, and can prevent the problem of stress release and warping caused by carrier release and baking. The annular side wall 113 structure can reduce the impact of die flow on chip mounting during plastic packaging and avoid the chip offset problem. Secondly, the annular side wall 113 structure can also be used as a chip mounting alignment correction point, so that the mounting accuracy is improved. The supporting block 115 structure can improve the wiring accuracy, and the supporting block 115 structure can be used as a grounding point after the solder ball is manufactured, so that static electricity is led out to the outside, and the heat dissipation effect is improved. The first heat dissipation structure 110 can promote the binding force between the dielectric layer 150 and the wiring layer 160, reduce the roughening process on the wiring layer 160, and solve the skin effect generated by the wiring layer 160 in the conventional technology, namely, the phenomenon that current tends to flow on the surface of the wiring, so that the transmission loss caused by the phenomenon and the electric leakage phenomenon of the wiring layer 160 and the metal conductive column can be avoided by the supporting block 115.

The protective body 130 adopts the molding compound of the resin matrix, has better insulativity and hygroscopicity, avoids the corrosion and leakage current problems in the process of the silicon perforation, reduces the process of depositing the insulating layer, can effectively play a role in protection, avoids phenomena such as breakage, crack and the like which are extremely easy to occur after the protective body is subjected to mechanical external force, and has more reliable packaging quality.

The first chip 120 is disposed in the protection body 130, and the second chip 171 and the third chip 173 are stacked on the first chip 120, so that the integration level is high, the integration of a plurality of chiplets is realized, and the difficulty in manufacturing a chip process is reduced. The first chip 120 contacts the bottom wall 111, thereby greatly improving heat dissipation performance.

Second embodiment

Referring to fig. 7, in this embodiment, after step S8, step S9 is further included: an electromagnetic shielding layer 181 is disposed on the first package 180, and the electromagnetic shielding layer 181 is electrically connected to the sidewall 113. The first heat dissipation structure 110 is made of a conductive material, such as a metal material.

Optionally, after plastic packaging, if the side wall 113 of the first heat dissipation structure 110 protrudes out of the first package body 180, a polishing process may be used to polish the side wall 113 to be flush with the first package body 180. If the sidewall 113 of the first heat dissipation structure 110 is lower than the first package body 180, i.e. buried in the first package body 180, the first package body 180 can be polished by a polishing process until the sidewall 113 is exposed, so that the surface is smoother and smoother.

An electromagnetic shielding layer 181 is formed on the surface of the first package 180 by a metal sputtering PVD method, and the electromagnetic shielding layer 181 is a multi-layer structure of a metal material such as SUS stainless steel-copper-SUS stainless steel. Or the electromagnetic shielding layer 181 may be formed of a copper-cobalt-chromium multilayer structure. The whole sputtering mode is adopted, so that the production efficiency is higher. The electromagnetic shielding layer 181 is connected to the sidewall 113 of the first heat dissipation structure 110, and has an electromagnetic shielding effect to prevent electromagnetic interference between chips. Of course, in some embodiments, the electromagnetic shielding layer 181 may also be made of a shielding film material, such as a high polymer including a polyolefin film, a graphene film, a metal film, etc., and is disposed outside the first package 180 by adhering a film, and is electrically connected to the side wall 113, so as to also play a role in electromagnetic shielding.

Then, a solder ball is formed on the metal layer 165 on the dielectric layer 150 by a ball-implanting process. Alternatively, the end surface of the supporting block 115 may be implanted with balls. And then cutting the packaging structure into single pieces by using a cutting process and adopting a resin cutting knife to complete the manufacturing process. It should be noted that the above steps may also be adaptively adjusted, such as first implanting balls and then forming the electromagnetic shielding layer 181, which is not particularly limited herein.

In this embodiment, the first heat dissipation structure 110 is made of metal, and is grounded, so as to have an electromagnetic shielding function, and prevent electromagnetic interference between chips or interference between chips and components. After the end face of the supporting block 115 is planted with balls, the supporting block can serve as a grounding point to lead out static electricity to the outside of the packaging structure and improve the heat dissipation effect of the static electricity.

Other parts of the content not mentioned in this embodiment are similar to those described in the previous embodiment, and will not be repeated here.

Third embodiment

Referring to fig. 8, in this embodiment, the protective body 130 is molded with a resin matrix. The first heat dissipation structure 110 includes a heat dissipation block 117, and the heat dissipation block 117 is disposed around the first chip 120. Optionally, the protective body 130 is provided with multiple layers of first conductive pillars 140 in the circumferential direction, two layers are shown, and the first layer surrounds the periphery of the first chip 120. The second layer is located at the periphery of the first layer and also surrounds the periphery of the first chip 120. Wherein the first layer and the second layer conductive pillars are electrically connected to the second chip 171, respectively, and the first layer and the second layer conductive pillars are electrically connected to the third chip 173, respectively. The heat sink 117 is disposed between the first layer and the second layer conductive pillars. The heat sink 117 serves to support, buffer and dissipate heat. Alternatively, the heat dissipation block 117 may be disposed between the first layer conductive pillar and the first chip 120, and around the periphery of the first chip 120, or the heat dissipation block 117 is disposed on a side of the second layer conductive pillar away from the first layer conductive pillar. It should be understood that the number of layers of the first conductive pillars 140 in the circumferential direction is not limited to two layers as illustrated, and the number of each layer of the first conductive pillars 140 seen in the cross section may be three, one, two or four, five, etc. The number of layers in the circumferential direction may be one, three, four, five or more.

Alternatively, the height of the heat dissipation block 117 is approximately equal to the height of the protection body 130, that is, the heat dissipation block 117 is embedded in the protection body 130, and the height of the heat dissipation block 117 is approximately equal to the height of the first chip 120, so that a good heat dissipation effect can be achieved on the first chip 120.

It will be appreciated that the heat dissipation block 117 may be mounted on the carrier by attaching the heat dissipation block 117 and the first chip 120 at intervals, and the heat dissipation block 117 is disposed around the first chip 120, and then the packaging is completed according to the steps described in the first embodiment. Preferably, the heat dissipation block 117 or the first conductive pillar 140 is disposed closely adjacent to the outer periphery of the first chip 120, and has a compact structure and a good heat dissipation effect.

With reference to fig. 9, optionally, the heat dissipation block 117 in the first heat dissipation structure 110 is made of metal, so that better heat dissipation performance is achieved. In addition, in some embodiments, the heat dissipation block 117 made of metal may replace the first conductive pillar 140 to perform an electrical connection function, so that the forming process of the first conductive pillar 140 in the first embodiment is omitted.

Specifically, if the first conductive post 140 is formed by using the mounting heat dissipation block 117 instead of electroplating, one process that can be implemented is as follows: the first heat dissipation structure 110 includes a side wall 113, a bottom wall 111, a supporting block 115 and a heat dissipation block 117, where the bottom wall 111 and the side wall 113 are connected to form a heat dissipation groove 116, the supporting block 115 is disposed on a side of the bottom wall 111 away from the side wall 113, and the heat dissipation block 117 is connected to a side of the bottom wall 111 close to the side wall 113 and is located in the heat dissipation groove 116. With the foregoing steps S1 to S3, the first chip 120 is mounted in the heat dissipation groove 116, and the heat dissipation block 117 is located at the periphery of the first chip 120. The first chip 120 is molded to form a protective body 130.

Referring to fig. 10, S41: the supporting block 115 is turned upward, the supporting block 115 and the bottom wall 111 are ground and removed by a grinding process, one end surfaces of the side wall 113 and the heat sink 117 near the bottom wall 111 are exposed, and the wiring layer 160 and the dielectric layer 150 are formed on the end surfaces by a fan-out process. Alternatively, both the side wall 113 end face and the heat dissipation block 117 end face are fan-out arranged, and electrically connected with the wiring layers 160, respectively. Alternatively, the end surface of the sidewall 113 may not be electrically connected to the wiring layer 160.

S42: the structure is turned over so that the side with the wiring layer 160 and the dielectric layer 150 faces downward, the first pad 121 of the first chip 120 faces upward, and the portion of the sidewall 113 above the protective body 130 is polished and removed by a polishing process. I.e., the end of the sidewall 113 remote from the wiring layer 160 is ground such that the end of the sidewall 113 remote from the wiring layer 160 is flush with the first pad 121. Alternatively, an end surface of the side wall 113 and the heat sink 117 remote from the wiring layer 160 is flush with the surface of the protective body 130 and is in the same plane as the first pad 121. In this way, it is convenient to continue stacking the second chip 171 and the third chip 173 on the first chip 120. The second chip 171 is electrically connected to the heat sink 117, and the second chip 171 is electrically connected or disconnected to the side wall 113. The third chip 173 is electrically connected to the heat sink 117, and the third chip 173 is electrically connected or disconnected to the side wall 113.

In the process, the first heat dissipation structure 110 is processed into the conductive column structure with heat dissipation and electric connection functions by adopting a twice grinding process, so that the step of forming the first conductive column 140 by punching an electroplated metal on the protective body 130 is omitted, the process is simpler, the efficiency is high, and the operability is strong. It is to be understood that, in the polishing process, the third carrier 107 may be added appropriately according to actual needs to perform supporting and protecting functions. After the corresponding steps are completed, the third carrier 107 is removed. In addition, a roughening effect may be achieved by grinding, improving the bonding force between the first heat dissipation structure 110 and the wiring layer 160, and improving the bonding force between the protective body 130 and the dielectric layer 150.

Optionally, after the sidewall 113 is polished, a redistribution layer 183 may be further disposed on a side of the first heat dissipation structure 110 away from the dielectric layer 150, and the second chip 171 and the third chip 173 may be attached to the redistribution layer 183. The redistribution layer 183 is electrically connected to the first heat dissipation structure 110, and in this embodiment, the redistribution layer 183 is electrically connected to the heat dissipation block 117, and the first chip 120 is electrically connected to the second chip 171 and the third chip 173 through the redistribution layer 183. Alternatively, the rewiring layer 183 may be electrically connected to the side wall 113, or to the side wall 113 and the heat sink 117, respectively. The polishing process can also improve the bonding force between the first heat dissipation structure 110 and the redistribution layer 183.

Referring to fig. 11, in the first heat dissipating structure 110, the heights of the side wall 113 and the heat dissipating blocks 117 may be different, and the heights of the plurality of heat dissipating blocks 117 may not be identical. This makes it possible to form high and low conductive pillars, thereby forming a plurality of stacked structures in the height direction. The heat sink 117 includes a first heat sink 1171 and a second heat sink 1173, the first heat sink 1171 being lower than the second heat sink 1173, the second heat sink 1173 being located at the periphery of the first heat sink 1171, and the side wall 113 being located at the periphery of the second heat sink 1173. The second chip 171 and the third chip 173 are connected to the first heat dissipation block 1171, and are located in an area surrounded by the second heat dissipation block 1173. An electromagnetic shielding layer 181 may be disposed on the top of the second heat dissipating block 1173 to provide electromagnetic shielding. The top of the sidewall 113 may continue to route the redistribution layer 183 and continue to stack other chips or components, such as the seventh chip 185 in the figure, on the redistribution layer 183.

Of course, the electromagnetic shielding layer 181 may be omitted. The other chips continue to be stacked on the second heat spreader 1173 or the redistribution layer 183 is stacked. Wherein the heights of the side wall 113 and the second heat sink 1173 may be the same or different. The side wall 113 and the heat sink 117 may be provided with various height differences according to the number of layers actually stacked, for example, the side wall 113 is higher than the second heat sink 1173, and the second heat sink 1173 is higher than the first heat sink 1171, which is not particularly limited herein.

It is easily understood that in some embodiments, the supporting blocks 115 and the bottom wall 111 in the first heat dissipation structure 110 may also remain, or the first heat dissipation structure 110 may be designed to include only the side wall 113 and the heat dissipation block 117, so that the step of grinding the bottom wall 111 and the supporting blocks 115 may be omitted, thereby improving the packaging efficiency. The support block 115 and bottom wall 111 may be selectively ground to be removed completely or partially.

Optionally, the first heat dissipation structure 110 includes a heat dissipation block 117 and a side wall 113, where the heat dissipation block 117 is disposed around the periphery of the first chip 120; the side wall 113 is arranged on a layer of the heat dissipation block 117 away from the first chip 120; one end of the heat sink 117 is connected to the substrate 190 or penetrates through the substrate 190, and the other end is flush with or higher than a side of the first chip 120 away from the substrate 190.

Optionally, as shown in fig. 11, the side wall 113 and the heat dissipation block 117 are ground to different heights, or the side wall 113 and the heat dissipation block 117 with different heights are designed in the first heat dissipation structure 110, for example, the side wall 113 is higher than the heat dissipation block 117, and stacking can be further performed on the side wall 113 and the heat dissipation block 117, for example, devices such as a circuit layer or a mounted chip are arranged, so as to realize multi-layer packaging and improve the integration level.

Fourth embodiment

Referring to fig. 12, in some embodiments, the first heat dissipation structure 110 may be configured to include only a heat dissipation block 117, where the heat dissipation block 117 is located between the first layer conductive pillars and the second layer conductive pillars and is located around the first chip 120; and, one end of the heat sink 117 is flush with the surface of the protective body 130, and the other end is flush with the surface of the dielectric layer 150 remote from the first chip 120. In this way, the heat dissipation block 117 plays a role of not only dissipating heat but also improving the bonding force between the wiring layer 160 and the dielectric layer 150. In this manner, the heat dissipation block 117 and the second chip 171 or the third chip 173 may be electrically connected or disconnected, and the end of the heat dissipation block 117 remote from the second chip 171 may be ball-mounted or not ball-mounted, which is not particularly limited herein. The first heat dissipation structure 110 may also be made of resin, ceramic, or other non-metallic materials without electrical connection.

Fifth embodiment

Referring to fig. 13, alternatively, the first heat dissipation structure 110 may be designed to include only the sidewall 113, where the sidewall 113 is located on a side of the second layer conductive pillar away from the first layer conductive pillar. The bottom end of the sidewall 113 is flush with the bottom end of the first chip 120, in other words, the bottom end of the sidewall 113 is flush with the bottom end of the protector 130, and the other end of the sidewall 113 is higher than the upper surface of the protector 130. Optionally, the top end of the sidewall 113 is higher than the upper surface of the second chip 171. By this arrangement, heat of the first chip 120, the second chip 171, and the third chip 173 can be radiated to the outside with a better heat radiation effect.

Sixth embodiment

Referring to fig. 14, alternatively, the first heat dissipation structure 110 may be designed to include only the side wall 113 and the bottom wall 111, and the side wall 113 and the bottom wall 111 are connected to form the heat dissipation groove 116. The first chip 120 is mounted on the bottom wall 111 and is located in the heat dissipation groove 116. The top end of the sidewall 113 is higher than the upper surface of the protector 130. Optionally, the top end of the sidewall 113 is higher than the upper surface of the second chip 171. By this arrangement, heat of the first chip 120, the second chip 171, and the third chip 173 can be radiated to the outside with a better heat radiation effect.

Seventh embodiment

Alternatively, in connection with fig. 15, the present embodiment employs a multilayer stacked structure. The packaging method further comprises a step S10.

S10: a first substrate 210 and a second heat dissipation structure 220 attached to the first substrate 210 are disposed on a side of the metal layer 165 away from the first package 180; wherein, the fourth chip 231 and the fifth chip 233 are mounted in the second heat dissipation structure 220; the fourth chip 231 and the fifth chip 233 are electrically connected to the metal layer 165, respectively. The heat dissipation grooves in the second heat dissipation structure 220 are larger than the heat dissipation grooves 116 (see fig. 1) of the first heat dissipation structure 110, and the heat dissipation grooves of the second heat dissipation structure 220 can completely accommodate the first heat dissipation structure 110, and the chip, the wiring layer 160, and the dielectric layer 150 on the first heat dissipation structure 110.

In this embodiment, the first heat dissipation structure 110 and the second heat dissipation structure 220 respectively include a bottom wall 111, a side wall 113, and a supporting block 115. The first substrate 210 may be a substrate, a lead frame, a ceramic substrate, a PCB board, an epoxy fiberglass cloth substrate, silicon dioxide or silicon nitride, etc.

Optionally, second conductive pillars 230 are formed; one end of the second conductive pillar 230 is electrically connected to the first substrate 210, and the other end is electrically connected to the metal layer 165. In this embodiment, the second conductive pillars 230 are located at positions corresponding to the positions of the first chips 120, and are located approximately in the middle, so as to implement vertical interconnection between the solder balls on the metal layer 165 and the first substrate 210. The fourth chip 231 and the fifth chip 233 are located at both sides of the second conductive post 230.

Alternatively, the first substrate 210 is fabricated using steps S5 and S6. The wiring layer 160 and the dielectric layer 150 may be formed using a fan-out process. Of course, a pre-prepared substrate finished product may also be used, and is not particularly limited herein. The number of stacked chips is more, the integration level is high, the structure is compact, and the heat dissipation performance is good. Optionally, the side wall 113 of the first heat dissipation structure 110 is higher than the side wall 113 of the second heat dissipation structure 220.

Alternatively, a first insulating layer 241 is formed on the outer sides of the second chip 171 and the third chip 173; forming a first shielding layer 242 outside the first insulating layer 241, the first shielding layer 242 being electrically connected to the sidewall 113 of the first heat dissipation structure 110; a second insulating layer 243 is formed outside the first shielding layer 242. A second shielding layer 244 is formed on the outer side of the second insulating layer 243, and the second shielding layer 244 is electrically connected to the sidewall 113 of the second heat dissipation structure 220. Wherein, the first insulating layer 241 is located in the heat dissipation groove 116 of the first heat dissipation structure 110. An underfill layer may be formed using a dispensing process, encapsulating the upper guard 130 and the stack. The first shielding layer 242 wraps the first heat dissipation structure 110, is located outside the heat dissipation groove 116 of the first heat dissipation structure 110, and is electrically connected to the sidewall 113 of the first heat dissipation structure 110. The first shielding layer 242 may be formed using a dispensing process. The second insulating layer 243 is located in the heat dissipation groove 116 of the second heat dissipation structure 220. The second shielding layer 244 covers the second heat dissipation structure 220, is located outside the heat dissipation groove 116 of the second heat dissipation structure 220, and is electrically connected to the sidewall 113 of the second heat dissipation structure 220. The second insulating layer 243 and the second shielding layer 244 may also be formed using a dispensing process. The arrangement has a multi-layer electromagnetic shielding effect, can realize shielding partition and prevent electromagnetic interference between chips.

In addition, the insulating layer serves to prevent conductive particles of the shielding glue layer from entering the internal structure of the chip. The side walls 113 in the first heat dissipation structure 110 and the second heat dissipation structure 220 form a blocking wall, which limits the insulating layer to the inside of the blocking wall, so that insufficient thickness of the shielding colloid layer is avoided, and the shielding performance is attenuated. The multi-layer heat dissipation structure greatly improves the heat dissipation performance of the packaging structure. And a runner structure is formed among the multi-layer radiating structures, so that the air flow mobility is enhanced, better heat dissipation is realized, and the runner structure can promote the capillary action of glue in the dispensing process, and the filling performance and the binding force of the runner structure are improved.

Eighth embodiment

In connection with fig. 16, a multilayer shielding structure is provided in this embodiment. In comparison with the seventh embodiment, only one shielding layer and insulating layer are provided in the structure. In the seventh embodiment, two insulating layers and two shielding layers are provided.

Optionally, the packaging method further includes: a second package 245 is disposed, and the second package 245 encapsulates the first heat dissipation structure 110, the fourth chip 231, and the fifth chip 233. A third shielding layer 246 is disposed on the outer side of the second package body 245, and the third shielding layer 246 is electrically connected to the sidewall 113 of the second heat dissipation structure 220. The second package 245 encapsulates the first heat dissipation structure 110 and is located in the heat dissipation groove 116 of the second heat dissipation structure 220, so as to perform an insulation protection function. The third shielding layer 246 wraps the second heat dissipation structure 220, is located outside the heat dissipation groove 116 of the second heat dissipation structure 220, and is electrically connected to the sidewall 113 of the second heat dissipation structure 220. By the arrangement, the electromagnetic shielding effect on the multilayer packaging structure is realized, and electromagnetic interference between chips can be prevented.

Optionally, the side wall 113 of the first heat dissipation structure 110 is substantially flush with the side wall 113 of the second heat dissipation structure 220, so that only one insulating layer and one shielding layer can be formed, the process steps can be reduced, the packaging efficiency can be improved, and the heat dissipation performance is good.

Ninth embodiment

In conjunction with fig. 17, optionally, the packaging method further includes: providing a second substrate 310; wherein, the second substrate 310 is provided with a containing groove 311; mounting the semi-finished products obtained in the steps S1 to S7 in the accommodating groove 311; wherein the metal layer 165 is electrically connected to the second substrate 310. The depth of the accommodating recess 311 corresponds to the overall height of the semi-finished product, such that the upper surface of the protective body 130 is substantially in the same plane as the upper surface of the second substrate 310.

The first device is mounted on the second substrate 310 and/or the second device is mounted on the second substrate 310 and the protective body 130 of the semi-finished product. Wherein one end of the second device is connected to the second substrate 310 and the other end is electrically connected to the first conductive pillar 140 of the semi-finished product.

It is understood that the first device includes a first component 321 and a sixth chip 323, and the first component 321 and the sixth chip 323 are disposed on two sides of the accommodating recess 311. The second device is a second component 325, where the second component 325 is a common device between the second substrate 310 and the protective body 130, and one end of the second component 325 is connected to the upper surface of the second substrate 310, and the other end is electrically connected to the first conductive pillar 140 of the protective body 130. The first conductive post 140 may be formed by electroplating, or may be a part of the first heat dissipation structure 110, for example, may be the heat dissipation block 117 or the side wall 113 in the first heat dissipation structure 110.

Optionally, the second substrate 310 and the first conductive pillars 140 on the protective body 130 may also be connected using wire bonding.

The first device and the second device can be selectively mounted according to actual conditions, such as alternative mounting of the first device and the second device. The mounting positions and the number thereof can be flexibly adjusted, and are not particularly limited herein.

It will be appreciated that the 2.5D package structure semi-finished product is stacked on the second substrate 310, and the passive devices are electrically connected to the upper surface circuit layer of the 2.5D package structure, so as to shorten the transmission path, and share one second component 325. The passive device is attached to the upper portion of the accommodating groove 311, so that the problem of tin bridging at the bottom of the passive device in the conventional technology is avoided, and the active device is attached again. Here, the passive devices are the first device 321 and the second device 325 in the figure, and may be an inductor or the like. The devices on two sides of the passive device are covered with tin solder, and are connected and fixed through reflow soldering. The active device, such as the sixth chip 323 in the figure, may be a radio frequency chip, a logic chip, a memory chip, or the like. The second substrate 310 may be a substrate, a lead frame, a ceramic substrate, a PCB board, an epoxy fiberglass cloth substrate, silicon dioxide or silicon nitride, etc.

What is not mentioned in the present embodiment is similar to that in the foregoing embodiments. The above embodiments may be combined with each other without conflict.

Note that among the first chip 120, the second chip 171, the third chip 173, the fourth chip 231, and the fifth chip 233, the logic chip may be used for the first chip 120. The second chip 171 and the third chip 173 may be HBM (High Bandwidth Memory) high-bandwidth memory chips. The fourth chip 231 and the fifth chip 233 may be SOC chips, for example, the fourth chip 231 is an ASIC chip and the fifth chip 233 is an FPGA chip. The high-bandwidth storage is realized through the micro-bumps of the HBM chip, the logic chip controls the HBM chip, and the SOC chip stack is placed in the substrate again, so that more functional chips are integrated in the same packaging structure, and the functions of the packaging structure are improved.

Tenth embodiment

Referring to fig. 1 to 17, an embodiment of the present invention further provides a packaging structure, which is manufactured by using the packaging method according to any one of the foregoing embodiments. The package structure includes a substrate 190, a first chip 120, a first heat dissipation structure 110, a protection body 130, and a second chip 171, wherein the first chip 120 is connected to the substrate 190. The first heat dissipation structure 110 includes a sidewall 113, the sidewall 113 is connected to the substrate 190, and the sidewall 113 is disposed around the periphery of the first chip 120. The protecting body 130 is connected to the substrate 190, and the protecting body 130 is provided with a through slot, and the first chip 120 is located in the through slot. The second chip 171 is mounted on a side of the first chip 120 away from the substrate 190; the second chip 171 is electrically connected to the substrate 190 and the first chip 120, respectively. The substrate 190 includes the wiring layer 160, the dielectric layer 150, and the metal layer 165 in the foregoing embodiments. The number and the positions of the second chips 171 may be flexibly set according to actual conditions.

Optionally, the package structure further includes a first conductive pillar 140 penetrating through the protective body 130, where one end of the first conductive pillar 140 is electrically connected to the second chip 171, and the other end is electrically connected to the substrate 190. Alternatively, one end of the sidewall 113 is connected to the substrate 190 or penetrates the substrate 190, and the other end is flush with or higher than a side of the first chip 120 away from the substrate 190.

Optionally, the first heat dissipation structure 110 further includes a bottom wall 111, where the bottom wall 111 is connected to the side wall 113, and the bottom wall 111 and the side wall 113 form a heat dissipation groove 116; the bottom wall 111 is connected with the base 190, and the first chip 120 is arranged on the bottom wall 111; the first conductive post 140 penetrates the protective body 130 and the bottom wall 111. The first conductive post 140 may be formed by electroplating through an opening in the protective body 130, or may be formed by attaching the heat dissipation block 117 together when attaching the first heat dissipation structure 110, which is not particularly limited herein.

Optionally, the first heat dissipation structure 110 further includes a supporting block 115, where the supporting block 115 is disposed on a side of the bottom wall 111 away from the side wall 113; the support blocks 115 are buried or extend through the substrate 190. Optionally, the support block 115 is connected to a ground line of the substrate 190; the first heat dissipation structure 110 is made of metal. The support block 115 can support, partition and dissipate heat.

The packaging structure further comprises a shielding layer and a first packaging body 180, wherein the first packaging body 180 coats the second chip 171 and the first heat dissipation structure 110, and the shielding layer is arranged on one side, far away from the substrate 190, of the first packaging body 180; the shield layer is electrically connected to the sidewalls 113.

Optionally, the package structure further includes a first substrate 210 and a second heat dissipation structure 220 disposed on the first substrate 210. The second heat dissipation structure 220 includes a heat dissipation groove 116 surrounded by the bottom wall 111 and the side wall 113; a fourth chip 231 is arranged in the heat dissipation groove 116; the base 190 is disposed on a side of the fourth chip 231 away from the first substrate 210; the fourth chip 231 is electrically connected to the substrate 190; the base 190 and the first substrate 210 are electrically connected. The number and positions of the fourth chips 231 may be flexibly set according to actual situations.

Optionally, the package structure further includes a second conductive post 230; one end of the second conductive post 230 is connected to the base 190, and the other end is connected to the first substrate 210.

Optionally, a first insulating layer 241 is disposed on the outer side of the second chip 171; the first insulating layer 241 has a first shielding layer 242 disposed on an outer side thereof, and the first shielding layer 242 is electrically connected to the sidewall 113 of the first heat dissipation structure 110. The second insulating layer 243 is disposed on the outer side of the first shielding layer 242, the second shielding layer 244 is disposed on the outer side of the second insulating layer 243, and the second shielding layer 244 is electrically connected to the sidewall 113 of the second heat dissipation structure 220.

Optionally, the package structure further includes a second package 245, and the second package 245 encapsulates the first heat dissipation structure 110 and the fourth chip 231. The third shielding layer 246 is disposed on the outer side of the second package body 245, and the third shielding layer 246 is electrically connected to the sidewall 113 of the second heat dissipation structure 220.

Optionally, the package structure further includes a second substrate 310, where the second substrate 310 is provided with a receiving recess 311. The substrate 190 is disposed in the accommodating recess 311; wherein the base 190 is electrically connected to the second substrate 310. The second substrate 310 is attached with a first device; and/or attaching a second device to the second substrate 310 and the protective body 130, wherein one end of the second device is connected to the second substrate 310, and the other end is electrically connected to the first conductive post 140 on the protective body 130.

It should be noted that the first heat dissipating structure 110 may include only the side wall 113, only the heat dissipating block 117, only the bottom wall 111 and the side wall 113, or the side wall 113 and the heat dissipating block 117, or the bottom wall 111, the side wall 113, the heat dissipating block 117 and the supporting block 115, or the bottom wall 111, the side wall 113 and the supporting block 115, etc., which are not particularly limited herein.

Other matters not mentioned in the present embodiment are similar to those described in the first to ninth embodiments, and are not particularly limited here.

In summary, the beneficial effects of the embodiment of the invention include:

according to the packaging method and the packaging structure provided by the embodiment of the invention, the heat dissipation structure is attached to the substrate 190, so that the heat dissipation performance of the structure can be improved. Meanwhile, the heat dissipation structure is connected with the dielectric layer 150, so that the bonding force between layers in the structure is improved, and the layering phenomenon of the structure is improved. The chip integration level is improved, and the structure is compact. The electromagnetic shielding function can be realized, and static electricity can be led out to the outside. It is advantageous to improve the wiring accuracy and quality of the wiring layer 160. The insulating material has good insulativity and hygroscopicity, avoids corrosion and leakage current problems in the process, reduces the process of depositing an insulating layer, and can effectively play a role in protection. Avoiding phenomena such as breakage, crack and the like which are extremely easy to occur after the silicon plate material has mechanical external force, and reducing the process difficulty. The heat dissipation structure can reduce the roughening process for the wiring layer 160, solve the skin effect generated after the roughening of the wiring layer 160 in the prior art, namely the transmission loss caused by the phenomenon that current tends to flow on the surface of the wiring, and avoid the leakage phenomenon of the wiring layer 160 and the metal conductive column. The whole packaging structure has high strength and can relieve the warping problem of the carrier after being released. The die flow impact on the chip after mounting during plastic packaging can be reduced, the offset problem is avoided, the heat dissipation structure can be used as a chip mounting alignment correction point, and the mounting precision is improved.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of packaging, comprising:

s1: providing a first heat dissipation structure; the first heat dissipation structure comprises a supporting block, a bottom wall and a side wall convexly arranged on the bottom wall, and the bottom wall and the side wall enclose a heat dissipation groove; the supporting block is arranged on one side of the bottom wall away from the side wall;

s5: a dielectric layer and a wiring layer are arranged on one side, far away from the first bonding pad, of the first chip; the wiring layer is electrically connected with the first conductive column, and the dielectric layer wraps the wiring layer; the first heat dissipation structure is connected with the dielectric layer; wherein the dielectric layer and the wiring layer are arranged on one side of the bottom wall provided with the supporting block; the supporting block is buried in the dielectric layer;

2. The packaging method according to claim 1, wherein step S1 includes:

step S4, removing the first carrier;

3. The packaging method according to claim 1, wherein step S2 includes:

and attaching the first chip to the bottom wall.

4. The packaging method of claim 1, wherein the dielectric layer comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and the wiring layers comprise a first wiring layer and a second wiring layer; the step S5 comprises the following steps:

s53: a second dielectric layer is arranged on the first wiring layer;

s55: a third dielectric layer is provided on the second wiring layer.

5. The packaging method according to claim 4, wherein in step S55, the metal layer and the supporting block are electrically connected.

6. The packaging method of claim 5, wherein the support block is grounded; the method further comprises the steps of:

7. The packaging method according to claim 1, wherein step S4 includes:

A first conductive post is formed within the via.

8. The packaging method according to claim 1, wherein in step S3:

9. The packaging method of claim 1, wherein the first heat dissipating structure comprises a bottom wall, a side wall, a support block, and a heat dissipating block, the bottom wall and the side wall being connected to form a heat dissipating recess; the support block is arranged on one side of the bottom wall far away from the side wall, and the heat dissipation block is connected to one side of the bottom wall close to the side wall and is positioned in the heat dissipation groove; the method further comprises the steps of:

grinding to remove the bottom wall and the supporting block after the step S4;

in step S5, at least one of the side wall and the heat dissipation block is electrically connected to the wiring layer;

in step S7, one end of the side wall and the heat dissipation block away from the wiring layer is ground, so that one end of the side wall and the heat dissipation block away from the wiring layer is flush with the first bonding pad; and attaching the second chip or the third chip to the side wall and the heat dissipation block.

10. The packaging method according to claim 1, wherein connecting ribs are arranged between the first heat dissipation structures.

11. The packaging method of claim 1, further comprising:

12. The packaging method of claim 11, wherein the first substrate is fabricated using steps S5 and S6.

13. The packaging method of claim 11, further comprising:

forming a second insulating layer outside the first shielding layer;

14. The packaging method of claim 11, further comprising:

15. The packaging method according to any one of claims 1 to 12, characterized by further comprising:

16. A package structure, characterized in that it is manufactured by the packaging method according to any one of claims 1 to 15.

17. The package structure of claim 16, comprising:

a substrate;

a first chip; the first chip is connected to the substrate;

18. The package structure of claim 17, further comprising a first conductive post extending through the protective body, one end of the first conductive post being electrically connected to the second chip and the other end being electrically connected to the substrate.

19. The package structure of claim 18, further comprising a redistribution layer disposed on a side of the first conductive pillar remote from the substrate and electrically connected to the first conductive pillar; the first chip and the second chip are respectively connected with the rewiring layer.

20. The package structure of claim 17, wherein one end of the sidewall is connected to or penetrates the substrate, and the other end is flush with or higher than a side of the first chip away from the substrate.

21. The package structure of claim 20, wherein the first heat dissipation structure further comprises a heat dissipation block, the heat dissipation block being disposed around the periphery of the first chip; the side wall is arranged on a layer of the heat dissipation block far away from the first chip; one end of the heat dissipation block is connected with or penetrates through the substrate, and the other end of the heat dissipation block is flush with or higher than one side, away from the substrate, of the first chip.

22. The package structure of claim 21, wherein the side walls and the heat sink are different in height; and/or the plurality of heat sinks may be different in height.

23. The package structure of claim 18, wherein the first heat spreading structure further comprises a bottom wall, the bottom wall and the side wall being connected, the bottom wall and the side wall forming a heat spreading groove; the bottom wall is connected with the substrate, and the first chip is arranged on the bottom wall; the first conductive post penetrates through the protective body and the bottom wall.

24. The package structure of claim 23, wherein the first heat dissipation structure further comprises a support block disposed on a side of the bottom wall remote from the side wall; the support blocks are embedded in or penetrate through the substrate.

25. The package structure of claim 24, wherein the support block is connected to a ground line of the substrate; the first heat dissipation structure is made of metal;

26. The package structure of claim 24, further comprising a first substrate and a second heat spreading structure disposed on the first substrate;

27. The package structure of claim 26, further comprising a second conductive post; one end of the second conductive column is connected with the base, and the other end of the second conductive column is connected with the first substrate.

28. The package structure of claim 26, wherein a first insulating layer is disposed on an outer side of the second chip; a first shielding layer is arranged on the outer side of the first insulating layer, and the first shielding layer is electrically connected with the side wall of the first heat dissipation structure;

29. The package structure of claim 26, further comprising a second package body that encapsulates the first heat spreader structure and the fourth chip;

30. The package structure according to any one of claims 17 to 25, further comprising a second substrate provided with a receiving recess;