CN113708785A - Anti-interference system for big data network transmission - Google Patents
Anti-interference system for big data network transmission Download PDFInfo
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- CN113708785A CN113708785A CN202111079933.0A CN202111079933A CN113708785A CN 113708785 A CN113708785 A CN 113708785A CN 202111079933 A CN202111079933 A CN 202111079933A CN 113708785 A CN113708785 A CN 113708785A
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- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
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Abstract
The invention discloses an anti-interference system for big data network transmission, which utilizes the principle that the current of a capacitor C1 leads the terminal voltage to lead the big data network signal to shift the phase by 180 degrees, and utilizes an operational amplifier AR2 to add the big data network signal with the big data network signal, utilizes a single continuous negative voltage of a sum signal to conduct a triode Q6, charges a capacitor C2, utilizes a single continuous positive voltage of the original sum signal to conduct a triode Q2, charges a capacitor C3, utilizes an operational amplifier AR4 to conduct differential operation on the voltage of the capacitor C2 or the voltage of the capacitor C3 and the divided voltage values of resistors R18-R19, respectively compares the obtained difference signals with the divided voltage values of resistors R24-R25 and the divided voltage values of resistors R27-R28 to detect the adjacent frequency interference state of the big data network signal digitally modulated by 2PSK, judges the distortion degree of the big data network signal waveform, and sends a +3.3V to a big data network signal waveform control terminal to perform early warning when the big data network signal is seriously distorted .
Description
Technical Field
The invention relates to the technical field of big data, in particular to an anti-interference system for big data network transmission.
Background
With the increasing popularity and maturity of information communication technology, big data comes along with the operation, and with its characteristics fast, that ageing is high, is widely applied to information communication industry, and big data is at communication system's transmission principle: the transmitter firstly performs digital modulation and power amplification on data to be transmitted to obtain a big data network signal, then wirelessly transmits the big data network signal by using an antenna transmitter, or performs wired transmission on the big data network signal by using a communication cable, a corresponding big data network signal receiver receives a large number of signals, a pre-filter therein performs band-pass filtering on the received large number of signals, selects the corresponding big data network signal and performs signal amplification, then transmits the signal to a demodulator to demodulate the big data network signal, restores the data and transmits the data to a big data control terminal for analysis;
however, due to the limitation of hardware circuit parameters of the pre-filter in the big data network signal receiver, the bandwidth of most pre-filters is not narrow enough, so that when the big data network signal receiver receives the big data network signal, the adjacent frequency interference signals also enter the big data network signal receiver, and the adjacent frequency interference signals will be mixed with the big data network signal, so that the waveform of the big data network signal is distorted seriously, especially the big data network signal modulated by adopting the 2PSK digital modulation mode, because of the signal phase inversion, after the big data network signal modulated by 2PSK and the adjacent frequency interference signal waveform are superposed, the conditions that the time length of a single continuous positive voltage and the time length of a single continuous negative voltage are different from the half period of the standard big data network signal are existed, which will cause the demodulation result obtained after the demodulator is demodulated to be wrong, therefore, the accuracy of analysis and judgment of the big data control terminal is greatly reduced.
Disclosure of Invention
In view of the above situation, and in order to overcome the defects of the prior art, an object of the present invention is to provide an anti-interference system for big data network transmission, which can detect the adjacent channel interference state of a big data network signal digitally modulated by 2PSK, determine the degree of waveform distortion of the big data network signal, and send +3.3V to a big data control terminal for early warning when the waveform of the big data network signal is seriously distorted, so as to find out and manage the information source of the adjacent channel interference signal in time, thereby improving the accuracy of analysis and determination of the big data control terminal.
The technical scheme includes that the system comprises a big data network signal receiver, a big data pre-filter, a 2PSK interference detection module, a big data demodulator and a big data control terminal, wherein the big data network signal receiver transmits a received big data network signal to the big data pre-filter, the big data pre-filter performs frequency selection filtering on the big data network signal, amplifies the signal and then transmits the amplified signal to the big data demodulator for demodulation, so that original data are obtained and sent to the big data control terminal, and the 2PSK interference detection module comprises a phase shift addition circuit, a period conversion circuit, a period comparison circuit and an interference judgment circuit;
the phase shift addition circuit samples a big data network signal output by the big data prefilter, adjusts the resistance value of a rheostat R1 by utilizing the principle that the current of a capacitor C1 leads the terminal voltage, shifts the phase of the big data network signal by 180 degrees in advance, adds the original big data network signal and the big data network signal shifted by 180 degrees in advance by utilizing an operational amplifier AR2, outputs an obtained sum value signal through an operational amplifier AR2, utilizes a single continuous negative voltage of the sum value signal to conduct a triode Q6, charges a capacitor C2, utilizes the conduction state of a relay K4 to output the voltage on the capacitor C2, utilizes a single continuous positive voltage of the sum value signal to conduct the triode Q7, rapidly discharges the capacitor C2, simultaneously, utilizes the operational amplifier AR3 to invert the phase of the sum value signal, utilizes the single continuous positive voltage of the original sum value signal to conduct a triode Q2, charges the capacitor C3, the voltage on the capacitor C3 is output by using the conducting state of the relay K2, the triode Q3 is conducted by using the single continuous negative voltage of the original sum value signal, the capacitor C3 discharges rapidly, the period comparison circuit uses the operational amplifier AR4 to perform a differential operation on the voltage on the capacitor C2 or the voltage on the capacitor C3 and the divided voltage values of the resistors R18-R19, and outputs the obtained difference signal, the interference decision circuit compares the difference signal with the voltage division value of the resistors R24-R25 by using the operational amplifier AR5, compares the difference signal with the voltage division value of the resistors R27-R28 by using the operational amplifier AR6, when the operational amplifier AR5 and the operational amplifier AR6 both output positive voltage, the relay K7 outputs +3V, the thyristor Q12 outputs +3.3V to the big data control terminal, when the operational amplifier AR5 and the operational amplifier AR6 both output negative voltage, the relay K8 outputs +3V, and the thyristor Q12 outputs +3.3V to a big data control terminal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages:
1. when the influence of adjacent frequency interference is large, the situation that the time length of a single continuous positive voltage and the time length of a single continuous negative voltage of a large data network signal digitally modulated by 2PSK have large difference with the half period of a standard large data network signal exists, particularly at the position where the phase is reversed, but because the waveform of the large data network signal has two adjacent positive half cycles or two adjacent negative half cycles at the position where the phase is reversed, the time length of the single continuous positive voltage or the time length of the single continuous negative voltage of the large data network signal is not easy to directly detect, the large data network signal output by a large data prefilter and the large data network signal obtained by shifting the phase by 180 degrees ahead of the large data network signal are subjected to addition operation, and the single continuous positive voltage and the single continuous negative voltage in the obtained sum signal are alternated at intervals;
the triode Q6 is conducted by using a single continuous negative voltage in the sum signal, so that the power supply +6V charges the capacitor C2 and outputs the capacitor C2 in a zero level time period of the sum signal, and the triode Q7 is conducted by using a single continuous positive voltage in the sum signal, so that the capacitor C2 discharges rapidly; transistor Q1 is turned on with a single continuous positive voltage in the sum signal, thereby turning on transistor Q2, causing +6V to charge capacitor C3, during the zero level time period of the sum signal, a single continuous negative voltage in the sum signal turns on transistor Q3, causing capacitor C3 to discharge rapidly, thereby converting the single continuous positive voltage duration and the single continuous negative voltage duration in the sum signal into the charging voltages on the capacitor C3 and the capacitor C2 respectively, and the differential operation is carried out with the divided voltage value of the resistors R18-R19 converted from the half period of the standard big data network signal, so as to detect the adjacent channel interference state of the big data network signal and the waveform distortion degree, and send +3.3V to the big data control terminal for early warning when the big data network signal waveform is seriously distorted, therefore, the information source of the adjacent channel interference signal can be checked and managed in time, and the accuracy of analysis and judgment of the big data control terminal is improved.
2. The charging voltage of the capacitor C2 is determined by parameters of a resistor R15 and a capacitor C2, the charging voltage of the capacitor C3 is determined by parameters of a resistor R13 and a capacitor C3, the resistance values of a resistor R15 and a resistor R13 are equal, the parameters of the capacitor C2 are the same as the parameters of a capacitor C3, and the diode D1 is used for counteracting the tube voltage drop of the triode Q1, so that the state that the triode Q6 controls the power supply +6V to charge the capacitor C2 is symmetrical to the state that the triode Q2 controls the power supply +6V to charge the capacitor C3, the sum signal level duration is converted into the standard of the charging voltage of the capacitor uniformly, and the error of the comparison of a later-stage periodic comparison circuit is reduced.
Drawings
FIG. 1 is a schematic diagram of a phase shifting adder circuit of the present invention;
FIG. 2 is a schematic diagram of the cycle switching circuit of the present invention;
FIG. 3 is a schematic diagram of a cycle comparison circuit of the present invention;
fig. 4 is a schematic diagram of an interference decision circuit of the present invention.
Detailed Description
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings of fig. 1 to 4. The structural contents mentioned in the following embodiments are all referred to the attached drawings of the specification.
An anti-interference system for big data network transmission comprises a big data network signal receiver, a big data pre-filter, a 2PSK interference detection module, a big data demodulator and a big data control terminal, wherein the 2PSK interference detection module comprises a phase-shifting addition circuit, a period conversion circuit, a period comparison circuit and an interference judgment circuit; the big data network signal receiver receives a large number of signals, the big data pre-filter performs band-pass filtering on the received large number of signals, corresponding big data network signals are selected and amplified and then transmitted to the big data demodulator, the big data demodulator demodulates the big data network signals and outputs original data to the big data control terminal for data analysis, the 2PSK interference detection module samples the big data network signals output by the big data pre-filter, the state that the big data network signals modulated by 2PSK digital are interfered by adjacent frequencies is detected, the degree of waveform distortion of the big data network signals is judged, and +3.3V is sent to the big data control terminal for early warning when the waveform of the big data network signals is seriously distorted, so that information sources of the adjacent frequency interference signals are timely searched and managed.
The invention is only suitable for communication systems which adopt 2PSK digital modulation mode modulation.
The phase shift addition circuit samples a big data network signal output by the big data prefilter, a phase shift circuit is formed by applying a capacitor C1, a rheostat R1, an operational amplifier AR1 and resistors R2-R3, the terminal voltage of the rheostat R1 is taken as output by utilizing the principle that the current of the capacitor C1 is ahead of the terminal voltage and the current phase of the rheostat R1 are the same, the resistance value of the rheostat R1 is adjusted, the big data network signal is shifted by 180 degrees in advance, the proportionality coefficient of the operational amplifier AR1 is determined by the resistance values of the resistor R3 and the resistor R2 and is 1, and the big data network signal shifted by 180 degrees in advance is output by the operational amplifier AR 1;
an adder circuit is formed by an operational amplifier AR2 and resistors R4-R7, the original big data network signal and the big data network signal which is advanced and shifted by 180 degrees are added, the proportionality coefficient of the operational amplifier AR2 is determined by the resistance values of R7 and a resistor R6, the proportionality coefficient is 1, and a sum signal obtained by adding operation is output through an operational amplifier AR 2; the resistor R8 and the resistor R9 form a voltage division circuit, so that the sum value signal output by the resistor R8 has certain attenuation to inhibit interference clutter signals with small amplitude included in the sum value signal and prevent the interference clutter signals from falsely triggering a triode in the period conversion circuit.
When the period conversion circuit inputs a single continuous negative voltage of the sum signal, the triode Q7 is cut off, the diode D1 is conducted, the triode Q6 is conducted along with the single continuous negative voltage, the power supply +6V starts to charge the capacitor C2, the triode Q13 is conducted, the triode Q14 is cut off, the relay K5 is conducted, the contact 1 of the relay K is connected with the contact 3, the power supply +5V is grounded through the resistor R16, and therefore the relay K4 is cut off to prevent the voltage on the capacitor C2 from being output when the charging is not finished; meanwhile, the triode Q1 is cut off, the relay K1 is cut off, and the sum signal cannot charge the capacitor C3; when the single continuous negative voltage of the sum signal is over, the sum signal starts to output a zero level, in the time period, the diode D1 and the triode Q6-Q7 are all cut off, the charging to the capacitor C2 is stopped, the triodes Q13-Q14 are all cut off, and the relay K5 is also cut off, so that the power supply +5V is output to the contact 1 of the relay K4 through the contact 1 of the relay K5, the relay K4 is switched on, the voltage on the capacitor C2 is output to the contact 6 of the relay K6 of the period comparison circuit through the contact 3 of the relay K4 and the contact 4;
when the zero level is finished and the sum signal outputs a single continuous positive voltage, the diode D1 is cut off, the triode Q6 is cut off, the capacitor C2 is stopped being charged, the triode Q13 is cut off, the triode Q14 is conducted, the relay K5 is conducted, and the relay K4 is cut off along with the cut-off, so that the voltage output on the capacitor C2 is prevented, the triode Q7 is conducted, and the capacitor C2 is rapidly discharged; meanwhile, the triode Q1 is switched on, the relay K1 is switched on accordingly, the operational amplifier AR3 and the resistors R10-R12 form an inverter circuit, the positive level of the sum signal is converted into the negative level to be output, the triode Q2 is switched on, the +6V power supply starts to charge the capacitor C3, the triode Q3 and the triode Q5 are both cut off, the triode Q4 is switched on, the relay K3 is switched on, the contact 1 of the relay K is connected with the contact 3, and the +5V power supply is grounded through the resistor R14, so that the relay K2 is cut off to prevent the voltage on the capacitor C3 from being output when the charging is not finished; when the single continuous positive voltage of the sum signal is over, the sum signal also starts to output a section of zero level, in the time period, the triode Q1 and the triode Q3 are both cut off, the relay K1 is cut off, the triode Q2 is cut off, the capacitor C3 is stopped being charged, the triodes Q4-Q5 are all cut off, the relay K3 is cut off, the power supply +5V is transmitted to the contact 3 of the relay K2 through the contact 1 of the power supply +5V, the relay K2 is then turned on, and the voltage on the capacitor C3 is output to the contact 6 of the relay K6 of the period comparison circuit through the contact 1 of the relay K2 and the contact 2;
until the next single continuous negative voltage of the sum signal, the triode Q1 is cut off, the relay K1 is cut off, the triode Q2 is cut off, the capacitor C3 cannot be charged, the triode Q4 is cut off, the triode Q5 is turned on, the relay K3 is turned on, and the relay K2 is cut off accordingly, so that the voltage output on the capacitor C3 is prevented, the triode Q3 is turned on, and the capacitor C3 is rapidly discharged; meanwhile, the capacitor C2 starts to charge again, the process is repeated, and the cycle is repeated; conducting a triode Q6 by each continuous negative voltage of the sum signal, charging a capacitor C2 by using a power supply +6V, and outputting a voltage on a capacitor C2 at the end of the negative level so as to convert the single continuous negative voltage duration of the sum signal into the voltage on a capacitor C2 in real time, similarly, conducting a triode Q1 by each continuous positive voltage of the sum signal, conducting a triode Q2 after the phase inversion of a reverse circuit, charging a capacitor C3 by using the power supply +6V, and outputting a voltage on a capacitor C3 at the end of the positive level so as to convert the single continuous positive voltage duration of the sum signal into the voltage on a capacitor C3 in real time;
the resistor R14 and the resistor R16 are current-limiting resistors; the charging voltage of the capacitor C2 is determined by parameters of a resistor R15 and a capacitor C2, the charging voltage of the capacitor C3 is determined by parameters of a resistor R13 and a capacitor C3, the resistance values of a resistor R15 and a resistor R13 are equal, the parameters of the capacitor C2 are the same as the parameters of a capacitor C3, and the diode D1 is used for counteracting the tube voltage drop of the triode Q1, so that the state that the triode Q6 controls the power supply +6V to charge the capacitor C2 is symmetrical to the state that the triode Q2 controls the power supply +6V to charge the capacitor C3, the sum signal level duration is converted into the standard of the charging voltage of the capacitor uniformly, and the error of the comparison of a later-stage periodic comparison circuit is reduced.
When the voltage on the capacitor C2 is input into the period comparison circuit, the triode Q8 is conducted, the relay K6 is conducted, the contact 1 is conducted with the contact 3, the contact 4 is conducted with the contact 6, the operational amplifier AR4 and the resistors R20-R23 are used for forming a differential proportional circuit, the proportional coefficient of the operational amplifier AR4 is determined by the ratio of the resistor R23 to the resistor R22, the differential proportional circuit conducts differential operation on the voltage on the capacitor C2 and the divided voltage values of the resistors R18-R19, the divided voltage values of the resistors R18-R19 are set according to the voltage converted by the same parameters of the period conversion circuit in the half period of the standard big data network signal, the obtained difference signal is output by the operational amplifier AR4, and the difference signal at the moment represents the difference between the continuous negative voltage duration of the sum signal and the half period of the standard big data network signal;
when the voltage on the capacitor C3 is input into the period comparison circuit, the triode Q8 is conducted, the relay K6 is conducted, the contact 1 is connected with the contact 3, the contact 4 is connected with the contact 6, the voltage on the capacitor C2 and the divided voltage value of the resistors R18-R19 are subjected to differential operation by using a differential proportion circuit, an obtained difference signal is output through an operational amplifier AR4, and the difference signal at the moment represents the difference between the single continuous positive voltage duration of the sum signal and the half period of the standard big data network signal; resistor R17 is a current limiting resistor.
When the period comparison circuit has input, the triode Q8 is conducted, a relay K9 in the interference judgment circuit is conducted, a contact 1 of the relay K8 is conducted, a relay K10 is conducted, a contact 3 of the relay K10 is conducted, a contact 4 of the relay K9 is conducted, the difference signal is compared with the voltage division values of the resistors R24-R25 through the operational amplifier AR5, the difference signal is compared with the voltage division values of the resistors R27-R28 through the operational amplifier AR6, wherein the voltage division values of the resistors R24-R25 are set according to the tube voltage drop of the triode Q1, so that comparison errors are reduced; the voltage division value of the resistors R27-R28 is set according to the voltage drop of the negative triode Q1, so that the comparison error is reduced;
if the difference signal is greater than the divided voltage values of the resistors R24-R25, the difference signal is also greater than the divided voltage values of the resistors R27-R28, which indicates that the time length of a single continuous positive voltage and the time length of a single continuous negative voltage of the big data network signal output by the big data prefilter have a condition that the difference between the half cycle of the standard big data network signal is larger, at this time, the operational amplifier AR5 and the operational amplifier AR6 both output positive levels, the diode D2 is conducted, the diode D3 is also conducted, and the resistance value of the current limiting resistor R26 is smaller than that of the current limiting resistor R29, so the triode Q9 can be conducted, the relay K7 is conducted accordingly, the power supply +3V is connected with the contact 2 through the contact 1 of the relay K7 and is loaded on the control electrode of the Q12, the thyristor Q12 is conducted, and the power supply +3.3V is output to the big data control terminal through the thyristor Q12 for early warning, so as to find out the information source of the adjacent frequency interference signal and manage in time, therefore, the accuracy of analysis and judgment of the big data control terminal is improved;
if the difference signal is smaller than the divided voltage values of the resistors R27-R28, the difference signal must also be smaller than the divided voltage values of the resistors R24-R25, which indicates that the time duration of a single continuous positive voltage and the time duration of a single continuous negative voltage of the big data network signal output by the big data prefilter have a larger difference with the half cycle of the standard big data network signal, at this time, the operational amplifier AR5 and the operational amplifier AR6 both output negative levels, the diode D4 is conducted, the diode D5 is also conducted, the triode Q11 is conducted, the triode Q10 is conducted, the relay K8 is conducted accordingly, the power supply +3V is connected with the contact 4 through the contact 3 of the relay K8 and is loaded on the control electrode of the thyristor Q12, the controlled silicon Q12 is switched on, the power supply with +3.3V is output to the big data control terminal through the controlled silicon Q12 for early warning, therefore, the information source of the adjacent channel interference signal can be checked and managed in time, and the accuracy of analysis and judgment of the big data control terminal is improved.
The specific structure of the phase shift adder circuit comprises that one end of a capacitor C1 is connected with one end of a resistor R2 and one end of a resistor R5 and an output port of a big data prefilter, the other end of a capacitor C1 is connected with one end of a rheostat R1 and a non-inverting input end of an operational amplifier AR1, the other end of a resistor R1 is grounded, the other end of a resistor R2 is connected with an inverting input end of an operational amplifier AR1 and one end of a resistor R3, the other end of a resistor R3 is connected with an output end of an operational amplifier AR1 and one end of a resistor R4, the other end of the resistor R4 is connected with the other end of the resistor R4 and the non-inverting input end of the operational amplifier AR4, the inverting input end of the operational amplifier AR4 is connected with one end of the resistor R4 and one end of the resistor R4, the other end of the resistor R4 is connected with one end of a triode Q4, a triode Q4, a Q4 and a Q4 in a period conversion circuit, One end of the triode Q7, the triode Q13 and the triode Q14, the cathode of the diode D1, the contact 3 of the relay K1 and the other end of the resistor R9 are grounded.
The specific structure of the cycle conversion circuit comprises a triode Q1, a triode Q3, a triode Q4, a triode Q5, a triode Q7, a triode Q13, one end of a triode Q14, the cathode of a diode D1, a contact 3 of a relay K1, one end of a resistor R9 and the other end of a resistor R8 in the phase shifting addition circuit, the emitter of a triode Q1 is grounded, the collector of the triode Q1 is connected with a contact 8 of a relay K1, the contact 7 of the relay K1 is connected with a power supply +6V, a contact 5 of the relay K1 is grounded with a contact 6 of the relay K1, a contact 2 of the relay K1 is grounded with the emitter of the triode Q1 and one end of a capacitor C1, the other end of the capacitor C1 is connected with the collector of the triode Q1, one end of the resistor R1 and the contact 3 of the relay K1, the other end of the resistor R1 is connected with the collector of the triode Q1, the emitter of the triode Q1 is connected with the power supply +6V, the base of the diode Q1 and the anode of the Q1, contact 1 of relay K4 is connected with contact 2 of relay K5, contact 1 of relay K5 is connected with power supply +5V, contact 5 of relay K5 is grounded and one end of resistor R16, the other end of resistor R16 is connected with contact 3 of relay K5, contact 4 of relay K5 is connected with transistor Q13 and the collector of transistor Q14, the emitter of transistor Q13 is connected with power supply +5V, the collector of transistor Q14 is connected with power supply +5V, contact 2 of relay K4 is grounded, contact 4 of relay K4 is connected with contact 2 of relay K4 and one end of resistor R4 in the period comparison circuit, contact 6 of relay K4, contact 1 of relay K4 is connected with one end of resistor R4, one end of resistor R4 and the inverting input end of operational amplifier 4, contact 4 of relay K4 is connected with one end of resistor R4, the other end of resistor R4 is connected with the non-inverting input end of operational amplifier R4, the base of resistor R4 and the inverting input end of operational amplifier R4 are connected with the triode Q4, the emitter of the triode Q2 is connected with a power supply +6V, the collector of the triode Q2 is connected with one end of a resistor R13, the other end of the resistor R13 is connected with one end of a capacitor C3, the emitter of the triode Q3 and the contact 1 of a relay K2, the other end of the capacitor C3 is grounded and the collector of the triode Q3, the contact 4 of a relay K2 is grounded, the contact 3 of the relay K2 is connected with the contact 2 of a relay K3, the contact 3 of the relay K3 is connected with one end of a resistor R14, the other end of the resistor R14 is grounded and the contact 5 of the relay K3, the contact 1 of the relay K3 is connected with the power supply +5V, the contact 4 of the relay K3 is connected with the emitter of the triode Q4 and the collector of the triode Q5, the collector of the triode Q4 is connected with the collector of the transistor Q5 and the emitter of the transistor Q5 is connected with the power supply + 5V.
The specific structure of the period comparison circuit comprises that one end of a resistor R17 and a contact 6 of a relay K6 are connected with a contact 4 of a relay K4 of the period conversion circuit and a contact 2 of a relay K2, the other end of the R17 is connected with a base electrode of a triode Q8, an emitter of a triode Q8 is grounded, a collector of a triode Q8 is connected with a contact 8 of a relay K6 and a contact 4 of a relay K9 of the interference decision circuit and a contact 1 of a relay K10, a contact 7 of the relay K6 is connected with a power supply +5V, a contact 5 of a relay K6 is grounded, a contact 2 of a relay K6 is grounded, a contact 3 of a relay K6 is connected with one end of a resistor R18 and a resistor R19, the other end of the resistor R19 is grounded, the other end of the resistor R18 is connected with the power supply +6V, a contact 1 of a relay K6 is connected with one end of a resistor R22, the other end of the resistor R22 is connected with one end of a resistor R22 and an anti-phase amplifier AR 22, and an in-phase of the same phase of an operational amplifier AR 22, One end of the resistor R21 and the other end of the resistor R20 are connected with the contact 4 of the relay K6, the other end of the resistor R21 is grounded, and the other end of the resistor R23 is connected with the output end of the amplifier AR4, the non-inverting input end of the amplifier AR6 in the interference judging circuit and the non-inverting input end of the amplifier AR 5.
The specific structure of the interference judging circuit is that the non-inverting input end of the operational amplifier AR6 is connected with the non-inverting input end of the operational amplifier AR5 and the other end of a resistor R23, the output end of the operational amplifier AR4, the inverting input end of the operational amplifier AR6 is connected with a contact 3 of a relay K10, a contact 1 of a relay K10 is connected with a contact 4 of a relay K9 and the collector of a triode Q8 in the period comparing circuit, a contact 8 of a relay K6, a contact 2 of a relay K10 is connected with a power supply +5V, a contact 4 of a relay K10 is connected with a resistor R27 and one end of a resistor R28, the other end of a resistor R27 is connected with a power supply-6V, the other end of a resistor R28 is grounded and the contact 5 of a relay K10, the output end of the operational amplifier AR6 is connected with one end of a resistor R29, the other end of a resistor R29 is connected with the anode of a diode D3 and the cathode of a diode D5, the cathode of a relay K5 is connected with the contact 3 of a triode Q5, the emitter of the triode Q10 is connected with a power supply +5V, the collector of the triode Q10 is connected with the emitter of the triode Q11, the contact 1 of the relay K7 is connected with the power supply +3V, the contact 2 of the relay K7 is connected with the contact 4 of the relay K8 and the control electrode of the thyristor Q12, the collector of the triode Q11 is connected with the contact 1 of the relay K8, the contact 2 of the relay K8 is grounded, the contact 3 of the relay K8 is connected with the power supply +3V, the base of the triode Q11 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D2 and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the operational amplifier AR5, the inverting input end of the operational amplifier AR5 is connected with the contact 1 of the relay K5, the contact 2 of the relay K5 is grounded, the contact 5V of the relay K5, the contact 5 of the relay K5 is connected with the power supply +5V, the contact 3 of the relay K5 is connected with the contact 3, the contact 3 of the resistor R5 is connected with the power supply +3, the anode of the controlled silicon Q12 is connected with the +3.3V power supply, and the cathode of the controlled silicon Q12 is connected with the input port of the big data control terminal.
When the phase-shifting adder circuit is used specifically, a phase-shifting circuit is used for sampling a big data network signal output by a big data prefilter, the phase-shifting circuit is formed by using a capacitor C1, a rheostat R1, an operational amplifier AR1 and resistors R2-R3, the resistance value of the rheostat R1 is adjusted by using the principle that the current of the capacitor C1 leads the terminal voltage, the big data network signal is advanced and phase-shifted by 180 degrees, the operational amplifier AR2 and the resistors R4-R7 form an adder circuit, the original big data network signal and the big data network signal advanced and phase-shifted by 180 degrees are subjected to addition operation, the obtained sum value signal is output by the operational amplifier AR2, and the resistors R8 and R9 form a voltage division circuit, so that the sum value signal output by the resistor R8 has certain attenuation; the period conversion circuit utilizes a single continuous negative voltage of the sum signal to conduct the diode D1, so that the triode Q6 is conducted, the power supply +6V charges the capacitor C2, and the voltage on the capacitor C2 is output by utilizing the conducting state of the relay K4; the triode Q7 is conducted by using a single continuous positive voltage of the sum signal, the capacitor C2 discharges rapidly, meanwhile, the triode Q1 is conducted, the relay K1 is conducted therewith, the contact 1 is conducted with the contact 3, the contact 4 is conducted with the contact 6, the operational amplifier AR3 and the resistors R10-R12 are used for forming an inverter circuit, the sum signal is inverted, the triode Q2 is conducted by using the single continuous positive voltage of the original sum signal, the capacitor C3 is charged, and the voltage on the capacitor C3 is output by using the conducting state of the relay K2; the triode Q3 is conducted by using the next continuous negative voltage of the original sum signal, and the capacitor C3 discharges rapidly;
when the voltage on the capacitor C2 is input into the period comparison circuit, the triode Q8 is conducted, the relay K6 is conducted, the contact 1 is connected with the contact 3, the contact 4 is connected with the contact 6, the operational amplifier AR4 and the resistors R20-R23 are used for forming a differential proportion circuit, the differential proportion circuit carries out differential operation on the voltage on the capacitor C2 and the divided voltage value of the resistors R18-R19, and the obtained difference signal is output through the operational amplifier AR 4; when the voltage on the capacitor C3 is input into the period comparison circuit, the triode Q8 is conducted, the relay K6 is conducted, the contact 1 is connected with the contact 3, the contact 4 is connected with the contact 6, the voltage on the capacitor C2 and the divided voltage value of the resistors R18-R19 are subjected to differential operation by using a differential proportion circuit, and an obtained difference signal is output through an operational amplifier AR 4; when the period comparison circuit has input, the relay K9 in the interference judgment circuit is conducted, the contact 1 is conducted, the contact 3 is conducted, the relay K10 is also conducted, the contact 3 is conducted, the operational amplifier AR5 is used for comparing the difference signal with the voltage division value of the resistors R24-R25, the operational amplifier AR6 is used for comparing the difference signal with the voltage division value of the resistors R27-R28, if the difference signal is greater than the voltage division value of the resistors R24-R25, the difference signal is certainly greater than the voltage division value of the resistors R27-R28, the operational amplifier AR5 and the operational amplifier AR6 both output positive levels, the diode D2 is conducted, the diode D3 is conducted, the resistance value of the current limiting resistor R26 is smaller than that of the current limiting resistor R29, the triode Q9 can be conducted, the relay K7 is conducted, the power supply +3V is conducted through the contact 1 of the relay K7 and is conducted 2 to be loaded on the control electrode of the thyristor Q12, the controlled silicon Q12 is switched on, and the power supply +3.3V is output to the big data control terminal through the controlled silicon Q12 for early warning; if the difference signal is smaller than the voltage division value of the resistors R27-R28, the difference signal is also smaller than the voltage division value of the resistors R24-R25, the operational amplifier AR5 and the operational amplifier AR6 both output negative levels, the diode D4 is conducted, the diode D5 is also conducted, the triode Q11 is conducted, the triode Q10 is conducted, the relay K8 is conducted accordingly, the power supply +3V is connected with the contact 4 through the contact 3 of the relay K8 and loaded on the control electrode of the silicon controlled rectifier Q12, the silicon controlled rectifier Q12 is conducted, and the power supply +3.3V is output to the big data control terminal through the silicon controlled rectifier Q12 to perform early warning.
While the invention has been described in further detail with reference to specific embodiments thereof, it is not intended that the invention be limited to the specific embodiments thereof; for those skilled in the art to which the present invention pertains and related technologies, the extension, operation method and data replacement should fall within the protection scope of the present invention based on the technical solution of the present invention.
Claims (5)
1. An anti-interference system for big data network transmission comprises a big data network signal receiver, a big data pre-filter, a 2PSK interference detection module, a big data demodulator and a big data control terminal, and is characterized in that the big data network signal receiver transmits a received big data network signal to the big data pre-filter, the big data pre-filter performs frequency selection filtering on the big data network signal, amplifies the signal and then transmits the amplified signal to the big data demodulator for demodulation, and original data are obtained and sent to the big data control terminal, wherein the 2PSK interference detection module comprises a phase shift addition circuit, a period conversion circuit, a period comparison circuit and an interference judgment circuit;
the phase shift addition circuit samples a big data network signal output by the big data prefilter, adjusts the resistance value of a rheostat R1 by utilizing the principle that the current of a capacitor C1 leads the terminal voltage, shifts the phase of the big data network signal by 180 degrees in advance, adds the original big data network signal and the big data network signal shifted by 180 degrees in advance by utilizing an operational amplifier AR2, outputs an obtained sum value signal through an operational amplifier AR2, utilizes a single continuous negative voltage of the sum value signal to conduct a triode Q6, charges a capacitor C2, utilizes the conduction state of a relay K4 to output the voltage on the capacitor C2, utilizes a single continuous positive voltage of the sum value signal to conduct the triode Q7, rapidly discharges the capacitor C2, simultaneously, utilizes the operational amplifier AR3 to invert the phase of the sum value signal, utilizes the single continuous positive voltage of the original sum value signal to conduct a triode Q2, charges the capacitor C3, the voltage on the capacitor C3 is output by using the conducting state of the relay K2, the triode Q3 is conducted by using the single continuous negative voltage of the original sum value signal, the capacitor C3 discharges rapidly, the period comparison circuit uses the operational amplifier AR4 to perform a differential operation on the voltage on the capacitor C2 or the voltage on the capacitor C3 and the divided voltage values of the resistors R18-R19, and outputs the obtained difference signal, the interference decision circuit compares the difference signal with the voltage division value of the resistors R24-R25 by using the operational amplifier AR5, compares the difference signal with the voltage division value of the resistors R27-R28 by using the operational amplifier AR6, when the operational amplifier AR5 and the operational amplifier AR6 both output positive voltage, the relay K7 outputs +3V, the thyristor Q12 outputs +3.3V to the big data control terminal, when the operational amplifier AR5 and the operational amplifier AR6 both output negative voltage, the relay K8 outputs +3V, and the thyristor Q12 outputs +3.3V to a big data control terminal.
2. The big data network transmission anti-interference system according to claim 1, wherein the phase shift adder circuit comprises a capacitor C1, one end of the capacitor C1 is connected to a resistor R2, one end of a resistor R5 and an output port of the big data pre-filter, the other end of the capacitor C1 is connected to one end of a varistor R1 and a non-inverting input end of an operational amplifier AR1, the other end of a varistor R1 is connected to ground, the other end of a resistor R2 is connected to an inverting input end of an operational amplifier AR1 and one end of a resistor R3, the other end of a resistor R3 is connected to an output end of an operational amplifier AR1 and one end of a resistor R4, the other end of a resistor R4 is connected to the other end of a resistor R5 and a non-inverting input end of an operational amplifier AR2, the inverting input end of the operational amplifier AR2 is connected to one end of a resistor R6 and one end of a resistor R7, the other end of a resistor R6 is connected to ground, the other end of a resistor R7 is connected to an output end of an operational amplifier R7 and one end of a resistor R7 is connected to an output end of the operational amplifier R7, In the cycle conversion circuit, one end of a triode Q1, a triode Q3, a triode Q4, a triode Q5, a triode Q7, a triode Q13, one end of a triode Q14, the cathode of a diode D1, a contact 3 of a relay K1 and the other end of a resistor R9 are grounded.
3. The big data network transmission anti-interference system according to claim 1, wherein the period conversion circuit comprises a transistor Q1, an emitter of the transistor Q1 is grounded, a collector of the transistor Q1 is connected to a contact 8 of a relay K1, a contact 7 of a relay K1 is connected to a power supply +6V, a contact 5 of a relay K1 is grounded and a contact 6 of a relay K1, a contact 2 of a relay K1 is grounded and an emitter of the transistor Q7 and one end of a capacitor C2, the other end of the capacitor C2 is connected to a collector of a transistor Q7, one end of a resistor R15 and a contact 3 of a relay K4, the other end of a resistor R15 is connected to a collector of a transistor Q6, an emitter of a transistor Q6 is connected to a power supply +6V, a base of a transistor Q6 is connected to an anode of a diode D1, a contact 1 of a relay K4 is connected to a contact 2 of a relay K5, a contact 1 of a relay K5 is connected to a power supply +5V, a contact 1 of a relay K5 and a contact 16 are connected to a power supply +5V, the other end of the resistor R16 is connected with a contact 3 of the relay K5, a contact 4 of the relay K5 is connected with a triode Q13 and a collector of a triode Q14, an emitter of the triode Q13 is connected with a power supply +5V, a collector of the triode Q14 is connected with the power supply +5V, a contact 2 of the relay K4 is grounded, a contact 4 of the relay K4 is connected with a contact 2 of the relay K2 and one end of a resistor R17 in the period comparison circuit and a contact 6 of the relay K6, a contact 1 of the relay K1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R1 and an inverting input end of an operational amplifier AR1, a contact 4 of the relay K1 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with an inverting input end of the operational amplifier AR1, the other end of the resistor R1 is connected with an output end of the operational amplifier AR1 and a base of the triode Q1, an emitter of the triode Q1 is connected with a power supply +6V, one end of the resistor Q1, and one end of the collector of the resistor R1 is connected with a capacitor C of the transistor R1, The emitter of the triode Q3 and the contact 1 of the relay K2, the other end of the capacitor C3 is grounded and the collector of the triode Q3, the contact 4 of the relay K2 is grounded, the contact 3 of the relay K2 is connected with the contact 2 of the relay K3, the contact 3 of the relay K3 is connected with one end of the resistor R14, the other end of the resistor R14 is grounded and the contact 5 of the relay K3, the contact 1 of the relay K3 is connected with the power supply +5V, the contact 4 of the relay K3 is connected with the emitter of the triode Q4 and the collector of the triode Q5, the collector of the triode Q4 is connected with +5V, and the emitter of the triode Q5 is connected with the power supply + 5V.
4. The big data network transmission anti-jamming system according to claim 1, wherein the period comparison circuit includes a resistor R17, the other end of the resistor R17 is connected to the base of the transistor Q8, the emitter of the transistor Q8 is grounded, the collector of the transistor Q8 is connected to the contact 8 of the relay K6 and the contact 4 of the relay K9 of the jamming decision circuit, the contact 1 of the relay K10, the contact 7 of the relay K6 is connected to the power supply +5V, the contact 5 of the relay K6 is grounded, the contact 2 of the relay K6 is grounded, the contact 3 of the relay K6 is connected to the resistor R18 and one end of the resistor R19, the other end of the resistor R19 is grounded, the other end of the resistor R18 is connected to the power supply +6V, the contact 1 of the relay K6 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to one end of the resistor R23 and the inverting input end of the operational amplifier AR4, the non-inverting input end of the operational amplifier R4 is connected to the non-inverting input end of the amplifier 20 and one end of the amplifier 21, the other end of the resistor R20 is connected with the contact 4 of the relay K6, the other end of the resistor R21 is grounded, and the other end of the resistor R23 is connected with the output end of the amplifier AR4, the non-inverting input end of the amplifier AR6 in the interference judging circuit and the non-inverting input end of the amplifier AR 5.
5. The big data network transmission anti-jamming system according to claim 1, wherein the jamming decision circuit includes an operational amplifier AR6, an inverting input terminal of the operational amplifier AR6 is connected to the contact 3 of the relay K10, the contact 2 of the relay K10 is connected to the power supply +5V, the contact 4 of the relay K10 is connected to one end of the resistor R27 and the resistor R28, the other end of the resistor R27 is connected to the power supply-6V, the other end of the resistor R28 is connected to the ground and the contact 5 of the relay K10, an output terminal of the operational amplifier AR6 is connected to one end of the resistor R29, the other end of the resistor R29 is connected to an anode of the diode D3 and a cathode of the diode D5, a cathode of the diode D3 is connected to the contact 3 of the relay K7, an anode of the diode D5 is connected to a base of the transistor Q10, an emitter of the transistor Q10 is connected to the power supply +5V, a collector of the transistor Q10 is connected to an emitter of the transistor Q11, and a contact 1 of the relay K7 is connected to the power supply +3V, the contact 2 of the relay K7 is connected with the contact 4 of the relay K8 and the control electrode of the thyristor Q12, the collector of the triode Q11 is connected with the contact 1 of the relay K8, the contact 2 of the relay K8 is grounded, the contact 3 of the relay K8 is connected with the power supply +3V, the base of the triode Q11 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D2 and one end of the resistor R26, the other end of the resistor R26 is connected with the output end of the amplifier AR5, the inverting input end of the amplifier AR5 is connected with the contact 1 of the relay K9, the contact 2 of the relay K9 is grounded, the contact 5 of the relay K2 is connected with the power supply +5V, the contact 3 of the relay K8269556 is connected with the resistor R24 and one end of the resistor R25, the other end of the resistor R24 is grounded, the other end of the resistor R25 is connected with the power supply +6V, the anode of the thyristor Q12 is connected with the power supply +3.3V, and the cathode of the thyristor Q12 is connected with the data control input port.
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| CN116527463A (en) * | 2023-06-26 | 2023-08-01 | 四川新川航空仪器有限责任公司 | Common mode interference signal suppression device and method |
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