CN112397015B - Driving device, display control chip, display device and display control method - Google Patents

Driving device, display control chip, display device and display control method Download PDF

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Publication number
CN112397015B
CN112397015B CN201910749350.0A CN201910749350A CN112397015B CN 112397015 B CN112397015 B CN 112397015B CN 201910749350 A CN201910749350 A CN 201910749350A CN 112397015 B CN112397015 B CN 112397015B
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pulse width
width modulation
constant current
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CN112397015A (en
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费小泂
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Cool Silicon Semiconductor Technology Shanghai Co ltd
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Cool Silicon Semiconductor Technology Shanghai Co ltd
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Priority to CN202111025175.4A priority patent/CN113707078B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/20—Controlling the colour of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/32—Pulse-control circuits
    • H05B45/325—Pulse-width modulation [PWM]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/345—Current stabilisation; Maintaining constant current
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/16—Controlling the light source by timing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Led Devices (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to a driving device, a display control chip, a display device and a display control method. The driving device comprises a plurality of pulse width modulation modules, and each pulse width modulation module forms a corresponding pulse width modulation signal according to the gray scale data matched with one path of matched light emitting diode. The cycle period shared by each pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and the plurality of light emitting diodes are sequentially lightened in a time-sharing mode in the cycle period. Each sub-time segment is distributed with a clock signal, and the number of the clock signals of each sub-time segment is a preset value. And determining the time length of each sub-period according to the clock signal distributed to each sub-period and the number of the clock signals. The frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.

Description

Driving device, display control chip, display device and display control method
Technical Field
The present invention relates to the field of illumination display, and more particularly, to providing a driving apparatus and a display control chip, and a display device and a display control method thereof in an illumination display scene containing a solid-state light emitting diode light source.
Background
In the field of illumination display, the pulse dimming is to change the time width of turning on or off of a diode within a certain period of time and consider the current flowing through the diode during the on-lighting of the light emitting diode to be a fixed value, thereby realizing a luminance change. According to the Grassmann's law and the standard chromaticity diagram of the International luminous Commission on illumination, the reference color component of the pixel point needs to be distributed in a preset intensity range in the illumination and display system, and all colors which can be perceived by the visual system can be basically obtained by depending on the gray scale change of the primary colors and the superposition of different brightness. In the industry, because various core parameters of the light sources of the various primary colors of the light emitting diodes are different, such as working voltage and luminous efficiency, when the primary colors are mixed, the light intensity ratio designed for the light sources of the various primary colors is difficult to achieve in practical application, so that in some occasions, a gamma correction algorithm with a large ratio must be adopted for compensation in software, typically, for example, the brightness range of blue is remarkably smaller than the brightness ranges of red light and green light, which requires more hardware resources to be consumed and more complex circuits to be applied. It is necessary to design a new driving scheme for the primary color light sources, to allow the hardware-limited resolution to flexibly distribute the primary color colors and to freely distribute the power ratios of the primary color light sources.
Disclosure of Invention
The application designs a drive arrangement, drive multichannel emitting diode, includes:
each pulse width modulation module forms a corresponding path of pulse width modulation signal according to the gray scale data matched with one path of light emitting diode matched with the pulse width modulation module, and the multiple paths of light emitting diodes correspond to the multiple paths of pulse width modulation signals;
each path of constant current unit is connected in series with one path of light emitting diode;
whether any path of light emitting diode flows through the constant current provided by the constant current unit connected in series with the light emitting diode is controlled by one path of pulse width modulation signal corresponding to any path of light emitting diode;
the common cycle period of each pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lightened in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals of each sub-time period is a preset value;
determining the time length of each sub-time period according to the clock signals distributed by each sub-time period and the number of the clock signals in a clock counting mode;
the frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
The above-mentioned drive device, wherein:
at least multiple paths of light-emitting diodes with three primary colors of red, green and blue are equipped, the gray data of each path of light-emitting diode is adjusted under the condition of mixing the colors of the three primary colors, and different colors are obtained by the change of the gray data matched with the multiple paths of light-emitting diodes respectively.
The above-mentioned drive device, wherein:
the pulse width modulation modules are provided with a counter, the multi-bit counting data output by the counter comprises appointed high-bit data and appointed low-bit data, and the number of the sub-time periods in each cycle period is determined by the number of the appointed high-bit data;
the time length of each sub-period is counted by a clock signal trigger counter matched with the sub-period, and the preset value related to the number of clock signals in each sub-period is determined by the number of bits of the specified low-bit data.
The above-mentioned drive device, wherein:
setting the digit Z of the appointed high-order data and the digit F of the appointed low-order data to be natural numbers larger than zero;
the number of sub-periods per cycle does not exceed 2ZAnd the preset value in each sub-period is 2F。
The above-mentioned drive device, wherein:
the counter is provided with a data selector, a plurality of clock signals distributed for a plurality of sub-time periods are input to a plurality of data input ends of the data selector, and the appointed high-order data is regarded as a channel selection signal of the data selector;
in each cycle period, the appointed low-bit data triggers the appointed high-bit data carry once after the count is full, and further triggers the data selector to switch and output different clock signals;
the different channel selection signals map different clock signals output by the data selector, thereby distributing one clock signal for each sub-period and triggering the counter to count.
The above-mentioned drive device, wherein:
each pulse width modulation module is provided with a data comparator;
the appointed low-level data is reordered according to a rule that the weight is from low to high to obtain reverse-order data;
in any sub-time period, the gray data and the reverse data matched with one path of light emitting diode paired with the pulse width modulation module are sent to a data comparator for comparison by the corresponding pulse width modulation module:
the pulse width modulation signal has an effective logic value when the reverse order data is lower than the gradation data.
The above-mentioned drive device, wherein:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of the cycle periods, so that the average value of the duty ratio of each pulse width modulation signal in a plurality of the cycle periods is adjusted by the jitter signal;
the effective logic values of one pulse width modulation signal generated by each pulse width modulation module in a corresponding sub-time period are in discrete distribution, and when any pulse width modulation module outputs a jitter signal, the jitter signal is immediately output after the last effective logic value in the pulse width modulation signals generated by the pulse width modulation module is set.
The above-mentioned drive device, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-time period are arranged in a continuous mode; or
The effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a scattered manner.
The above-mentioned drive device, wherein:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of cycle periods, and when any pulse width modulation module outputs the jitter signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, the jitter signals are immediately output after the effective logic values of the pulse width modulation signals generated by any pulse width modulation module are set; or
If the effective logic values of the pulse width modulation signals are distributed in a scattered manner, the jitter signal is output immediately after the end of setting the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module.
The above-mentioned drive device, wherein:
the driving device comprises a shunting module connected with a plurality of paths of light-emitting diodes in parallel and used for stabilizing the input voltage supplied to the driving device;
the LED driving circuit comprises a power input end and a potential reference end, wherein the power input end receives input voltage, each light emitting diode and one constant current unit are coupled between the power input end and the potential reference end in series, and a shunt module is also coupled between the power input end and the potential reference end;
the shunt module comprises an adjustable parallel voltage reference circuit, the cathode of the adjustable parallel voltage reference circuit is coupled to the power input end through a resistor or not, the anode of the adjustable parallel voltage reference circuit is coupled to the potential reference end, and a resistor voltage divider is arranged between the power input end and the potential reference end;
the reference terminal of the adjustable parallel type voltage reference circuit is coupled to a voltage dividing node of the resistor voltage divider.
The above-mentioned drive device, wherein:
the first data transmission module is provided with a decoder and is used for decoding gray data from received communication data;
the driving device intercepts the communication data belonging to the driving device from each frame of communication data by the first data transmission module, and then forwards the rest other received communication data.
The above-mentioned drive device, wherein:
setting a constant current unit in a mode in which the supplied constant current is fixed; or
The programmable constant current unit is set in a mode that the supplied constant current can be adjusted, the driving device comprises a first data transmission module with a decoder, the first data transmission module is used for decoding first current adjusting data from received communication data, and the driving device adjusts the magnitude of the constant current supplied by the constant current unit according to the first current adjusting data.
The above-mentioned drive device, wherein:
the method comprises the following steps that multiple paths of constant current units are arranged, each path of light emitting diode is independently connected with a corresponding path of constant current unit in series in a one-to-one mode, when one path of pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the any path of light emitting diode is lightened, and the path of constant current unit connected with the light emitting diode in series is started; or
And a single and common constant current unit is provided, each path of light emitting diode is connected with the common constant current unit in series, and when one path of pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the common constant current unit is started and any path of light emitting diode is switched to be connected with the common constant current unit in series to be lightened.
The above-mentioned drive device, wherein:
the bypass module is connected with the multiple paths of light-emitting diodes in parallel, the result obtained by executing NOR logic operation on the multiple paths of pulse width modulation signals is regarded as a control signal of the bypass module, and the bypass module is triggered to shunt the total input current of the driving device when the control signal has an effective logic value.
The above-mentioned drive device, wherein:
the load of the bypass module and one path of constant current unit are set to be connected in series;
each path of light emitting diode and each load are respectively provided with a constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the constant current unit connected in series with the light emitting diode is started, and when the control signal has an effective logic value, the constant current unit connected in series with the load is started; or
The multiple paths of light emitting diodes and the load share a common constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the pulse width modulation signal is switched to be connected in series with the common constant current unit, and when the control signal has an effective logic value, the load is switched to be connected in series with the common constant current unit.
The above-mentioned drive device, wherein: the load comprises a light emitting diode or a non-emitting diode or a resistor.
The above-mentioned drive device, wherein:
a current source module with a constant current source is arranged on a line for supplying power to the driving device and is used for maintaining the total input current of the driving device at a preset value;
the constant current source is set in a mode of fixed output current or the programmable constant current source is set in a mode of adjustable output current.
The above-mentioned drive device, wherein:
the second data transmission module configured by the current source module is provided with a decoder and is used for decoding second current regulation data from the communication data received by the current source module;
the current source module adjusts the output current of the programmable constant current source according to the second current adjustment data.
The above-mentioned drive device, wherein:
as the second current regulation data received by the current source module is refreshed, the total input current is updated from a predetermined value corresponding to the second current regulation data before the refresh to a predetermined value corresponding to the second current regulation data after the refresh.
The above-mentioned drive device, wherein:
after the second data transmission module intercepts the communication data belonging to the current source module from each frame of communication data, the current source module forwards the rest of the received communication data.
The above-mentioned drive device, wherein:
the driving device also comprises a first data transmission module with a decoder, the first data transmission module is used for decoding gray data from received communication data and also used for decoding first current regulation data from the communication data, and the driving device regulates the magnitude of constant current provided by the programmable constant current unit according to the first current regulation data;
in each frame of communication data, setting the magnitude of constant current provided by the constant current unit by first current regulation data sent to the driving device, and setting the magnitude of output current of the constant current source by second current regulation data sent to the current source module;
when the first current regulation data and the second current regulation data are set, the current flowing through any path of light-emitting diode is limited not to exceed the output current of the constant current source in the current source module.
The above-mentioned drive device, wherein:
the result of the multi-channel pulse width modulation signal executing the NOR logic operation is regarded as a control signal of a bypass module which is connected with the multi-channel light-emitting diode in parallel, and the bypass module is triggered to be conducted and shunt when the control signal has an effective logic value;
the shunt current when the bypass module shunts is determined by one constant current unit, and the shunt current is limited not to exceed the output current of the constant current source in the current source module when the first and second current regulation data are set.
The application relates to a display control chip, which comprises the driving device.
The application relates to a display control chip, drive multichannel emitting diode includes:
each pulse width modulation module forms a corresponding path of pulse width modulation signal according to the gray scale data matched with one path of light emitting diode matched with the pulse width modulation module, and the multiple paths of light emitting diodes correspond to the multiple paths of pulse width modulation signals;
each path of pulse width modulation signal is used for driving a path of light emitting diode corresponding to the pulse width modulation signal to perform display control;
the common cycle period of each pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lightened in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals of each sub-time period is a preset value;
the time length of each sub-time period is triggered by a clock signal matched with the sub-time period to count by a counter;
the frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
The display device of the driving apparatus described above includes:
each stage of driving device intercepts communication data belonging to each stage of communication data from each frame of communication data through a first data transmission module of each stage of driving device, and transmits the received other rest communication data to a rear stage of driving device which is in cascade connection with the driving device, so that each stage of driving device captures gray data belonging to the stage;
each level of driving device drives the matched multi-path light emitting diodes to carry out display control according to the gray scale data of the level.
The display device of the driving apparatus described above includes:
each driving device further comprises a power input terminal for receiving an input voltage and a potential reference terminal;
any path of light emitting diode in each driving device is coupled between the power input end and the potential reference end in series with a corresponding path of constant current unit, and a shunt module is also coupled between the power input end and the potential reference end.
The display device of the driving apparatus described above includes:
the plurality of driving means are arranged in one or more columns, a power supply input terminal of a first driving means as a column head in each column is coupled to a power supply positive terminal and a potential reference terminal of a last driving means as a column tail is coupled to a power supply negative terminal, and a power supply input terminal of a subsequent driving means in each column is arranged to be coupled to a potential reference terminal of an adjacent previous driving means.
The display device of the driving apparatus described above includes:
each row driving device is connected in series with at least one current source module with a constant current source, and the current source module is used for limiting the total input current flowing from the power supply input end of any one driving device in each row driving device to the potential reference end to a preset value, and setting the constant current source in a mode of fixed output current or setting the programmable constant current source in a mode of adjustable output current.
The display device of the driving apparatus described above includes:
under the condition that the programmable constant current source is arranged, the second data transmission module configured by the current source module is provided with a decoder used for decoding second current regulation data from the received communication data, and the current source module regulates the output current of the constant current source according to the second current regulation data; and
each current source module and the multi-stage driving device are arranged in a cascade connection relationship, so that the current source module with the data forwarding function and the driving device can forward communication data to each other.
The display device of the driving apparatus described above includes:
after the previous frame of communication data transmitted to the current source modules and the driving device is refreshed to the next frame of communication data, the second current adjusting data received by each current source module is refreshed synchronously according to frames;
the total input current of each driving device in each row of driving devices is also determined again by the current source module connected in series in each row of driving devices according to the refreshed second current regulation data.
The display device of the driving apparatus described above includes:
the first data transmission module of the driving device is also used for decoding first current regulation data from the communication data, and the driving device regulates the magnitude value of the constant current provided by the programmable constant current unit according to the first current regulation data;
after the previous frame of communication data transmitted to the current source module and the driving devices is refreshed to the next frame of communication data, the first current regulation data received by each driving device is refreshed synchronously according to the frame, so that the constant current provided by each constant current unit in each driving device is redetermined according to the refreshed first current regulation data.
The display device of the driving apparatus described above includes:
each driving device is provided with a bypass module connected with the multiple paths of light-emitting diodes in parallel, the result obtained by executing NOR logic operation on the multiple paths of pulse width modulation signals corresponding to the multiple paths of light-emitting diodes in each driving device is regarded as a control signal of the bypass module, and the bypass module is triggered to shunt the total input current of the driving device when the control signal has an effective logic value;
the shunt value of the bypass module in each driving device during shunting is determined by the constant current provided by one constant current unit, and after the previous frame of communication data transmitted to the current source module and the driving device is refreshed to the next frame of communication data, the constant current of one constant current unit distributed for the bypass module in each driving device is determined again according to the refreshed first current regulation data.
The display device of the driving apparatus described above includes:
the current source module and the multi-stage driving device transmit communication data in a mode based on a single-wire communication protocol.
The application relates to a display control method for driving multiple paths of light emitting diodes, which comprises the following steps:
any path of light emitting diode and one path of constant current unit are connected in series;
forming a pulse width modulation signal corresponding to each path of light emitting diode by using a pulse width modulation module according to the gray scale data matched to each path of light emitting diode, wherein the plurality of paths of light emitting diodes correspond to the plurality of paths of pulse width modulation signals;
whether each path of light-emitting diode flows through the constant current provided by the constant current unit connected in series with the light-emitting diode is controlled by a path of pulse width modulation signal corresponding to the light-emitting diode;
dividing a common cycle period of each pulse width modulation signal into a plurality of sub-time periods, and arranging an effective logic value of each pulse width modulation signal in a corresponding sub-time period;
distributing a clock signal for each sub-time period and setting the number of the clock signals of each sub-time period as a preset value;
determining the time length of each sub-time period according to the clock signals distributed in each sub-time period and the number of the clock signals in a clock counting mode;
the frequencies of the plurality of clock signals assigned to the plurality of sub-periods of each cycle period are set to be the same or different.
The method described above, wherein:
the bypass module playing a role in shunting and the shunting module playing a role in stabilizing voltage are connected with the multiple paths of light-emitting diodes in parallel;
whether the bypass module is switched on or not is controlled by a control signal, a result obtained by executing NOR logic operation on the multipath pulse width modulation signals is defined as the control signal, and the current of the bypass module under the condition of switching on and shunting is a preset constant current value;
in each cycle period, when the multiple paths of light emitting diodes are not conducted, at least the bypass module and the shunt module carry out shunt together.
The method described above, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-time period are arranged in a continuous mode; or
The effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a scattered manner.
The method described above, wherein:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of cycle periods, and when any pulse width modulation module outputs the jitter signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, the jitter signals are immediately output after the effective logic values of the pulse width modulation signals generated by any pulse width modulation module are set; or
If the effective logic values of the pulse width modulation signals are distributed in a scattered manner, the jitter signal is output immediately after the end of setting the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module.
The method described above, wherein:
triggering a counter to count by a clock signal matched with the time length of any sub-time period to obtain a count value of any sub-time period, and reordering the count values according to a rule that the weight is from low to high to obtain reverse data;
and comparing the reverse data of the count value of any sub-time period with the gray scale data matched with the lighted one path of light emitting diode in any sub-time period, wherein the pulse width modulation signal has an effective logic value when the reverse data is lower than the gray scale data.
The method described above, wherein:
the time length of each sub-period is adjusted in a mode of adjusting the frequency of one clock signal distributed to each sub-period, and then the total time length of the cycle period shared by all paths of pulse width modulation signals is adjusted.
The method described above, wherein:
the plurality of clock signals allocated to the plurality of sub-periods are obtained by dividing an initial clock signal output from one oscillator by a plurality of times, respectively.
The application relates to a driving device for driving a light emitting diode, comprising:
the pulse width modulation module forms a corresponding pulse width modulation signal according to the gray scale data matched with the light emitting diode;
the pulse width modulation signal is used for driving the light emitting diode to carry out display control;
the pulse width modulation module is provided with a counter and a data comparator;
triggering the counter to count by a clock signal and obtaining a count value;
the counting values are reordered according to a rule that the weight is from low to high to obtain reverse data;
the pulse width modulation module sends the gray data and the reverse data into a data comparator for comparison:
the pulse width modulation signal has an effective logic value when the reverse order data is lower than the gradation data.
Drawings
To make the above objects, features and advantages more comprehensible, embodiments accompanied with figures are described in detail below, and features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following figures.
Fig. 1 is a schematic circuit diagram of a driving circuit for driving a light source and integrating a data transmission function.
Fig. 2 is an alternative example of a constant current unit capable of outputting a constant current to a light emitting diode connected in series thereto.
Fig. 3 is another example of a constant current unit capable of outputting a constant current to a light emitting diode connected in series.
Fig. 4 shows that the data transmission module of the driving circuit cooperates with the pulse width modulation module to form a pulse width modulation signal.
Fig. 5 is a waveform diagram of a pwm module forming multiple pwm signals according to gray scale data.
Fig. 6 shows that the cycle period shared by the pulse width modulation signals is divided into sub-periods with adjustable duration.
Fig. 7 is a diagram for adjusting the time length of the sub-period in such a manner that the frequency of the clock signal of the sub-period is adjusted.
Fig. 8 is a diagram in which multiple light emitting diodes driven by a driving circuit are arranged to share the same common constant current unit.
Fig. 9 is a block diagram of a bypass module connected in parallel with multiple leds to form a parallel shunt branch.
FIG. 10 is a bypass module with a light emitting or non-light emitting diode load in parallel with multiple light emitting diodes.
Fig. 11 shows that the light emitting diodes and the bypass modules connected in parallel with them are each separately provided with a constant current unit.
Fig. 12 shows an example of a pwm module used for a distributed pwm signal with valid logic values.
Fig. 13 shows control signals obtained by performing nor operation on pulse width modulation signals of continuous type effective logic values.
Fig. 14 shows control signals obtained by performing nor operation on pulse width modulation signals of distributed effective logic values.
Fig. 15 is an example of a pwm module circuit for generating a pwm signal with distributed effective logic values.
Fig. 16 shows that different gray data results in different dispersion type effective logic values of the pulse width modulation signal.
Fig. 17 is a waveform of a pulse width modulated signal having a continuous type effective logic value added with a dither signal.
Fig. 18 is a waveform of a pulse width modulated signal having a dispersion type effective logic value added with a dither signal.
Fig. 19 is an alternative circuit architecture schematic of a current source module that can provide a constant current source to the driver circuit.
FIG. 20 shows a second data transmission module and a trimming resistor of the current source module to adjust the output current.
Fig. 21 is a circuit diagram of cascaded driver circuits arranged in one or more columns with each column provided with an adjustable current source module.
Detailed Description
The present invention will be described more fully hereinafter with reference to the accompanying examples, which are intended to illustrate and not to limit the invention, but to cover all those embodiments, which may be learned by those skilled in the art without undue experimentation.
Referring to fig. 1, a driving chip IC, which is temporarily in the form of an integrated circuit, is used as a typical example of a driving circuit for driving the light-emitting diode light source to light, but it should be emphasized that this does not mean that the driving circuit can be designed as an integrated circuit because discrete electronic components can also build a driving circuit with the same function. The driver circuit can be designed as an integrated circuit or be built up from discrete electronic components. The data transmission module DAT1 of the driving circuit has the same decoding function as the later mentioned data transmission module DAT2 of the current source module PCS, and they both have a decoder and can decode the input serial data according to a predetermined communication protocol, except that the former needs to decode the grayscale data from the received communication data, and the latter needs to decode the current adjustment data. In fact, whether the current regulation data or the gray scale data are the signals with preset coding rules in the communication data are restored into common binary data by the decoder, and the restored data are slightly different in use and are different in naming. Circuits, such as over-temperature protection, start-up protection, electrostatic protection, transient voltage protection, and peak current leakage circuit, etc., which play a basic protection role, as well as oscillators, power-on reset circuits, and even clock circuits, etc., all belong to necessary or optional parts of the driving chip, and are well known by those skilled in the art, and therefore, they are not described again. The pulse width modulation is essentially to convert the amplitude of a signal into the time of the signal and obtain the pulse width signal, the implementation mechanism of the pulse width modulation mainly comprises main technical routes such as a counting comparison mode, a delay unit mode, a shift mode, a mixed mode of the counting comparison and the delay unit, and the like, and the obtained result in any mode is the pulse width signal with a certain duty ratio. The so-called digital pulse width modulation DPWM technique in the industry is within the scope of the prior art. In the application, the pulse width modulation module of the driving circuit forms a pulse width modulation signal according to the gray scale data, and the gray scale data is used for determining the duty ratio of the pulse width modulation signal, namely the pulse width modulation signal can be regarded as duty ratio information carried by the characterization gray scale data. The driving circuit is a typical example of the driving device.
Referring to fig. 1, four-way leds are illustrated for ease of explanation only, it being understood that the specific number of light sources is not to be construed as limiting in any way and is for reference only. Assuming that the data transmission module DAT1 decodes four sets of gray scale data from the communication data, the first pulse width modulation module PWM1 forms a first pulse width modulation signal corresponding to the first light emitting diode LED1 according to the gray scale data allocated to the first light emitting diode LED1, the second pulse width modulation module PWM2 forms a second pulse width modulation signal corresponding to the second light emitting diode LED2 according to the gray scale data allocated to the second light emitting diode LED2 according to the same principle, the third pulse width modulation module PWM3 forms a third pulse width modulation signal corresponding to the third light emitting diode LED3 according to the gray scale data allocated to the third light emitting diode LED3, and the fourth pulse width modulation module PWM4 forms a fourth pulse width modulation signal corresponding to the fourth light emitting diode LED4 according to the gray scale data allocated to the fourth light emitting diode LED 4. It can thus be seen that: each pulse width modulation module in the driving circuit forms a corresponding path of pulse width modulation signal according to the gray scale data matched with the corresponding path of light emitting diode, and specifically, each pulse width modulation module forms the pulse width modulation signal corresponding to each path of light emitting diode according to the gray scale data distributed to each path of light emitting diode. The four-way light emitting diode comprises a white light type light emitting diode besides a red-green-blue three-primary-color light source, or comprises two green and red-blue light and other alternatives. If the lighting display scene does not need multiple LED light sources but only needs a single light source, the four LEDs can be reduced to only reserve a single LED.
Referring to fig. 1, a first light emitting diode LED1 and a constant current unit CC1 are connected in series, and a constant current unit CC1 generating a constant current is controlled by a first pulse width modulation signal. The first path of pulse width modulation signal determines the constant current lighting time of the first path of light emitting diode in the period of the first path of pulse width modulation signal. A constant current of full amplitude for the light source is applied to the light source in a sequence of repeated pulses that are on or off: when the current is on, for example, the first pwm signal has a high logic level, the constant current is applied to the first LED1, and when the current is off, for example, the first pwm signal has a low logic level, the constant current is disconnected from the first LED 1.
Referring to fig. 1, a second light emitting diode LED2 and a constant current unit CC2 are provided in series, and a constant current unit CC2 generating a constant current is controlled by a second pulse width modulation signal. The second path of pulse width modulation signal determines the constant current lighting time of the second path of light emitting diode in the period of the second path of pulse width modulation signal. The second pwm signal has a high logic level and the constant current is applied to the second LED2, whereas the constant current is disconnected from the second LED2 if the second pwm signal has a low logic level.
Referring to fig. 1, a third light emitting diode LED3 and a constant current unit CC3 are provided in series, and the constant current unit CC3 generating a constant current is controlled by a third pulse width modulation signal, which determines a constant current lighting time of the third light emitting diode in a period of the third pulse width modulation signal. The constant current is output to the third light emitting diode LED3 if the third pulse width modulated signal has a high logic level, and is otherwise disconnected from the third light emitting diode LED3 if the third pulse width modulated signal has a low logic level.
Referring to fig. 1, a fourth light emitting diode LED4 and a constant current unit CC4 are provided in series, and a constant current unit CC4 generating a constant current is controlled by a fourth pulse width modulation signal, which determines a constant current lighting time of the fourth light emitting diode in a period of the fourth pulse width modulation signal. The constant current is applied to the fourth LED4 if the fourth pwm signal has a high logic level, and is disconnected from the fourth LED4 if the fourth pwm signal has a low logic level. In this example, a plurality of constant current cells, such as the constant current cells CC1-CC4, are provided, and each of the light emitting diodes is individually connected in series with a corresponding one of the constant current cells in a one-to-one manner. If an active logic level, for example, a high level, occurs in one pulse width modulation signal, for example, the fourth pulse width modulation signal, corresponding to any one of the light emitting diodes, for example, the LED4, then the any one of the light emitting diodes, for example, the LED4, is lit by a constant current, and one of the constant current units, for example, the CC4, connected in series with the any one of the light emitting diodes, for example, the LED4, is enabled.
Referring to fig. 1, the driving circuit is provided with a shunt module SHU connected in parallel with the plurality of light emitting diodes and configured to shunt the plurality of light emitting diodes. It is noted that, each of the pwm signals is either completely or completely absent with respect to the driving current of the corresponding light source in the cycle period, and it is considered that the constant current of the driving current is loaded to each of the light emitting diodes in a repetitive pulse sequence of on or off, and the current that is turned on or off and jumps causes a large swing of the input and output currents of the driving circuit, and the larger the number of the light emitting diodes driven by the driving circuit, the higher the frequency of the swing of the current and the larger the degree of the swing of the current, the instantaneous current of the solid state light emitting diode light source is a great challenge for the design of the driving circuit. The significance of the shunting module SHU is: when any one of the light emitting diodes is turned on or off to generate a current jump, the shunting module SHU will adaptively adjust the shunting value flowing through itself to maintain the total input current of the driving circuit at a preset value. Taking the constant current unit CC1 as an example, it is either turned on or off under the control of the first pulse width modulation signal, when the constant current unit is turned on, the first light emitting diode LED1 may adaptively decrease its current to compensate the on current of the first light emitting diode LED1, or when the constant current unit is turned off, the first light emitting diode LED1 may adaptively increase its current to compensate the decrease of the current of the first light emitting diode LED 1. Similarly, the current of the other light emitting diodes that are turned on or off and jump is also compensated by the shunt module SHU. Even if the total current of the plurality of paths of light emitting diodes is not changed in the event of current jump, the shunt value of the shunt module can be kept unchanged, for example, the current reduced by turning off one path of light emitting diodes is just compensated by another path of light emitting diodes synchronously turned on, and the purpose of the compensation mechanism is to clamp the total input current of the driving circuit to a predetermined value or within a predetermined range.
Referring to fig. 2, a topology suitable for use in the field of solid state light source display or illumination is a linear converter, which is also referred to in the industry as a linear modulator or a series-type regulator. The constant output current generated by the constant current unit CC1 is the driving current ID1 supplied to the light source load: the transistor MQ forms an equivalent adjustable electrical resistance connecting the power supply and the light source and operates in a linear state or in a non-switching state. A light emitting diode light source, a transistor MQ and a sampling resistor RS1 are connected in series between a power supply input end and a potential reference end in a driving circuit, driving current flowing through the light source also flows through a sampling resistor RS1 connected in series with the light source, sampling voltage and reference voltage VB1 at two ends of the sampling resistor RS1 are respectively input to a negative end and a positive end of an error amplifier EA1 to be amplified and compared, and an output voltage part of the error amplifier EA1 needs to be coupled to a control end of the transistor MQ to drive the transistor to work linearly. The value of the driving current flowing through the sampling resistor is multiplied by the resistance value of the sampling resistor to be equal to the sampling voltage, and the sampling voltage can be indirectly used for representing the magnitude condition of the driving current in fact. The reference voltage VB1 approaches a sampled voltage across the sampling resistor and it essentially indirectly determines the magnitude of the drive current. The reference voltage VB1 allows a stable voltage provided by the bandgap reference BG1 with a higher robustness if the driving circuit is designed as an integrated circuit. The improved constant current unit CC1 uses a current mirror structure to provide the driving current for the light source, and defines a mirror transistor of the transistor MQ in the current mirror structure, the current flowing in the mirror transistor not shown in the figure is either equal to the driving current ID1 or proportional to ID1, the driving circuit is instead a mirror transistor of the light source and the transistor MQ connected in series between the power supply input terminal and the potential reference terminal, and the mirror current provided by the mirror transistor is used as the constant current generated by the constant current unit CC1 to be output to the light source.
Referring to fig. 2, in an alternative example a controlled switch, not shown, is provided between the output of error amplifier EA1 and the control terminal of transistor MQ. For example, the first path of the LED1 and the corresponding first path of the pwm signal are used to control the controlled switch to be turned on or off in the constant current unit CC 1. If the first pulse width modulation signal has an effective logic level, such as a high level, the controlled switch is switched on, and if the first pulse width modulation signal has a non-effective logic level, such as a low level, the controlled switch is switched off. In this embodiment, whether the first light emitting diode LED1 flows through the constant current unit CC1 connected in series or not is controlled by the first pulse width modulation signal corresponding to the first light emitting diode LED 1. Whether the second LED2 flows through the constant current unit CC2 connected in series or not is controlled by the second pwm signal corresponding to the second LED 2. And so on until whether the constant current provided by the constant current unit CC3 connected in series with the third light emitting diode LED3 flows is controlled by the third pulse width modulation signal corresponding to the third light emitting diode LED 3. The constant current cells CC1-CC4 in this alternative example claim that a controlled switch is provided between the error amplifier EA1 output terminal and the control terminal of the transistor MQ of each constant current cell but this is merely an alternative example and not the only solution. Still take the first path of LED1, the constant current unit CC1 corresponding to it, and the first path of pwm signal as examples: assuming that a first terminal of the transistor MQ is coupled to the cathode of the first LED1 and the anode of the first LED1 is connected to the power input terminal, an opposite second terminal of the transistor MQ is connected to the sampling resistor RS 1. In alternative embodiments, the controlled switch may be shifted from the original connection position to be located between the sampling resistor RS1 and the second terminal of the transistor MQ, or alternatively, the controlled switch may be shifted to be located between the first terminal of the transistor MQ and the first LED1, and so on. The controlled switch position moves and causes the circuit to change but still satisfies: whether the constant current provided by the constant current unit CC1 connected in series with the first light emitting diode LED1 flows or not is controlled by the first pulse width modulation signal corresponding to the first light emitting diode LED 1.
Referring to fig. 3, IN an alternative example, a light emitting diode light source LED1, a transistor PQ and a sampling resistor RS2 are connected IN series between a power input terminal IN and a potential reference terminal OUT of the driving circuit, and a driving current flowing through the light source also flows through a sampling resistor RS2 connected IN series with the light source. The sampling voltage and the reference voltage VB2 at the two ends of the sampling resistor RS2 are respectively input to the positive terminal and the negative terminal of an error amplifier EA2 for amplification comparison, and the output voltage part of the error amplifier EA2 is coupled to the control terminal of the transistor PQ to drive the linear operation of the transistor. The constant output current generated by the constant current unit CC1 is the driving current ID2 supplied to the light source load. Comparing the embodiment of fig. 2 with the embodiment of fig. 3, the light emitting diode LED1 is shifted to be connected between the transistor PQ and the sampling resistor RS2 in the driving circuit. Accordingly, the topology of the constant current cell CC1 generating a constant output current is not unique but diverse.
Referring to fig. 4, if the driving circuit has locally stored gray data as a display resource, the driving apparatus does not need the data transmission module DAT1 functioning as a communication at all. On the contrary, the data transmission module DAT1 is indispensable if the driving apparatus is operated in a mode of collecting gray data online.
Referring to fig. 4, allowing the driver circuits and the current source modules PCS to be cascade-connected to each other also allows the driver circuits to be cascade-connected to each other so that they each have a data forwarding function. One of the core functions of the driving circuit is to drive the multiple light emitting diodes matched with the driving circuit to light according to the display requirement, and when the three primary colors are added and mixed, the relative brightness ratio of the red, green and blue primary colors is changed to obtain different colors. When the three primary colors are mixed, the brightness ratio of the light emitting diodes with various colors is changed by changing the lighting time of the light emitting diodes with the colors of red, green and blue in a cycle period, which is equivalent to changing the relative brightness ratio of the three primary colors, so that different colors are obtained when the gray level of the light emitting diodes is changed. In an alternative example, it is assumed that the first to fourth LEDs 1 to 4 are rgb primary LEDs and white LEDs, and the four LEDs are temporarily considered and other light source parts are omitted. The data transmission module DAT1 of the driving circuit arrangement has a decoder which decodes the input serial data according to a predetermined communication protocol and decodes the gray data etc. from the received communication data, the driving circuit adjusting the color of the pixel point according to the respective gray data assigned to the rgb and white leds. The mechanism by which the data transmission module DAT1 receives communication data and forwards data is illustrated in an alternative example as having a data decoder 110 and a data forwarding module 120. The decoder 110 decodes or decodes the data information carried in the communication data, which means that the data in the pre-encoded format that cannot be directly displayed by the light emitting diode can be restored to a conventional binary code that is easy to recognize and execute, the decoded binary code is temporarily stored in the register 130, and the decoded data can be stored in the buffer space or the latch 150 when the data in the register 130 is updated due to the fast data refresh. The decoding process of the communication data can select to detect an ending instruction code or a reset instruction in the data to judge whether the data is transmitted and received. The return-to-zero code is exemplified by indicating a reset command with a long low level of relatively long duration. A long low detection circuit, not shown, RESETs and refreshes the received gray data from the latch 150 to the first to fourth pulse width modulation blocks PWM1-PWM4 if it is monitored that a long low indicating a RESET command RESET occurs. The first to fourth PWM modules respectively generate first to fourth PWM signals and record as DR, DG, DB and DW, and the four PWM signals are used for controlling whether the red, green, blue and white LEDs are lighted or not and controlling the constant current lighting time. And adjusting the gray data of each path of light-emitting diode during the three-primary color mixing, and obtaining different colors by the gray data change of the three-primary color light-emitting diodes.
Referring to fig. 4, the driving circuit performs data regeneration or data forwarding by the data forwarding module 120, and performs a so-called data sending task such as transmitting communication data to the subsequent driving circuit. The simplest forwarding mode of the data forwarding module 120 is transparent transmission, that is, communication data received by the signal input terminal DI is allowed to be directly output from the signal output terminal DO, and then the driving circuit or the current source module PCS connected in cascade are respectively extracted from the single data line according to the address allocation rule to communication data which is consistent with the address of the data forwarding module and belongs to the data forwarding module. The alternative first forwarding path Sel1 needs to be matched with statistics of communication data belonging to each stage of driving circuit, each stage of driving circuit intercepts the communication data belonging to it in each frame of communication data and forwards the rest other received communication data to the next stage of communication data receiver cascaded with it, and the next stage of communication data receiver may be a next stage of driving circuit or a current source module PCS. Each stage of the driving circuit counts whether the total number of bits of the communication data attributed to it is completely received, and as a result of the counting, once the communication data attributed to the driving circuit is decoded and completely received by it, an enable signal ENB is generated, and when the enable signal ENB is active, for example, high level active, the data forwarding module 120 is triggered to forward the communication data received at the signal input DI from the signal output DO, in which case the data forwarding module 120 acts as a switch to allow the received communication data to be output. It can be understood that the functions of the data transmission module DAT2 and the data transmission module DAT1 of the driving circuit described later in data decoding and data forwarding are substantially the same. In order to solve the cascade attenuation effect, the data forwarding module 120 may reconstruct each bit to make its transmission loss modified to restore to the standard transmission code in addition to acting as a switch. The counter 160 can be used to count whether the total number of bits required by the driving circuit is completely received, and the counter 160 will generate an active enable signal ENB after the communication data belonging to the driving circuit is decoded and completely received.
Referring to fig. 4, it can be seen from the above description that the similar second forwarding path Sel2 requires the communication data to be decoded by the decoder 110 of the data transmission module DAT 2. The data forwarding module 120 acts as a switch to decide whether to allow the decoded data to be forwarded under the condition of being controlled by the enable signal ENB, and the forwarded data is the result of forwarding the decoded and re-encoded input data: the encoded data having the predetermined encoding format at the time of forwarding is decoded and recovered again to the data of the predetermined encoding format under the sampling of the clock resource of the data transmission module DAT1 in synchronization. The other scheme for realizing data forwarding is a recoding technology, that is, a third forwarding path Sel3, the recoding technology of the data transmission module DAT1 is realized by the configured encoder 140, the communication data is decoded and temporarily stored in the storage space of the data transmission module DAT1, and then the temporarily stored data is recoded and output by the encoder 140 which can recode the binary data again, and the relay function of decoding and storing the data and recoding and outputting according to the preset coding format ensures that the data can be transmitted smoothly. The second forwarding path Sel2 and the third forwarding path Sel3 described above need to be distinguished: the former uses local clock resources to sample input data and recovers the sampling result into data with a preset coding format, so that each bit data not only restores represented binary data under the sampling condition of the clock resources, but also the sampling result of the clock resources is synchronous and is regarded as reconstruction data needing to be forwarded, and therefore, the data reconstruction process of the former on the input data of each bit is only equivalent to the recoding of the input data; the different idea of the latter is that the input data needs to be actually re-encoded by an additional encoder and following the protocol similar to manchester or return-to-zero code and the symbol period obtained by local decoding, and then the re-encoded input data is output to a communication data receiver such as a subsequent driving circuit or a current source module.
Referring to fig. 4, the first PWM module PWM1 forms the first PWM signal DR corresponding to the first LED1 according to the gray data distributed to the first LED1, i.e., the bits of data denoted as R < M > to R <0 >. The first pulse width modulation signal DR is obtained by comparing the cycle count data provided by the counter CNT with the gray data R < M > to R <0> by using the mode of count comparison. Digital pulse width modulation based on count comparison uses an illustrative comparator CMP1 to compare the gray scale data with the counter data. The first pwm signal DR has a high level period and a low level period in the duty cycle, for example, the first pwm signal DR may instruct the constant current unit CC1 to provide the generated constant current to the first light emitting diode LED1 in the high level period, and conversely, the first pwm signal DR may instruct the constant current unit CC1 to provide the generated constant current to the first light emitting diode LED1 no longer so as to make it unable to conduct in the low level period. The first pulse width modulation signal DR is equivalent to determine the turn-on time and turn-off time of the red light emitting diode in the first pulse width modulation signal DR period. The natural number M used to represent the number of bits of gray scale data is greater than 1, and it is most common to take 8 bits, R <7> to R <0>, for a total of 8 bits to provide 256 levels of gray scale for the red light emitting diode and 65536 levels of gray scale if 16 bits are taken. The number of bits of the gradation data is not limited to 8 or 16, and the specific number of bits is described here for convenience of explanation. The first pulse width modulation signal essentially reflects duty ratio information carried by gray scale data matched with the red light emitting diode. Whether the constant current provided by the constant current unit CC1 connected in series with the red light emitting diode flows through the red light emitting diode is controlled by the corresponding first pwm signal DR, and the constant current lighting time of the red light emitting diode in the period of the first pwm signal DR is determined by the corresponding first pwm signal DR.
Referring to fig. 4, the second PWM2 forms a second PWM signal DG corresponding to the second LED2 according to the gray data distributed to the second LED2, i.e., the bit data denoted as G < M > to G <0 >. The second pulse width modulation signal DG is obtained by comparing the cycle count data and the gray scale data G < M > to G <0> provided by the counter CNT by using the mode of count comparison. Digital pulse width modulation based on count comparison uses an illustrative comparator CMP2 to compare the gray scale data with the counter data. The second pwm signal has a high level period and a low level period in the duty cycle, for example, the second pwm signal DG may indicate the constant current unit CC2 to provide the generated constant current to the second LED2 in the high level period, and conversely, the second pwm signal DG may indicate the constant current unit CC2 not to provide the generated constant current to the second LED2 and make it unable to conduct in the low level period, which is equivalent to that the second pwm signal DG determines the on-time and off-time of the green LED in the second pwm signal DG cycle. If the number of bits of gradation data assigned to the green light emitting diode is 8 bits, i.e., G <7> to G <0> for 8 bits of data, 256 gradations can be provided for the green light emitting diode in total, and 65536 gradations can be provided for the green light emitting diode in 16 bits. The second pulse width modulation signal essentially reflects duty ratio information carried by gray scale data matched with the green light emitting diode. Whether the constant current provided by the constant current unit CC2 connected in series with the green light emitting diode flows through the green light emitting diode is controlled by the corresponding second pulse width modulation signal DG, and the constant current lighting time of the green light emitting diode in the period of the second pulse width modulation signal DG is determined by the second pulse width modulation signal DG corresponding to the green light emitting diode.
Referring to fig. 4, the third PWM3 forms a third PWM signal DB corresponding to the third LED3 according to the gray scale data distributed to the third LED3, i.e., the bit data labeled B < M > to B <0 >. The second pulse width modulation signal DB is obtained by comparing the cycle count data and the gray data B < M > to B <0> provided by the counter CNT by using the mode of count comparison. Digital pulse width modulation based on count comparison uses an illustrative comparator CMP3 to compare the gray scale data with the counter data. The third pwm signal DB may indicate that the constant current unit CC3 provides the generated constant current to the third LED3 during the high level period, and conversely may indicate that the constant current unit CC3 does not provide the generated constant current to the third LED3 and makes the third LED3 non-conductive during the low level period, which is equivalent to the third pwm signal DB determining the on-time and off-time of the blue LED during the period of the third pwm signal DB. If the number of bits of the gradation data assigned to the blue light emitting diode is 8 bits, that is, B <7> to B <0> for 8 bits of data, 256 gradations can be provided for the blue light emitting diode in total, and 65536 gradations can be provided for the blue light emitting diode in 16 bits. The third pulse width modulation signal essentially represents the duty ratio information carried by the gray scale data matched with the blue light emitting diode. Whether the blue light emitting diode flows the constant current provided by the constant current unit CC3 connected in series with the blue light emitting diode is controlled by the third pwm signal DB corresponding thereto, and the constant current lighting time of the blue light emitting diode in the period of the third pwm signal DB is determined by the third pwm signal DB corresponding to the blue light emitting diode.
Referring to fig. 4, the fourth PWM4 generates a fourth PWM signal DW corresponding to the fourth LED4 according to the gray data distributed to the fourth LED4, i.e., the bit data denoted as W < M > to W <0 >. The fourth pulse width modulation signal DW is obtained by comparing the cycle count data supplied from the counter CNT with the gray scale data W < M > to W <0> using the count comparison mode. Digital pulse width modulation based on count comparison uses an illustrative comparator CMP4 to compare the gray scale data with the counter data. The fourth pwm signal DW may instruct the constant current unit CC4 to provide the generated constant current to the fourth LED4 during the high level period, and conversely, the fourth pwm signal DW may instruct the constant current unit CC4 to no longer provide the generated constant current to the fourth LED4 to make it non-conductive during the low level period, which is equivalent to the fourth pwm signal DW determining the on-time and off-time of the white LED within the cycle of the fourth pwm signal DW. If the number of bits of the gray scale data allocated to the white light emitting diode is 8 bits, i.e., W <7> to W <0> for 8 bits in total, 256 gray scales can be provided for the white light emitting diode in total. The fourth pulse width modulation signal essentially represents the duty ratio information carried by the gray scale data matched with the white light emitting diode. Whether the white led passes the constant current supplied from the constant current unit CC4 connected in series with the white led is controlled by the fourth pwm signal corresponding to the white led. And the constant current lighting time of the white light emitting diode in the period of the fourth pulse width modulation signal DW is determined by the fourth pulse width modulation signal DW corresponding to the white light emitting diode.
Referring to fig. 5, the cycle period T common to the respective channels of pulse width modulated signals DR and DG and DB and DW is divided into a plurality of illustrated sub-periods T1-T4. And the effective logic value distribution of each pulse width modulation signal is in a corresponding sub-time period, and then the multiple light-emitting diodes are sequentially lightened in a time-sharing manner in the cycle period T: the effective logic values of the first pwm signal DR, such as logic high level 1, are distributed in the first sub-period T1, the effective logic values of the second pwm signal DG, such as logic high level 1, are distributed in the second sub-period T2, the effective logic values of the third pwm signal DB, such as logic high level 1, are distributed in the third sub-period T3, and the effective logic values of the fourth pwm signal DW, such as logic high level 1, are distributed in the fourth sub-period T4. During the cycle period T, the multiple paths of light-emitting diodes are sequentially lighted in a time-sharing manner: the red led is turned on when the pwm signal DR has an active logic value in the first sub-period T1, the green led is turned on when the pwm signal DG has an active logic value in the second sub-period T2, the blue led is turned on when the pwm signal DB has an active logic value in the third sub-period T3, and the white led is turned on when the pwm signal DW has an active logic value in the fourth sub-period T4. The red leds are not lit at T2-T4 and the green leds are not lit at T1 and T3-T4, the blue leds are not lit at T4 and T1-T2, and the white leds are not lit at T1-T3. Distributing a clock signal to each sub-time period, wherein the number of the clock signals of each sub-time period is a preset value: the number of clock signals of the clock signal CK1 and the first sub-period T1 allocated to the first sub-period T1 is a predetermined value, the number of clock signals of the clock signal CK2 and the second sub-period T2 allocated to the second sub-period T2 is a predetermined value, the number of clock signals of the clock signal CK3 and the third sub-period T3 allocated to the third sub-period T3 is a predetermined value, and the number of clock signals of the clock signal CK4 and the fourth sub-period T4 allocated to the fourth sub-period T4 is a predetermined value. Determining the time length of each sub-period according to the clock signal distributed by each sub-period and the number of the clock signals in a clock counting mode: the time length of the first sub-period T1 is calculated to be equal to the number of clock signals CK1 multiplied by the cycle time of the clock signal CK1, the time length of the second sub-period T2 is the number of clock signals CK2 multiplied by the cycle time of the clock signal CK2, the time length of the third sub-period T3 is the number of clock signals CK3 multiplied by the cycle time of the clock signal CK3, and the time length of the fourth sub-period T4 is the number of clock signals CK4 multiplied by the cycle time of the clock signal CK 4. The frequencies of the plurality of clock signals CK1-CK4 allocated for the sub-periods T1-T4 of each cycle period may be set to be the same or different in alternative examples.
Referring to fig. 4, the plurality of pulse width modulation modules PWM1-PWM4 are configured with a counter CNT outputting a multi-bit count data including designated upper data and designated lower data. It is assumed that the specified upper data includes the upper data Q shown in the figure<M+1>-Q<M+2>And the specified lower data includes Q<M>-Q<0>. The number of sub-periods in each cycle period may be determined by the number of bits Z of the designated upper bits data, and the preset value regarding the number of clock signals in each sub-period may be determined by the number of bits F of the designated lower bits data. The time length of each sub-period is counted by a counter triggered by a clock signal matched with the sub-period: the time length of the first sub-period T1 is triggered by the clock signal CK1 to count the counter CNT, and the time length of the second sub-period T2 is triggered by the clock signalCK2 triggers the counter CNT to count, and the time length of the third sub-period T3 is triggered by the clock signal CK3 to count, and the time length of the last fourth sub-period T4 is triggered by the clock signal CK4 to count. Assuming that the number Z of bits of the designated upper bit data and the number F of bits of the designated lower bit data are both natural numbers greater than zero, for example, if F is M +1, the number of sub-periods in T per cycle period does not exceed 2ZAnd the preset value in each sub-period is 2F. The preset value regarding the number of clock signals in each sub-period can be determined by the number F of bits of the lower bit data specified. In an alternative example, if M is 7 and Z is 2, the number of sub-periods in each cycle does not exceed 4 and the number of clock signals in each sub-period is a predetermined value 256. If four sub-periods are adopted, which correspond to the clock signal CK1 counting 256 times in the first period T1, the clock signal CK2 counting 256 times in the second period T2, the clock signal CK3 counting 256 times in the third period T3, and the clock signal CK4 counting 256 times in the fourth period T4, the total time length of the cycle T is T1+ T2+ T3+ T4. Also for example Z-1 then the number of sub-periods per cycle period T does not exceed 2. Adjusting the frequency of one clock signal allocated to each sub-period corresponds to adjusting the time length of each sub-period, and further adjusting the total time length of the cycle period shared by each pwm signal, for example, adjusting the frequency of CK1-CK4 can adjust the total time length of T. It is assumed in this embodiment that the multi-bit count data output from the counter CNT includes Q<M+2>To Q<0>The high-order data specified in the count data may not be limited to the two-bit Q<M+1>-Q<M+2>The number of bits M +1 of the designated lower data is also optional.
Referring to fig. 4, the counter CNT is configured with a data selector MUX. Clock signals CK1-CK4 distributed for the sub-periods T1-T4 are input to data inputs of the data selector MUX. The assigned high-order data is used as channel selection signal of data selector MUX, such as high-order data Q<M+1>-Q<M+2>The channel select signals SL1/SL2, or address code inputs, are considered as data selectors. If high numberAccording to Q<M+1>-Q<M+2>00 triggers the data selector MUX to switch to the output clock signal CK1, the high data Q<M+1>-Q<M+2>01 triggers the data selector MUX to switch to the output clock signal CK2, the high data Q<M+1>-Q<M+2>A value of 10 triggers the data selector MUX to switch to the output clock signal CK3, the high data Q<M+1>-Q<M+2>A value of 11 triggers the data selector MUX to switch to the output clock signal CK 4. In addition, the first time period T1 may result in the high-order data being carried from the initial 00 to 01 once, the second time period T2 may result in the high-order data being carried from 01 to 10 after the end, and the third time period T3 may result in the high-order data being carried from 10 to 11 after the end. The specified lower data Q in each cycle period T<M>-Q<0>Each time the count expires, it triggers a specific high bit data Q<M+1>-Q<M+2>And carrying out the operation of carrying once, and further triggering the data selector MUX to switch and output different clock signals. For example, in the alternative, the counter CNT is triggered by the clock signal CK1 to count a preset value of 2FObtaining the first sub-period T1 and the lower data Q outputted from the counter CNT when the clock signal CK1 triggers<M>To Q<0>All 1's and the count-up will trigger the specified high-order data Q<M+1>-Q<M+2>Carry operations from 00 to 01 are performed. In an alternative example, the clock signal CK2 triggers the counter CNT to count a preset value of 2FObtaining the second sub-period T2 and the lower data Q outputted from the counter CNT when the clock signal CK2 triggers<M>To Q<0>All 1's and the count-up will trigger the specified high-order data Q<M+1>-Q<M+2>Carry operations from 01 to 10 are performed. In an alternative example, the clock signal CK3 triggers the counter CNT to count a preset value of 2FObtaining a third sub-period T3 and the lower data Q outputted from the counter CNT when the clock signal CK3 triggers<M>To Q<0>All 1's and the count-up will trigger the specified high-order data Q<M+1>-Q<M+2>Carry operations from 10 to 11 are performed. Q is determined when the last cycle period T is over and the next cycle period T comes<M+1>-Q<M+2>And reset to 00. The different channel selection signals being mapped to the output of the data selectorDifferent clock signals, e.g. Q<M+1>-Q<M+2>The four channel selection signals map the different clock signals CK1-CK4 outputted from the data selector, thereby allocating one clock signal for each sub-period and triggering the counter CNT to count. The oscillator OSC generates an initial clock signal which is divided by the divider DIV a plurality of times to obtain four clock signals CK1-CK4 with different frequencies. In an alternative example, the four clock signals CK1-CK4 with different frequencies may be generated independently by four separate oscillators.
Referring to fig. 4, in an alternative embodiment that does not use the data selector MUX, a clock signal may be allocated to each sub-period, and the number of clock signals in each sub-period may be a predetermined value. For example, the clock signal CK1 is directly used to trigger a first counter not shown for counting, the time length of the first sub-period T1 is triggered by the clock signal CK1 matching with the first sub-period T1 to count, and the number of times the first counter counts in the first sub-period T1 may also be a predefined value. In the same way, the clock signal CK2 triggers a second counter not shown to count, the time length of the second sub-period T2 is triggered by the clock signal CK2 matching with the second sub-period T2 to count, and the number of times the second counter counts in the second sub-period T2 may also be a predetermined value. In the same way, the clock signal CK3 triggers a third counter, not shown, to count, the time length of the third sub-period T3 is triggered by the clock signal CK3 matching with the third sub-period T3 to count, and the number of times the third counter counts in the third sub-period T3 may also be a predetermined value. In the same way, the clock signal CK4 triggers a fourth counter not shown to count, the time length of the fourth sub-period T4 is triggered by the clock signal CK4 matching with the fourth sub-period T4 to count, and the number of times the fourth counter counts in the fourth sub-period T4 may also be a predefined value. The same purpose is achieved by clock counting, but more hardware resources are consumed, the time length of each sub-period can be determined according to the number of the clock signals and the clock signals distributed to each sub-period, and the frequencies of the clock signals CK1-CK4 distributed to the sub-periods in each cycle T can be set to be the same or different.
Referring to fig. 5, the first pwm signal DR exhibits an effective logic value, i.e., a logic high level RH, in the first sub-period T1. The second pulse-width modulation signal DG exhibits an effective logic value, i.e., a logic high level GH, during the second sub-period T2. The third pulse width modulated signal DB exhibits an active logic value, i.e., a logic high level BH, during the third sub-period T3. The fourth pulse-width modulated signal DW exhibits an active logic value, i.e., a logic high level WH, during the fourth sub-period T4. The effective logic values of each of the first to fourth pwm signals DR-DW in a corresponding one of the sub-periods are arranged in a continuous manner. The active logic values of the logic high level RH in the first sub-period T1 are arranged in a consecutive manner, the active logic values of the logic high level GH in the second sub-period T2 are arranged in a consecutive manner, the active logic values of the logic high level BH in the third sub-period T3 are arranged in a consecutive manner, and the active logic values of the logic high level WH in the fourth sub-period T4 are arranged in a consecutive manner.
Referring to fig. 5, in an alternative example, the first pulse width modulation module PWM1 is enabled during the first sub-period T1 and compares the red light source matched gray data R < M > -R <0> with the lower data portion Q < M > -Q <0> of the count data of the counter CNT during the first sub-period T1, so that the effective logic level of the first pulse width modulation signal DR may be arranged during the first sub-period T1. The second sub-period 2 starts after the first sub-period T1 is finished, the second pulse width modulation module PWM2 is enabled during the second sub-period T2, and the second pulse width modulation module PWM2 compares the gray data G < M > -G <0> matched to the green light source with the lower data portion of the count data of the counter CNT during the second sub-period T2, i.e., Q < M > -Q <0>, so that the effective logic level of the second pulse width modulation signal DG is arranged to occur during the second sub-period T2. After the second sub-period T2 is completed and the third sub-period T3 is started, the third pulse width modulation module PWM3 is enabled during the third sub-period T3, and the third pulse width modulation module PWM3 compares the gray data B < M > -B <0> matched to the blue light source with the lower data portion of the count data of the counter CNT during the third sub-period T3, i.e., Q < M > -Q <0>, so that the effective logic level of the third pulse width modulation signal DB can be arranged to occur during the third sub-period T3. After the third sub-period T3 is completed and the fourth sub-period T4 is started, the fourth pulse width modulation module PWM4 is enabled during the fourth sub-period T4, and the fourth pulse width modulation module PWM4 compares the gray data W < M > -W <0> matched with the white light sources with the lower data portion of the count data of the counter CNT during the fourth sub-period T4, i.e., Q < M > -Q <0>, so that the effective logic level of the fourth pulse width modulation signal DW can be arranged to occur during the fourth sub-period T4. The first to fourth pulse width modulation modules PWM1-PWM4 respectively use data comparators CMP1-CMP4 to compare the gradation data and the count data. Taking the gray scale data R < M > -R <0> given by the red light source in the first sub-period T1 as an example, when the first sub-period T1 comes, the low-bit data state output by the counter CNT can be used to trigger the RS latch LAT carried by the comparator CMP1 to be set and start outputting high level at the start time of the first sub-period T1, and when the low-bit data Q < M > -Q <0> in the first sub-period T1 is counted from all zeros and once the given gray scale data R < M > -R <0> is counted, the RS latch LAT is triggered to be reset and switched to output low level, that is, the output of the comparator CMP1 is inverted. Other examples take the gray data G < M > -G <0> given by the green light source in the second sub-period T2 as an example, when the low data state output by the counter CNT comes in the second sub-period T2 triggers the RS latch LAT carried by the comparator CMP2 to be set and start outputting high level at the start time of the second sub-period T2, and when the low data Q < M > -Q <0> in the second sub-period T2 counts from all zeros and once the given gray data G < M > -G <0> is counted, the RS latch LAT is triggered to be reset and switched to output low level, i.e. the output of the comparator CMP2 is inverted. Note that in this embodiment, the lower data Q < M > -Q <0> described in the first sub-period T1 starts counting from all 0's until all 1's are counted, and after the lower data Q < M > -Q <0> is counted, it means that the first sub-period T1 ends and the upper data carries one time, and also marks the start of the second sub-period T2 and the lower data Q < M > -Q <0> starts counting from all 0's until all 1's are counted. The lower bit data Q < M > -Q <0> after the second sub-period T2 is counted means that the second sub-period T2 is ended and the upper bit data is carried once more, marking the start of the third sub-period T3 and the lower bit data Q < M > -Q <0> is counted again from all 0's until all 1's are counted. Finally, the low-order data Q < M > -Q <0> after the third sub-period T3 is full means that the third sub-period T3 ends and the high-order data is carried once again, which marks the beginning of the fourth sub-period T4 and the low-order data Q < M > -Q <0> counts again from all 0's until all 1's are counted. Until this one cycle period T is completed and the next cycle period T is entered.
Referring to fig. 6, the respective TIME lengths of the sub-periods T1 to T4 are adjusted in such a manner that the frequencies of the clock signals CK1 to CK4 are adjusted to be high or low during the same TIME 1. T1 of fig. 6 is longer than fig. 5, T2 of fig. 6 is shorter than fig. 5 and T3 of fig. 6 is longer than fig. 5, and T4 of fig. 6 is shorter than fig. 5, but T1+ T2+ T3+ T4 allows for no change. The driving scheme designed for the primary light sources thus allows a flexible distribution over the primary colors and a free distribution of the power contributions of the primary light sources over the cycle period T, even in the face of limited resolution. This is because the frequency of its clock signal CK1 is made lower in the stage T1 of fig. 6 than in fig. 5, and the frequency of its clock signal CK2 is made higher in the stage T2 of fig. 6 than in fig. 5, and similarly the frequency of its clock signal CK3 is made lower in the stage T3 of fig. 6 than in fig. 5, and the frequency of its clock signal CK4 is made higher in the stage T4 of fig. 6 than in fig. 5. This way of frequency conversion is very beneficial for freely assigning the respective luminance ratios of the primary light sources. For example, by changing the turn-on time of the diodes of the primary colors of red, green and blue in the cycle period during color mixing, changing the luminance ratio of the light emitting diodes of the respective primary colors also changes the relative luminance ratio of the primary colors during color mixing. For example, in terms of chromatology, pure white is displayed only when the ratio of the three primary colors of red, green and blue is 3:6:1, if any deviation exists in the actual ratio, deviation of white balance occurs, and the phenomenon that white has a bluish color or yellowish green color easily occurs.
Referring to fig. 7, the respective TIME lengths of the sub-periods T1 to T4 are adjusted in such a manner that the frequencies of the clock signals CK1 to CK4 are adjusted to be high or low during the same TIME 1. T1 of fig. 7 is a half of fig. 5, T2 of fig. 7 is a half of fig. 5 and T3 of fig. 7 is a half of fig. 5, and T4 of fig. 7 is a half of fig. 5. The total time length T of fig. 7 is half of the total time length T of fig. 5. The total time length of the cycle period shared by all the pulse width modulation signals can be flexibly adjusted.
Referring to fig. 8, it is recalled that the embodiment described in fig. 1 is equipped with multiple constant current cells CC1-CC4 and requires that a first light emitting diode LED1 is provided in series with its corresponding constant current cell CC1, a second light emitting diode LED2 is provided in series with its corresponding constant current cell CC2, and that a third light emitting diode LED3 is provided in series with its corresponding constant current cell CC3, and a fourth light emitting diode LED4 is provided in series with its constant current cell CC 4. Under the condition that each path of light emitting diode is individually connected in series with a corresponding path of constant current unit in a one-to-one manner, when an effective logic level, such as a high level, of a path of pulse width modulation signal, such as the first path of pulse width modulation signal, corresponding to any path of light emitting diode, such as the first path of light emitting diode LED1, occurs, the any path of light emitting diode, such as the first path of light emitting diode LED1, is turned on, and a path of constant current unit, such as the constant current unit CC1, connected in series with the any path of light emitting diode is enabled. This embodiment proposes to replace the embodiment of fig. 1 with a solution that can save the number of components and reduce the chip area. The original design method that each path of light emitting diode is connected with one corresponding path of constant current unit in series in a one-to-one mode is eliminated, the constant current unit CC1 is reserved as a matched public constant current unit, the total number of the constant current units is single, and other constant current units CC2-CC4 are abandoned. The new design requires that each LED is connected in series with the common constant current unit, the first LED1 is connected in series with the common constant current unit CC1 through the corresponding first switch S1, the second LED2 is connected in series with the common constant current unit CC1 through the corresponding second switch S2, the third LED3 is connected in series with the common constant current unit CC1 through the corresponding third switch S3, and the fourth LED4 is connected in series with the common constant current unit CC1 through the corresponding fourth switch S4. When an effective logic level appears in one of the pulse width modulation signals corresponding to any one of the light emitting diodes, the common constant current unit CC1 is enabled and any one of the light emitting diodes is switched to be connected in series with the common constant current unit CC1 to be turned on. When the first pwm signal appears active logic level, for example, appears high level, the first switch S1 is turned on, so that the common constant current unit CC1 is further enabled and the first LED1 is switched to be connected in series with the common constant current unit CC1 to light up. When the second pwm signal has an active logic level, such as a high level, the second switch S2 is turned on to further enable the common constant current cell CC1 and the second LED2 to be switched to be connected in series with the common constant current cell CC1 to be turned on. When the third pwm signal exhibits an active logic level, such as a high level, the third switch S3 is turned on to further enable the constant current unit CC1 and the third LED3 to be switched to be connected in series with the common constant current unit CC1 to be turned on. When the active logic level of the fourth pwm signal is high, the fourth switch S4 is turned on to further enable the constant current unit CC1 and the fourth LED4 to be connected in series with the common constant current unit CC1 to be turned on. Each light emitting diode and the common constant current unit are coupled in series between a power supply input terminal and a potential reference terminal. Since the first to fourth switches are controlled by the first to fourth pulse width modulation signals, respectively, they are turned on in an active logic level, e.g., a high state, and turned off in an inactive logic level, e.g., a low state. Whether each path of light emitting diode flows through the constant current provided by the public constant current unit connected in series with the light emitting diode is still controlled by the corresponding pulse width modulation signal, and the constant current lighting time of each path of light emitting diode in the period of the pulse width modulation signal is still determined by the corresponding pulse width modulation signal, so that the display effects obtained by arranging a plurality of paths of constant current units and arranging a single and public constant current unit are completely the same.
Referring to fig. 8, the data transmission module DAT1 of the driving circuit is provided with a decoder for decoding input serial data according to a predetermined communication protocol and decoding gray data from the received communication data, and the driving circuit adjusts the gray levels of the light emitting diodes of the respective paths according to the respective gray data assigned to the light emitting diodes of the respective paths. If the constant current unit CC1 is set in a mode in which the supplied constant current is fixed, the current flowing when any light emitting diode is turned on is held by the fixed constant current supplied from the constant current unit CC1 in any frame of communication data, the design is simpler and the constant current supplied from the constant current unit does not need to be changed. When the previous frame of communication data received by the driving circuit is refreshed to the next frame of communication data to adjust the respective gray scale data of the multiple light emitting diodes, taking the three-primary-color light source as an example, the color mixture color corresponding to the gray scale data decoded by the previous frame of communication data is different from the color mixture color corresponding to the gray scale data decoded by the next frame of communication data, so that the power consumption of the three-primary-color light emitting diodes under the condition of the gray scale data of the previous frame is different from the power consumption of the three-primary-color light emitting diodes under the condition of the gray scale data of the next frame without any doubt. If the constant current cell CC1 provides a fixed constant current, the aforementioned power consumption difference caused by different communication data frames may cause power waste, and the power waste phenomenon becomes more obvious when the number of the driving circuits connected in cascade is larger. Conversely, as an alternative to the fixed constant current, the magnitude of the constant current provided to each led can be adjusted by setting the programmable constant current unit CC1 in a mode that the provided constant current can be adjusted. Taking the three primary colors as an example, when the mixed color requires to provide a larger constant current to match the display effect, the constant current is adjusted to be larger, and when the mixed color requires to provide a smaller constant current to match the display effect, the constant current is adjusted to be smaller. The data transmission module DAT1 of the driver circuit is provided with a decoder for decoding the input serial data according to a predetermined communication protocol and decoding the constant current adjustment data from the received communication data, and the driver circuit adjusts the magnitude of the constant current provided by the constant current cell CC1 according to the constant current adjustment data allocated to the programmable constant current cell CC 1. It is apparent that the data transmission module DAT1 of the driving circuit arrangement can decode various types of data having different purposes or different meanings from the communication data, not just the gray data.
Referring to fig. 8, the specific embodiment of adjusting the magnitude of the constant current provided by the constant current cell CC1 in setting the programmable constant current cell is various. The data Y < X > to Y <0> represent the constant current regulating data which the driving circuit decodes and which is assigned to the constant current cell CC1, and the natural number X representing the number of data bits is greater than 1. The constant current adjustment data is used to fine tune the resistance of the sampling resistor RS1/RS2 as shown in FIGS. 2-3 for the purpose of adjusting the magnitude of the constant current provided by the constant current cell CC 1. The same objective of adjusting the magnitude of the constant current provided by the constant current cell CC1 can be achieved if the constant current adjustment data is used to fine tune the voltage values of the reference voltages VB1/VB 2. Fig. 8 is provided with a single number of common constant current cells CC1 so that the constant current adjusting data can be used to adjust the magnitude value of the constant current supplied from the common constant current cell CC 1. The other constant current cells CC2-CC4 shown in fig. 1 can be configured as programmable constant current cells, except that the driving circuit needs to increase the storage capacity of the latch or buffer for storing the constant current adjustment data, because the data amount of the constant current adjustment data that the driving circuit needs to receive increases, so that each constant current cell can be allocated with the corresponding constant current adjustment data to adjust the magnitude of the constant current provided by each programmable constant current cell.
Referring to fig. 8, the shunt module SHU connected in parallel with the light emitting diodes LED1-LED4 functions as a shunt and also stabilizes the input voltage supplied to the driving circuit at a desired value. The circuit structure implementing the basic functions of the shunting module SHU is likewise not unique but diverse. IN an alternative example, the shunting module SHU uses an NPN bipolar transistor such that the power input terminal IN is connected to the collector of the NPN bipolar transistor and the potential reference terminal OUT is connected to the emitter of the NPN bipolar transistor. A Zener diode is connected between the collector and the base of the NPN bipolar transistor, and a resistor is connected between the base and the emitter, the cathode of the Zener diode is connected to the collector of the NPN bipolar transistor, and the anode of the Zener diode is connected to the base of the NPN bipolar transistor. A cathode of a voltage regulator tube is coupled to the power input end IN and an anode of the voltage regulator tube is coupled to the potential reference end OUT to stabilize the input voltage of the driving circuit. IN alternative embodiments the shunt module SHU employs a PNP bipolar transistor such that the power input terminal IN is coupled to the emitter of the PNP bipolar transistor and the potential reference terminal OUT is coupled to the collector of the PNP bipolar transistor. The PNP bipolar transistor has a Zener diode connected between the collector and the base and a resistor connected between the base and the emitter, wherein the cathode of the Zener diode is connected to the base of the PNP bipolar transistor and the anode of the Zener diode is connected to the collector of the PNP bipolar transistor, and a voltage regulator is used for stabilizing the input voltage of the driving circuit. The cathode of the voltage regulator tube is connected to the power input terminal IN and the anode of the voltage regulator tube is coupled to the potential reference terminal OUT. Therefore, the scheme of the shunting module SHU is diversified.
Referring to fig. 8, a shunt module SHU connected in parallel with the light emitting diodes LED1-LED4 uses an adjustable parallel type voltage reference circuit ZT in the preferred embodiment. The adjustable parallel voltage reference circuit can be designed into a discrete device and can be integrated into an integrated circuit to be used as a part of functional modules of a driving chip. Terms such as Adjustable shunt reference voltage source or Adjustable precision shunt regulator (Adjustable shunt regulator) or programmable reference source circuit or Three-terminal programmable shunt regulator (Three-terminal programmable shunt regulator) or programmable shunt voltage reference source are used to describe the Adjustable shunt voltage reference circuit, except that naming rules of different manufacturers or users are slightly different to cause inconsistent terminology. Controllable precision voltage regulators TL431 and TL432 are the most common types of electronic components for adjustable parallel voltage reference circuits. The adjustable parallel voltage reference circuit is generally known as a cathode C (cathode), an anode A (anode), and a reference terminal R (reference). The simple scheme is that each path of light emitting diode and one path of constant current unit are coupled in series between a power supply input end and a potential reference end. As shown IN fig. 1, the light emitting diode LED1 and the constant current unit CC1 are connected IN series between the power input terminal IN and the potential reference terminal OUT, the light emitting diode LED2 and the constant current unit CC2 are connected IN series between the power input terminal IN and the potential reference terminal OUT, the light emitting diode LED3 and the constant current unit CC3 are connected IN series between the power input terminal IN and the potential reference terminal OUT, the light emitting diode LED4 and the constant current unit CC4 are connected IN series between the power input terminal IN and the potential reference terminal OUT so as to directly supply power to each of the light emitting diodes by using the input voltage at the power input terminal IN, and the shunt module SHU may also be coupled IN series between the power input terminal IN and the potential reference terminal OUT. IN fact, this is by no means the only solution because the divided voltage of the input voltage at the power input terminal IN can also supply power to each of the light emitting diodes, and IN an alternative embodiment, each of the light emitting diodes and a corresponding one of the constant current units can be arranged to be coupled IN series between the divided voltage of the input voltage and the potential reference terminal, and the shunt module SHU connected IN parallel with the light emitting diodes and the bypass module described later can also be arranged to be coupled between the divided voltage of the input voltage and the potential reference terminal. IN other embodiments, the stable voltage obtained by performing voltage conversion on the input voltage provided by the power input terminal IN may be used to power each of the light emitting diodes, each of the light emitting diodes and a corresponding one of the constant current units are coupled IN series between the stable voltage obtained by voltage conversion and the potential reference terminal, and the shunt module SHU connected IN parallel with the light emitting diodes and the bypass module described later are also coupled between the stable voltage obtained by voltage conversion and the potential reference terminal. For the sake of brevity, the embodiments that use the divided voltages of various forms of the input voltage as the power supply voltage of each light emitting diode, or use the stable voltage obtained by performing linear or switch-type voltage conversion on the input voltage as the power supply voltage of each light emitting diode are not described in detail in the drawings. Therefore, as long as the series structure formed by the light emitting diode and the constant current unit connected in series, the shunt module and the bypass module described later satisfy the parallel relationship, it is allowable that the three are connected in parallel between the power input end and the potential reference end or between two other nodes with potential difference. For example, if the former of the first node and the second node has a potential difference higher than the latter, the three nodes connected in parallel between the first node and the second node can also achieve the same functions of constant current control, current division, voltage stabilization, etc., and it should be appreciated that the three nodes connected in parallel between the power input terminal and the potential reference terminal in the figure are merely illustrative examples and are not limiting.
Referring to fig. 8, an example of a driving circuit designed to drive a chip IC is shown. Each of the light emitting diodes and the common constant current unit are coupled IN series between the power input terminal IN and the potential reference terminal OUT, and the shunt module SHU is also coupled between the power input terminal IN and the potential reference terminal OUT as a parallel configuration thereof. The shunting module SHU optionally contains an adjustable parallel voltage reference circuit ZT and the cathode C is coupled to the power input IN via a resistor or not and the anode a of the adjustable parallel voltage reference circuit ZT is further arranged to be coupled to the potential reference OUT. The resistance voltage divider VD is matched with the adjustable parallel type voltage reference circuit ZT, a reference end R of the adjustable parallel type voltage reference circuit ZT is coupled to a voltage dividing node of the resistance voltage divider, namely to the interconnection position of two resistors IN the resistance voltage divider, and the resistance voltage divider is also connected between a power input end IN and a potential reference end OUT.
Referring to fig. 9, when the first to third pwm signals DR and DG and DB as described above are used, a single period time T of the pwm signal is divided into three sub-periods, and an active logic level of each pwm signal is allocated in a corresponding one of the sub-periods. The result of the NOR operation performed by the PWM signals DR, DG and DB is regarded as the control signal DX of the bypass module, and the bypass module is triggered to be conducted and the shunting is performed on the multiple paths of light emitting diodes when the control signal DX has an effective logic level, such as a high level. In an alternative example, the shunt current of the bypass module is determined by the constant current cell CC1 described in fig. 9-10 or the shunt current is determined by the constant current cell CC5 described in the scheme of fig. 11. The bypass module in fig. 9 includes a constant current cell CC1 and a resistor RX connected in series therewith. The fig. 10 bypass module contains a constant current cell CC1 and a diode LED5 in series therewith. The bypass module in fig. 11 includes a constant current cell CC5 and a resistor RX connected in series therewith.
Referring to fig. 9, the current adjustment data allocated to the current source module PCS later is used to set the output current IT of the constant current source of the current source module PCS, part of the constant current adjustment data allocated to the driving circuit is used at least to set the value of the constant current I1 of the constant current unit CC1 of fig. 9 or fig. 10, or part of the constant current adjustment data allocated to the driving circuit is used to set the value of the constant current I5 supplied from the constant current unit CC5 of fig. 11 in the same frame of communication data. Taking the driving circuit for driving the first to third light emitting diodes LED1-LED3 as an example to explain the scheme of the present example, the result of performing nor logic operation on the pwm signals DR, DG and DB is used as the control signal DX of the bypass module. The control signal DX is caused to be at a high level during the low level period of the first pwm signal DR in the first sub-period T1, at a high level during the low level period of the second pwm signal DG in the second sub-period T2, and at a high level during the low level period of the third pwm signal DB in the third sub-period T3, and the bypass module is turned on whenever the high level XH occurs in the control signal. In this example, the driving circuit drives only three LEDs, and the total time duration of the cycle T is T1+ T2+ T3. The first to third pwm signals DR, DG and DB are respectively input to several input terminals of the nor gate 300, and the control signal DX output from the nor gate 300 is used to control whether the bypass module is turned on. The shunt current determined by the constant current unit CC1 or the shunt current determined by the constant current unit CC5 in case of the bypass module being turned on is limited not to exceed the output current of the constant current source in the current source module PCS.
Referring to fig. 1, in view of the first to fourth light emitting diodes LED1-LED4 being configured to be sequentially turned on, i.e. their turn-on times do not overlap, it can be defined that the current flowing through each light emitting diode does not exceed the output current of the constant current source module. The current I1 flowing through the first light emitting diode LED1 is limited within the first sub-period T1 not to exceed the output current IT determined by the current source module. And defining the current I2 flowing through the second light emitting diode LED2 not to exceed the output current IT determined by the current source module within the second sub-period T2. The third sub-period T3 also defines that the current I3 flowing through the third light emitting diode LED3 does not exceed the output current IT determined by the current source module. And the current I4 flowing through the fourth light emitting diode LED4 in the fourth sub-period T4 is also satisfied to not exceed the output current IT of the current source module. The currents I1 to I4 flowing when the first to fourth light emitting diodes LED1 to LED4 are turned on in the embodiment of fig. 1 are respectively provided by the constant current units CC1 to CC 4. In the alternative embodiment shown in fig. 9, the currents I1-I3 flowing through the first to third light emitting diodes LED1-LED3 are provided by the common constant current unit CC1, and the current of the load resistor RX of the bypass module is also provided by the constant current unit CC 1.
Referring to fig. 9, the main difference between this embodiment and the embodiment in fig. 1 is that a bypass module is added and the new design scheme requires that each led is connected in series with the common constant current unit. The first light emitting diode LED1 is connected in series with the common constant current unit CC1 through the corresponding first switch S1, the second light emitting diode LED2 is connected in series with the common constant current unit CC1 through the corresponding second switch S2, and the third light emitting diode LED3 is connected in series with the common constant current unit CC1 through the corresponding third switch S3. The load resistor RX of the bypass module is connected in series with the common constant current unit CC1 through the corresponding fifth switch S5. When the pulse width modulation signal corresponding to any one of the light emitting diodes appears at an effective logic level, the common constant current unit CC1 is enabled and any one of the light emitting diodes is switched to be connected in series with the common constant current unit CC1 to be turned on. When the first pwm signal appears active logic level, for example, appears high level, the first switch S1 is turned on, so that the common constant current unit CC1 is further enabled and the first LED1 is switched to be connected in series with the common constant current unit CC1 to light up. When the second pwm signal has an active logic level, such as a high level, the second switch S2 is turned on to further enable the common constant current cell CC1 and the second LED2 to be switched to be connected in series with the common constant current cell CC1 to be turned on. When the third pwm signal exhibits an active logic level, such as a high level, the third switch S3 is turned on to further enable the constant current unit CC1 and the third LED3 to be switched to be connected in series with the common constant current unit CC1 to be turned on. Each path of light emitting diode and the common constant current unit are coupled between the power supply input end and the potential reference end in series, and the load resistor and the common constant current unit in the bypass module are coupled between the power supply input end and the potential reference end in series. The bypass module is connected with the multiple paths of light-emitting diodes in parallel, and the result of the multiple paths of pulse width modulation signals executing the NOR logic operation is regarded as the control signal of the bypass module. The first to third pwm signals DR, DG and DB are respectively input to a plurality of input terminals of the nor gate 300, the result DX obtained by performing nor logic operation on the first to third pwm signals is used to control whether the fifth switch S5 is turned on or off and regards it as a control signal, and whether the bypass module is turned on or off depends on the logic state of the control signal DX.
Referring to fig. 9, if the control signal DX is at an active logic level value, such as a high level, the bypass module is triggered to shunt the total input current of the driving circuit. For example, the fifth switch S5 is turned on when the control signal DX is at the active logic level or the fifth switch S5 is turned off when the control signal DX is at the inactive logic level, e.g., the low level. The bypass module in this example includes a load resistor RX and its associated fifth switch S5 and a common constant current cell CC 1. The bypass module is not the only circuit configuration, e.g. using a forward conducting conventional diode instead of the load resistor RX, but is also an optional example of the bypass module, it is noted that the anode of the conventional diode should be coupled to the power supply input and the cathode should be coupled to the constant current unit. Alternatively, the load resistor RX may be serially connected to the conventional diode and then serially connected to the constant current unit CC1 between the power input terminal and the potential reference terminal, so that the anode of the conventional diode should be directly or indirectly coupled to the power input terminal and the cathode should be directly or indirectly coupled to the constant current unit. It is even possible to couple the conventional diode and the load resistor RX in parallel and then in series with the constant current unit CC1 between the power input terminal and the potential reference terminal, and it should be noted that the anode of the conventional diode should be coupled to the power input terminal and the cathode should be coupled to the constant current unit. In other alternative embodiments of the bypass module, the load resistor RX may be replaced by a mosfet in diode connection, or by a bipolar transistor in base-collector connection, i.e. a passive load, like the load resistor RX, may be replaced by an active load. The active load when coupled in series with the constant current cell CC1 in the bypass module is connected in such a way that: the fifth switch S5 should turn on immediately upon being controlled by the control signal to turn on and generate a voltage drop across the active load. In other words, as long as any load is arranged in the bypass module and connected in series with the constant current unit CC, when the control signal DX has an active logic level, the bypass module is triggered to conduct and shunt the total input current of the driving circuit, and at this time, the active load or the passive load included in the bypass module flows through the constant current provided by the constant current unit CC 1. Therefore, the shunt current flowing when the bypass module is connected and shunted can be considered to be a preset constant current value.
Referring to fig. 10, the bypass module includes a common constant current cell CC1 and a load connected in series therewith, and the diode LED5 may include a light emitting diode such as a white light emitting diode or a conventional diode that does not emit light as a load. The bypass module in fig. 9 includes a common constant current cell CC1 and a load, i.e., a resistor RX, connected in series therewith. The bypass module in fig. 11 includes a non-common but independent constant current cell CC5 and a load, i.e., a resistor RX, connected in series therewith.
Referring to fig. 11, the main difference between this embodiment and fig. 10 is that the multiple light emitting diodes and the bypass module no longer share the same common constant current unit CC1, and each light emitting diode and the bypass module are equipped with a constant current unit. The new design requires that each light emitting diode is connected in series with its corresponding constant current unit. The first path of light emitting diode LED1 and the corresponding constant current unit CC1 are connected in series between the power input end and the potential reference end, the second path of light emitting diode LED2 and the corresponding constant current unit CC2 are connected in series between the power input end and the potential reference end, and the third path of light emitting diode LED3 and the corresponding constant current unit CC3 are connected in series between the power input end and the potential reference end. The load resistor RX of the bypass module and the corresponding constant current unit CC5 are connected in series between the power input terminal and the potential reference terminal. When the pulse width modulation signal corresponding to any one path of light emitting diode has an effective logic level, the constant current unit connected in series with the light emitting diode is started, and when the control signal DX has an effective logic level, the constant current unit connected in series with the load resistor RX is started. When the first pwm signal is asserted, for example, when the first pwm signal is asserted high, the constant current unit CC1 is enabled and the first LED1 is turned on because it receives the constant current from the constant current unit CC1 connected in series. When the second pwm signal is asserted, for example, high, the constant current cell CC2 is enabled and the second LED2 is turned on because it receives the constant current from the constant current cell CC2 connected in series. When the third pwm signal is asserted, e.g., high, the constant current cell CC3 is enabled and the third LED3 is turned on because it receives a constant current from the series-connected constant current cell CC 3. An alternative case in which the constant current cell CC5 of the bypass module is turned on or off is described with an example of the constant current cell CC1 in fig. 2. A controlled switch, not shown, is provided between the output terminal of the error amplifier EA1 of the constant current unit CC5 and the control terminal of the transistor MQ, the control signal DX can be used to control whether the controlled switch is turned on or not, the controlled switch is turned on when the control signal DX has an active logic level, such as a high level, and further causes the constant current unit CC5 to be enabled and the load resistor RX to flow through the constant current provided by the constant current unit CC5, and conversely, the controlled switch is turned off when the control signal DX has an inactive logic level, such as a low level. The first to third pwm signals DR, DG and DB are respectively input to a plurality of input terminals of the nor gate 300, and a result DX obtained by performing a nor operation on the first to third pwm signals is used to control whether the constant current cell CC5 is turned on or off.
Referring to fig. 12, it is described that the multi-bit count data output from the counter CNT includes designated upper bit data and designated lower bit data, and the designated lower bit data includes Q < M > -Q <0 >. The value Q <0> in the combinational logic circuit LG outputs a pulse signal O < M > via the illustrated buffer BF. Q < M > is set to be inverted to QN < M >, i.e., any value, Q, after being inverted is defined herein as QN. In the combinational logic circuit, QN <0> and Q <1> obtained by inverting output of Q <0> through the inverter IV are input into the AND gate A1 and the AND gate A1 to output a pulse signal O < M-1 >. In the combinational logic circuit, the values Q <2> and QN <1> and QN <0> are inputted to an AND gate A2, so that a pulse signal O < M-2> can be outputted from an AND gate A2. In the combinational logic circuit, the values Q <3> and QN <2> and QN <1> and QN <0> are inputted into another AND gate A3, so that the pulse signal O < M-3> can be outputted from the AND gate A3. It is assumed that QN < M-1>, QN < M-2>, QN < M-3>, … … QN <0> and the value Q < M > are all inputted to the illustrated and gate AM in the combinational logic circuit according to the same principle, which is equivalent to QN < M-1> to QN <0> that M pieces of inverted data and the value Q < M > are all inputted to the illustrated and gate AM so that the pulse signal O <0> can be outputted from the and gate AM. M +1 so-called pulse signals, that is, a series of pulse signals including O < M > to O <0>, can be obtained. The series of M +1 groups of pulse signals can be provided for a plurality of pulse width modulation modules, and each pulse width modulation module forms a corresponding pulse width modulation signal according to the gray scale data matched with one path of light emitting diode paired with the pulse width modulation module and the series of pulse signals O < M > to O <0 >.
Referring to fig. 12, taking the gray data R < M > -R <0> of the red light source as an example: in this example, data R < M > AND pulse signal O < M > are input to a first AND gate AND. The data R < M-1> AND the pulse signal O < M-1> are inputted to another second AND gate AND. The data R < M-2> AND the pulse signal O < M-2> are inputted to a third AND gate AND AND so on, AND the data R < M-3> AND the pulse signal O < M-3> are inputted to a fourth AND gate AND. Analogize according to the same principle until the data R <0> AND the pulse signal O <0> are inputted to the M +1 th AND gate AND. Summing up M +1 AND gates AND they output a result of M +1 set of AND-gates in total. The outputs of the first to M +1 th AND gates AND are all sent to an OR gate OR shown in the figure, AND the output of the OR gate OR is regarded as the first pulse width modulation signal DR of the red light source. Light sources of other colors may also get the second and third pulse width modulation signals DG-DB through this mode. The principle of generating the PWM signal is to form M +1 groups of pulse signals, i.e., O <0>, O <1>, O <2>, … … O < M >, and then to use the gray data R < M > -R <0> of red light source to select whether to mask the pulse signals: when data R <0> takes 0, the pulse signal O <0> is masked and data R <0> takes 1, the pulse signal O <0> is not masked, when data R <1> takes 0, the pulse signal O <1> is masked and when data R <1> takes 1, the pulse signal O <1> is not masked, when data R <2> takes 0, the pulse signal O <2> is masked and when data R <2> takes 1, the pulse signal O <2> is not masked, and when data R < M > takes 0, the pulse signal O < M > is masked and when data R < M > takes 1, the pulse signal O < M > is not masked. The first path of pulse width modulation signal DR representing the duty ratio information carried by the gray scale data R < M > -R <0> is obtained by selecting whether the pulse signals O <0>, O <1>, O <2> and … … O < M > are output from the OR gate OR OR not through the shielding gating effect of the gray scale data R < M > -R <0> of the red light source.
Referring to fig. 13, in an alternative embodiment multiple channels of leds, such as three primary light sources and white light, correspond to multiple channels of pwm signals, such as first through fourth channels of pwm signals DR and DG and DB and DW. The period time T of the pwm signals is divided into a plurality of sub-periods, such as a first sub-period and a second sub-period, and a third sub-period and a fourth sub-period, and at the same time, the active logic level, such as the high level, of each pwm signal is allocated in a corresponding sub-period. For example, the active logic high level of the first pwm signal DR may be allocated in the corresponding first sub-period T1, the active logic high level of the second pwm signal DG may be allocated in the corresponding second sub-period T2, the active logic high level of the third pwm signal DB may be allocated in the corresponding third sub-period T3, and the active logic high level of the fourth pwm signal DW may be allocated in the corresponding fourth sub-period T4. In the embodiments of fig. 9-10 and fig. 11, the first to fourth paths of pwm signals DR and DG and DB and DW are respectively input to several input terminals of the nor gate 300, and the first to fourth paths of pwm signals DR and DG and DB and DW perform nor logic operation to obtain the control signal DX. The control signal DX, which causes the nor gate 300 to output, controls whether the fifth switch S5 of fig. 9-10 is turned on or not, and controls whether the constant current cell CC5 described in fig. 11 is turned on or not. When the control signal DX has an active logic level, for example, a high level triggers the bypass module to be switched on. For example, in the first sub-period T1, when the low level of the first pwm signal DR occurs, the control signal DX is high, when the low level of the second pwm signal DG occurs, the control signal DX is high, in the second sub-period T2, the third pwm signal DB occurs, when the low level of the third pwm signal DB occurs, the control signal DX is high, in the third sub-period T3, and when the low level of the fourth pwm signal DW occurs, the control signal DX is high, in the fourth sub-period T4. The high level XH represents a waveform when the control signal DX is at an active logic value, such as a high level, and when the control signal DX has a high level XH period, the bypass module is turned on and shunted. The effective logic values of each pulse width modulation signal in the corresponding sub-time period are arranged in a continuous mode: the effective logic values of the first pwm signal DR in T1 are arranged in a continuous manner, the effective logic values of the second pwm signal DG in T2 are arranged in a continuous manner, the effective logic values of the third pwm signal DB in T3 are arranged in a continuous manner, and the effective logic values of the fourth pwm signal DW in T4 are arranged in a continuous manner.
Referring to fig. 14, the example of fig. 12 may arrange the valid logic values, i.e., SRH, of the first pwm signal DR in a distributed manner in the first sub-period T1. It is also possible to arrange the effective logic values SGH of the second pulse-width modulation signal DG in the T2 in a decentralized manner, to arrange the effective logic values SBH of the third pulse-width modulation signal DB in the T3 in a decentralized manner, and to arrange the effective logic values SWH of the fourth pulse-width modulation signal DH in the T4 in a decentralized manner. In contrast to fig. 13-14, fig. 14 can essentially break up the pwm signal with continuous active logic values into several shorter discrete or discrete active logic values. For example, the first pwm signal DR may be broken up in the continuous effective logic value RH shown in fig. 13 to become a plurality of shorter distributed effective logic values SRH shown in fig. 14, and the duty ratio of the continuous effective logic value RH is still equal to the duty ratio of the distributed effective logic values SRH. Similarly, the continuous effective logic value GH of the second pwm signal DG is broken into several shorter distributed effective logic values SGH. The continuous effective logic value BH of the third pwm signal DB is broken into several scattered effective logic values SBH. The continuous effective logic values WH of the fourth pulse-width modulation signal DW are broken up into several discrete effective logic values SWH. Note that in fig. 14, several discrete channels of pwm signals DR and DG, and DB and DW still perform nor logic operation, the operation result is regarded as the control signal DX of the bypass module connected in parallel with the multiple channels of leds, and when the control signal DX has a valid logic value, the bypass module is triggered to conduct and shunt. The control signal DX output from the nor gate 300 controls whether the fifth switch S5 of fig. 9 to 10 is turned on or not and controls whether the constant current cell CC5 described in fig. 11 is turned on or not. When the control signal has an effective logic level, for example, a high level triggers the bypass module to be switched on. For example, in the first sub-period T1, when the low level period of the first pulse width modulation signal DR causes the control signal DX to be at a high level, when the low level period of the second pulse width modulation signal DG occurs in the second sub-period T2, the control signal DX is at a high level, when the low level occurs in the third pulse width modulation signal DB in the third sub-period T3, the control signal DX is at a high level, and when the low level occurs in the fourth pulse width modulation signal DW in the fourth sub-period T4, the control signal DX is at a high level. The high level XH represents a waveform when the control signal DX is at an effective logic value, such as a high level, and the occurrence of the high level XH in the control signal DX causes the bypass module to be conducted and shunted. The valid logic values of the pulse width modulated signal within the respective sub-period are arranged in a discrete manner: the effective logic values of the first pwm signal DR in T1 are arranged in a discrete manner, the effective logic values of the second pwm signal DG in T2 are arranged in a discrete manner, the effective logic values of the third pwm signal DB in T3 are arranged in a discrete manner, and the effective logic values of the fourth pwm signal DW in T4 are arranged in a discrete manner. The high level of the pulse width modulation signal is scattered into a plurality of shorter high levels, the sum of the scattered high levels is equal to the high level before scattering, and the sum of the duty ratios of the scattered high levels is equal to the duty ratio before scattering, which belongs to the Scambred-PWM (scanning pulse width modulation) technology. The application can lead the display system to have finer pictures and higher color gray scale: the design idea is that under the premise of not changing the duty ratio of the original pulse width signal, the original pulse width signal is scattered into a plurality of small secondary pulse width signals or sub-pulse width signals, and the duty ratio of each small secondary pulse width signal or sub-pulse width signal is completely the same as that of the original integral pulse width signal.
Referring to fig. 14, the duty ratio of the SRH, which is an effective logic value during the first sub-period T1 in fig. 14, is substantially equal to the duty ratio of the RH, which is an effective logic value during the first sub-period T1 in fig. 13. It can be similarly seen in fig. 14 that the duty cycle of the effective logic value SGH in the second sub-period T2 is substantially equal to the duty cycle of the effective logic value GH in the second sub-period in fig. 13. The duty ratio of the SBH, which is an effective logic value in the third sub-period T3 in fig. 14, is also substantially equal to the duty ratio of the BH, which is an effective logic value in the third sub-period T3 in fig. 13. The duty ratio of the effective logic value SWH in the fourth sub-period T4 in fig. 14 is equally equal to the duty ratio of the effective logic value WH in the fourth sub-period T4 in fig. 13. In this example, the discrete control signal DX controls whether the bypass module is turned on, and the result of the NOR operation performed by the PWM signals DR-DW is defined as the control signal DX. It was found in comparison with fig. 13 that the bypass module also has a very high switching frequency: because the longer active high logic value of the control signal DX in fig. 13 is also broken up into discrete active logic values in fig. 14. It can be considered that the effective logic values of the control signals for each sub-period are arranged in a dispersed manner in fig. 14, and the effective logic values of the control signals for each sub-period are arranged in a continuous manner in fig. 13. The current of the bypass module under the condition of switching on and shunting is a preset constant current value. If the load of the bypass module is a light emitting diode, such as diode LED5 of fig. 10, it is of great benefit that the control signal DX is broken up to be set to discrete valid logic values. Since the display refresh rate of the LED5 is increased, if the load diode LED5 of the bypass module is turned off or on as shown in fig. 13 for a long time, the visually displayed picture will show a flicker phenomenon, and the discrete control signal can increase the screen refresh rate and avoid the flicker phenomenon.
Referring to fig. 15, the counter CNT is configured with a data selector MUX to which clock signals CK1-CK3 distributed for sub-periods T1-T3 are input to data inputs thereof. The designated high-order data is used as the channel selection signal of the data selector MUX, such as the high-order data Q < M +1> -Q < M +2> is used as the channel selection signal SL1/SL2 of the data selector or the address code input. If the high-order data Q < M +1> -Q < M +2> is 00, the data selector MUX will be triggered to switch to the output clock signal CK1, if the high-order data Q < M +1> -Q < M +2> is 01, the data selector MUX will be triggered to switch to the output clock signal CK2, and if the high-order data Q < M +1> -Q < M +2> is 10, the data selector MUX will be triggered to switch to the output clock signal CK 3. The high data is carried from the initial 00 to 01 once after the first period T1 is over, and carried from 01 to 10 after the second period T2 is over. After the low-order data Q < M > -Q <0> specified in each cycle period T is counted from all 0 to all 1 and is full, the operation of causing the specified high-order data Q < M +1> -Q < M +2> to carry out one time is triggered, and then the data selector is triggered to switch and output different clock signals. For example, three states of Q < M +1> -Q < M +2>, i.e. three channel selection signals, are mapped to different clock signals CK1-CK3 outputted from the data selector, so that each sub-period of T1-T3 can be assigned a corresponding one of the clock signals and used to trigger the counter CNT to count. In this embodiment, only three leds of primary colors red, green and blue are used, so that the cycle period T is T1+ T2+ T3, and the three states of different channel selection signals, e.g. high bits, also map the data selector outputting three different clock signals.
Referring to fig. 15, the embodiment is also designed such that the time length of each sub-period is counted by the counter triggered by the clock signal matched with the sub-period: the time length of the first sub-period T1 is counted by the counter CNT triggered by the clock signal CK1, the time length of the second sub-period T2 is counted by the counter CNT triggered by the clock signal CK2, and the time length of the third sub-period T3 is counted by the counter CNT triggered by the clock signal CK 3. The generation mechanism of the pulse width modulated signal in this embodiment is different from that of fig. 4. The designated lower data Q < M > -Q <0> in the first sub-period T1 is reordered according to a rule that the weight is from low to high, resulting in the reverse data Q <0> -Q < M >. It can be understood that the original weight of the lower data Q [ M:0] is ordered from high to low but the reverse data is Q [0: M ] if it is reordered according to a rule that the weight is from low to high. Taking the lower data of the eight-bit data 01001010 as an example, its weight is from high to low, but if reordered according to a rule of low to high weight, so-called reverse order data 01010010 may result. Taking the four-bit low-order data 1010 as an example, its original weight is from high to low but if it is reordered according to the rule of weight from low to high, the reverse order data 0101 is obtained. According to the reverse rule, the low-order data Q < M >, Q < M-1>, Q < M-2>, … … Q <0>, that is, Q [ M:0], are reordered from low to high according to the weight rule to obtain the reverse data Q <0>, Q <1>, Q <2>, … … Q < M-1>, and Q < M > is denoted as Q [0: M ].
Referring to fig. 15, the data comparator CMP10 provided with the corresponding first pulse width modulation module PWM1 at the first sub-period T1 compares the gradation data R [ M:0] matched to the red light emitting diode paired with the PWM1 with the reverse order data Q [0: M ] within the first sub-period T1: this results in the first PWM signal DR having an active logic value, e.g., a high level, when the reverse data Q [0: M ] is lower than the gray data R [ M:0] of the red light source, otherwise the first PWM signal DR has a low level of an inactive logic. Since the reverse data Q [0: M ] does not grow from small to large as the low-order data does, the reverse data Q [0: M ] may appear to have a large value or a small value as time goes by. In other words, as the clock signal CK1 is counted by as few as possible, the reverse data Q [0: M ] may be higher than the gray data of the red light source and lower than the gray data of the red light source, so that the effective logic values of the first pulse width modulation signal DR in the corresponding first sub-period T1 naturally appear to be distributed discretely.
Referring to fig. 15, the data comparator CMP20 provided with the corresponding second pulse width modulation module PWM2 in the second sub-period T2 compares the gradation data G [ M:0] matched to the green led paired with the PWM2 with the reverse order data Q [0: M ] in the second sub-period T2: this results in the second pwm signal DG having an active logic value, e.g., a high level, when the reverse data Q [0: M ] is lower than the gray data G [ M:0] of the green light source, otherwise the second pwm signal DG has a low level of inactive logic. With the clock signal CK2 being counted by as few as possible, the reverse data Q [0: M ] may be higher than the gray data of the green light source and lower than the gray data of the green light source, and the effective logic value of the second pulse width modulation signal DG naturally appears as a discrete distribution in the second sub-period T2.
Referring to fig. 15, the data comparator CMP30 provided with the corresponding third pulse width modulation module PWM3 in the third sub-period T3 compares the gray data B [ M:0] matched to the blue led paired with the PWM3 with the reverse data Q [0: M ] in the third sub-period T3: this may result in the third pulse width modulation signal DB having an active logic value such as a high level when the reverse order data Q [0: M ] is lower than the gray scale data G [ M:0] of blue emission, otherwise the third pulse width modulation signal DB is a low level of inactive logic. With the clock signal CK3 counted by as few as or as many as possible, the reverse data Q [0: M ] may be higher than the gray data of the blue light source and the gray data of the blue green light source, and the valid logic values of the third pulse width modulation signal DB in the third sub-period T3 naturally appear as a discrete distribution.
Referring to fig. 15, according to this embodiment, the effective logic values of the first pwm signal DR in T1, the effective logic values of the second pwm signal DG in T2, and the effective logic values of the third pwm signal DB in T3 may be arranged in a distributed/discrete manner. The discrete waveform of the pulse width modulated signal is similar to that of figure 14 but the implementation mechanism is different.
Referring to FIG. 15, an alternative example of a driving circuit includes one of the pulse width modulation modules PWM1-PWM3, such as PWM1, for generating a corresponding pulse width modulation signal, such as DR, based on gray scale data, such as R [ M:0], matched by a light emitting diode, such as a red light source. Claim to truncate PWM2-PWM3 and truncate blue and green light sources. A pulse width modulated signal such as DR may be used to drive the red light source for display control. The pulse width modulation module PWM1 is configured with a counter, such as CNT in the figure, and a data comparator, such as CMP10 in the figure. In this example there is only the first time period T1 but no second and third time periods and the cycle period T is assumed to be T1. The counter is triggered to count by a clock signal, such as CK1, and obtains a count Q [ M:0] for a first time period T1. The original count value Q [ M:0] is reordered according to a rule that the weight is from low to high to obtain the reverse data Q [0: M ]. The pulse width modulation module PWM1 sends the gray data R [ M:0] matched with the light source and the inverted data Q [0: M ] to the data comparator CMP10 for comparison: after comparison, the pulse width modulation signal DR is at a high logic level when the reverse data Q [0: M ] is lower than the gray data R [ M:0], otherwise the pulse width modulation signal DR has a low logic level of non-significance. The count value is also called count data. The active logic value now appears as a number of discrete high levels.
Referring to fig. 16, according to the embodiment of fig. 15, assuming that the number of clocks of the clock signal CK2 in the second sub-period T2 is 256 from 0 to 255, that is, the preset value of the clock signal in the second sub-period T2 is 256, M is 7 and 256 times are counted in total per sub-period, and the gradation data has the reverse data Q [0:7] of the comparison object. In the first embodiment, when the gray scale data of the green light source is G [7:0] ═ 00000010, the actual waveform of the second pwm signal DG1 is as shown in the figure, and the second pwm signal has an effective logic value only when Q [0:7] ═ 00000000 or Q [0:7] ═ 00000001, and Q [0:7] has a total of 256 values, and Q [0:7] has no less than G [7:0] in the case of the remaining 254 values of Q [0:7], so that the second pwm signal has an ineffective logic value. In the second embodiment, when the gray scale data of the green light source is G [7:0] ═ 00011101, the second pwm signal DG2 is active logic value when Q [0:7] is lower than G [7:0] and otherwise the second pwm signal is inactive logic value. In the third embodiment, when the gray scale data of the green light source is G [7:0] ═ 01001111, the second pwm signal DG3 is active logic value when Q [0:7] is lower than G [7:0] and otherwise the second pwm signal is inactive logic value. In the fourth embodiment, when the gray scale data of the green light source is G [7:0] ═ 01111111, the second pwm signal DG4 is active logic value when Q [0:7] is lower than G [7:0] and otherwise the second pwm signal is inactive logic value. In the fifth embodiment, when the gray scale data of the green light source is G [7:0] ═ 11101000, and Q [0:7] is lower than G [7:0], the second pwm signal DG5 is active logic value, and otherwise the second pwm signal is inactive logic value. According to this embodiment, the effective logic values of the second PWM signals DG1-DG5 generated by the second PWM module PWM2 appear as discrete distributions in the corresponding second sub-time period T2.
Referring to fig. 17, each pwm module outputs a dither signal having a valid logic value once every several cycles, so that the average value of the duty ratio of each pwm signal is adjusted by the dither signal in several cycles. For example, the pulse width modulation module PWM1 outputs the dither signal RD as a valid logic value once every time TX, which is equal to a number of cycle periods T, for example, time TX, which is equal to 4 or 8 or 16 cycle periods T. The DITHER technique is attributed to the functionality of the DITHER-type digital pulse width modulation DPWM. The pulse width modulation module PWM2 outputs the dither signal GD at a valid logic value once every time TX, and the pulse width modulation module PWM3 outputs the dither signal BD at a valid logic value once every time TX. Therefore, the average value of the duty ratio of each pulse width modulation signal in a plurality of cycle periods is adjusted by the jitter signal. The average value of the duty ratio of the first pulse width modulation signal DR in the time TX is adjusted by the jitter signal RD, the average value of the duty ratio of the second pulse width modulation signal DG in the time TX is adjusted by the jitter signal GD, and the average value of the duty ratio of the third pulse width modulation signal DB in the time TX is adjusted by the jitter signal BD.
Referring to fig. 17, the above is that the valid logic values of each pwm signal in a corresponding one of the sub-periods are arranged in a continuous manner. For example, the valid logic values in the examples of fig. 5-7 and 13 are arranged in a sequential manner. When any pulse width modulation module outputs a jitter signal: if the effective logic values of the pwm signals are arranged in a continuous manner, the dither signal is output immediately after the effective logic values of the pwm signals generated by any one of the pwm modules are finished. In an alternative example, when the effective logic value RH of the first PWM signal DR in T1 is over, the PWM module PWM1 outputs the jitter signal RD immediately after the effective logic value RH of the first PWM signal DR is over, the jitter signal RD is also distributed in the first sub-period T1, and the time length of the jitter signal RD may be equal to the period time of one clock signal CK1 itself. In an alternative example, the pulse width modulation module PWM2 outputs the jitter signal GD immediately after the end of the effective logic value GH of the second PWM signal DG at the end of the effective logic value GH in T2, where the jitter signal GD is distributed in the second sub-period T2 and the time length of the jitter signal GD is set to be equal to the cycle time of one clock signal CK 2. When the effective logic value BH of the third PWM signal DB in T3 is over, the PWM module PWM3 outputs the jitter signal BD immediately after the effective logic value BH of the third PWM signal DB is over, and the jitter signal BD is distributed in the third sub-period T3, where the time length of the jitter signal BD is equal to the cycle time of one clock signal CK 3. In an alternative example there is a predefined number of cycle periods T within the time TX. In the example of fig. 17, the jitter signal is present only in the first cycle period T within the time TX and the remaining other cycle periods T do not output any jitter signal.
Referring to fig. 18, each pwm module outputs a dither signal having a valid logic value once every several cycles, so that the average value of the duty ratio of each pwm signal is adjusted by the dither signal during several cycles. For example, the pulse width modulation module PWM1 outputs the dither signal RD as a valid logic value once every time TX, which is equal to a number of cycle periods T, for example, time TX, which is equal to 4 or 8 or 16 cycle periods T. The PWM module PWM2 outputs the dither signal GD with an effective logic value once every time TX, and the PWM module PWM3 outputs the dither signal BD with an effective logic value once every time TX. Therefore, the average value of the duty ratio of each pulse width modulation signal in a plurality of cycle periods is adjusted by the jitter signal. For example, the average value of the duty ratio of the first pwm signal DR in the time TX is adjusted by the jitter signal RD, the average value of the duty ratio of the second pwm signal DG in the time TX is adjusted by the jitter signal GD, and the average value of the duty ratio of the third pwm signal DB in the time TX is adjusted by the jitter signal BD. Fig. 18 is a pulse width modulation signal combined dither signal of an effective logic value discrete type, and in contrast, fig. 17 is a pulse width modulation signal combined dither signal of an effective logic value continuous type.
Referring to fig. 18, the above is that the valid logic values of each pwm signal in a corresponding one of the sub-periods are arranged in a scattered or discrete manner. The valid logic values are arranged in a discrete manner as in the examples of fig. 12 and 14-16. When the pulse width modulation module outputs a jitter signal: if the effective logic values of the pulse width modulation signals are distributed in a dispersed mode, the jitter signal is output immediately after the end of the last effective logic value in the pulse width modulation signals generated by the pulse width modulation module. The first PWM signal DR has a plurality of effective logic values RH in T1, and the PWM module PWM1 outputs the jitter signal RD immediately after the end of the last effective logic value RH of the first PWM signal DR, the jitter signal RD is distributed in the first sub-period T1, and the time length of the jitter signal RD may be set to be equal to the cycle time of one clock signal CK 1. In an alternative example, the second PWM signal DG has a plurality of valid logic values GH in T2, and the PWM module PWM2 outputs the jitter signal GD immediately after the last valid logic value GH of the second PWM signal DG is over, the jitter signal GD is distributed in the second sub-period T2, and the time length of the jitter signal GD is set to be equal to the period time of one clock signal CK 2. The third PWM signal DB has a plurality of effective logic values BH in T3 and the PWM module PWM3 outputs the dither signal BD immediately after the end of the last effective logic value BH of the third PWM signal DB it generates, the dither signal BD being distributed in the third sub-period T3 and being settable to have a time length equal to the period time of one clock signal CK 3. In the embodiment of fig. 18, the jitter signal is present only in the first cycle period T within the time TX, and no jitter signal is output in the remaining other cycle periods within the time TX. Dithering techniques allow a greater number of colors to be simulated with a smaller number of colors.
Referring to fig. 19, the core function of the current source module PCS is to provide high accuracy and stable output current to the target object with constant current requirement. The current source module PCS is explained for the moment with a circuit architecture based on a linear regulator as an alternative embodiment. The power adjusting transistor of the constant current source part of the current source module PCS mainly works in a linear state or a non-switch state. The power adjusting transistor TQ has a first terminal, a second terminal and a control terminal, and if the power adjusting transistor is a mosfet, three terminals of the power adjusting transistor are generally called a drain, a source and a gate control terminal, and if the power adjusting transistor is a bjt, three terminals are generally called a collector, an emitter and a base control terminal. The power adjusting transistor TQ has a first terminal coupled to the power receiving terminal VI and a second terminal coupled to the node NT where the voltage is sampled. The voltage at the node NT is sampled by a feedback network and the first terminal receives the input voltage and the potential reference terminal VR or reference ground is the current output terminal of the constant current source. The resistors R1 and R2 connected in series between the node NT of the sampled voltage and the potential reference terminal VR belong to a feedback network, also called feedback resistor, and the interconnection node ND of the two is regarded as the voltage feedback node of the feedback network. The feedback voltage provided at the interconnection node ND is coupled to the inverting terminal of the error amplifier AP, and the reference voltage VB0 provided by the bandgap reference BG0 is provided to the positive terminal of the error amplifier AP. The error amplifier AP compares and amplifies the reference voltage VB0 with the feedback voltage at the feedback node while the output of the error amplifier AP is also coupled to the control terminal of the power adjusting transistor TQ and operates the power adjusting transistor in the linear region. Thereby maintaining the voltage at the node NT stable. A load resistor RL is connected between the potential reference terminal VR and the node NT based on a requirement for forming a stable output current. The voltage across the load resistor RL is determined and the current flowing through it is also determined, according to which it is ensured that the current flowing at the potential reference terminal VR is a constant current and meets the requirement that the constant current source can provide a stable output current. The voltage stabilizing diode ZD with the negative pole connected to the power receiving end VI and the positive pole connected to the potential reference end VR plays the role of overvoltage protection.
Referring to fig. 19, the constant current source including the power adjusting transistor TQ, the error amplifier AP, the load resistor RL and even the feedback network already has the capability of providing a stable output current, and if the current source module is simply constructed by this circuit, it is not doubtful that the output current from the constant current source is fixed and difficult to be modified online. Attempting to flexibly adjust the output current of the constant current source requires either changing the resistance value of the resistor R1 or R2 in the feedback network or changing the resistance value of the load resistor RL or changing the voltage value of the supply reference voltage VB 0. Considering that the actual application scenario of the current source module PCS is often a circuit board or a similar component carrier, directly replacing components on the carrier has the disadvantages of complex operation, high cost and the like. Instead of a constant current source with a fixed output current, a programmable constant current source should preferably be designed in a mode in which the output current is adjustable, so that the output current from the constant current source is not fixed any more but can be programmed online. When the current source module PCS is designed as a current source chip in the form of an integrated circuit, the action of changing the parameters of the components inside the integrated circuit chip is more complicated. In addition, a data transmission module DAT2 is provided for the current source module PCS, which has a decoder and can decode the input serial data according to a predetermined communication protocol, and the data transmission module DAT2 decodes the current adjustment data from the received communication data, so that the current source module PCS can adjust the magnitude of the output current of the programmable constant current source on line according to the current adjustment data. The meaning of the current regulation data is to change the magnitude of the output current of the constant current source, typically, the resistance of the resistor R1 or R2 in the feedback network can be adjusted according to the current regulation data, and the voltage value of the reference voltage VB0, even the resistance of the load resistor RL, can be adjusted according to the current regulation data. Any such on-line adjustment or programming causes the magnitude of the output current from the constant current source to be adjusted.
Referring to fig. 19, although the current source module PCS uses a linear modulator structure as an illustrative example, the circuit structure of the current source module PCS is not unique in nature, and any current source module capable of providing a stable output current can be used as an alternative to maintain the total input current of the driving circuit at a predetermined value. For example, a three-terminal programmable shunt regulator may be applied in the alternative to the current source module PCS: the power adjusting transistor TQ uses a bipolar junction transistor and removes a bandgap reference source, a feedback network and an error amplifier AP, a resistor which is not shown is connected between a first end and a control end of the power adjusting transistor TQ, a cathode of the three-terminal programmable parallel regulator is connected to the control end of the power adjusting transistor, an anode of the three-terminal programmable parallel regulator is connected to a potential reference end VR, and a reference end of the three-terminal programmable parallel regulator is connected to a node NT position shown in the figure. The load circuit RL sets the constant current source in a mode in which the output current is fixed without trimming. If the data transmission module DAT2 is used to fine-tune the resistance value of the load circuit RL, the programmable constant current source is alternatively set in a mode in which the output current is adjustable. The current source module PCS is again such as in other alternative types: the power adjusting transistor TQ is a bipolar junction transistor and directly removes a band gap reference source and an error amplifier, the cathode of the three-terminal programmable shunt regulator is connected to the control end of the power adjusting transistor, the anode of the three-terminal programmable shunt regulator is connected to a potential reference end VR, a resistor which is not shown in the figure is connected between the first end and the control end of the power adjusting transistor TQ, and the reference end of the three-terminal programmable shunt regulator which is not shown in the figure is connected to a node ND in a reserved feedback network. If the data transmission module DAT2 is used to finely adjust the resistance value of the resistor R1 or R2 having a series relationship in the feedback network, or even the resistance value of the load circuit RL, the programmable constant current source is alternatively set in a mode in which the output current is adjustable. The constant current source of the alternative current source module PCS is based on a bipolar junction transistor, a three-terminal programmable shunt regulator, a load circuit RL and a feedback network. It will be readily appreciated that the solutions mentioned for the current source module with a constant current source or the current source chip with a constant current source are versatile, as long as they produce an output current which is capable of maintaining the total input current of the driver circuit at a predetermined value or within a predetermined range.
Referring to fig. 20, the current source module PCS does not need the data transmission module DAT2 for communication at all if the constant current source is set in the mode in which the output current is fixed, whereas the data transmission module DAT2 is indispensable if the programmable constant current source is set in the mode in which the output current is adjustable. Both the case where data needs to be forwarded and the case where data does not need to be forwarded exist for the data transmission module DAT1-DAT 2. The PCS can receive communication data independently under the condition of not needing to forward data, and can participate in the cascade relation with the driving circuit under the condition of needing to forward data. In an alternative embodiment, the decoder 210 and the data forwarding module 220 are provided as an example to explain the working mechanism of the data transmission module for receiving the communication data and forwarding the data. The signal input terminal DI receives communication data provided from outside, and a typical data transmitting terminal such as a server or a microprocessor can output communication data conforming to the precoding rule. The decoder 210 decodes or decodes the data information carried in the communication data. Communication data encoded using, for example, manchester encoding and decoding techniques or return-to-zero encoding and decoding techniques, requires that the data in these formats be correctly decoded by the decoder 210. The data transmission module can be also regarded as a serial interface or a serial interface circuit. The significance of data decoding is that data with a pre-coded format that cannot be directly recognized can be reduced to the most conventional binary codes that are easily recognized and implemented, such as manchester codes that characterize a1 or 0 in high and low level transitions and return-to-zero codes that differ by a time width of a high level by a1 or 0. The decoded binary code is temporarily stored in the register 230. in view of the faster data refresh rate of the register 230, additional buffer space or latches 250 are often used to store the decoded data during updates. The decoding process of the communication data can select to detect an ending instruction code or a reset instruction in the data to judge whether the data is transmitted and received. Taking the return-to-zero code as an example, the reset instruction is represented by a long low level with a long duration, the return-to-zero code has a coding cycle time which is defined in advance no matter 1 code or 0 code, but the duration of the high level of the return-to-zero code is different in the coding cycle time, and the time length of the reset instruction is far longer than the single coding cycle time of the conventional 1 code and 0 code. A long low detection circuit, not shown, may be used to monitor the long low representing the RESET command RESET, which occurs to RESET the current source block and use the current adjustment data from latch 250 to trim and write the resistance value of resistor R2.
Referring to fig. 20, the number of the symbol bits of the current adjustment data of the correction resistor R2 is a natural number U, which is equivalent to selecting U number of trimming resistors RA0-RAU in series in the series of trimming resistors and equivalent to the resistor R2. A selection switch is connected between two ends of each selected trimming resistor, so that each trimming resistor is connected in parallel with one selection switch, for example, two ends of each trimming resistor are respectively connected in parallel with selection switches BS 0-BSQ. The current regulation data B < U > to B <0> are used to control whether the selection switch connected in parallel with each trimming resistor is turned on or not, respectively. Assuming as an example that B < U > is 1, the parallel selection switch BSU of the trimming resistor RAU controlled by the symbol is turned on and causes the resistance of the resistor R2 to decrease. As another alternative example, assuming that B <1> is 0, the parallel switch BS1 of the trimming resistor RA1 controlled by the symbol is turned off so as to cause the total resistance of the resistor R2 to increase. The current regulation data may cause the magnitude of the output current drawn by the constant current source to be adjusted by altering the resistance value of the resistor R2. For the same reason, it is easy to understand that the resistance value of the resistor R1 can be alternatively changed by using the current regulation data even though the voltage value of the reference voltage VB0 is changed by using the binary current regulation data, which is not shown in the figure, so as to adjust the magnitude of the output current flowing from the constant current source.
Referring to fig. 20, it is described that the current source module PCS and the driving circuit are allowed to be cascade-connected to transfer communication data based on a single-wire communication protocol as the simplest communication scheme. Manchester encoding belongs to phase encoding and characterizes 1 or 0 in the presence of high and low level jumps in each data encoding period, while return-to-zero codes represent 1 code with a longer high level duration and 0 code with a shorter high level duration in each encoding period, which are often applied to the encoding and decoding of single-wire communication protocols but not the only encoding and decoding schemes. For example, it is possible to distinguish even a 1-code or a 0-code by the difference in the number of occurrences of a high level in a single coding period, indicating 1 if the high level occurs twice, and indicating 0 if the high level occurs once, and thus, any protocol conforming to a single-wire communication capable of communicating data using a single data line can be applied to the present application. The data regeneration or data forwarding functions are performed in the current source module PCS by the data forwarding module 220, which performs data transmission tasks such as transmitting communication data to the subsequent driver circuit. The simplest forwarding mode of the data forwarding module 220 is transparent transmission, that is, allowing it to forward and output the communication data received from the signal input terminal DI directly from the signal output terminal DO, and then the driving circuit or the current source module PCS connected in cascade are respectively and respectively extracted from the single data line according to the address allocation rule to the communication data corresponding to its own address and belonging to itself. However, in practical applications, the number of cascaded driving circuits is extremely large, symbol errors are easily generated in long-distance data transmission, parameters such as parasitic or load capacitance existing in input and output ports of data signals inevitably induce transmission data to be attenuated, and the cascade attenuation effect is accumulated. In addition, the number of pixel points required by the display system itself is very large, so that the situation of data distortion is more serious as more chips are cascaded, and even the chips cannot normally identify the code elements, so that the number of the chips in cascade is limited. Instead of the first forwarding path Sel1 of transparent transmission, it is necessary to count whether the total number of bits of the current adjustment data B <0> to B < U > belonging to the current source module PCS is completely received, and the implementation means of counting the number of bits is various, such as using a counter is the most common. As soon as the current control data belonging to the current source module PCS are decoded and completely received by it, an active enable signal ENB is generated, which, if active high, triggers the data forwarding module 220 to enable the data forwarding function and to forward the communication data received at the signal input DI out of its signal output DO, in which case the data forwarding module 220 acts as a switch to determine whether the received communication data are allowed to be output. In addition to the data forwarding module 220 acting as a switch, the data forwarding module 220 should actually reconstruct each bit to solve the concern of the data cascade attenuation effect so that the transmission loss is modified to restore the standard transmission code. Still taking the return-to-zero code as an example, in view of the problem that there is partial loss in the high level retransmission of each bit, for example, if the data forwarding module 220 detects that the bit of the 1 code has a too short high level time, it may appropriately extend the high level time of the 1 code to be recognizable, and if the bit of the 0 code has a too short high level time, it may appropriately extend the high level time of the 0 code, but this extension operation cannot cause the high level time to be excessively extended to prevent erroneous recognition as the 1 code. The data forwarding module 220 may thereby reconstruct the bits of each return-to-zero code format back to the standard transmission encoding. The data forwarding module 220 should be able to reconstruct each bit, regardless of the predetermined encoding format of the communication data, so that the transmission loss of each bit is modified to recover the standardized transmission code conforming to the predetermined encoding format, which is easy to recognize. The counter 260 may be used to count whether the total number of bits of the current adjustment data B <0> to B < U > is completely received, and the counter 260 generates an enable signal ENB when the current adjustment data belonging to the current source module is decoded and completely received.
Referring to fig. 20, the second forwarding path Sel2 is slightly different from the first forwarding path Sel1 in that the communication data is decoded by the decoder 210 of the data transmission module DAT2 in advance, and the data forwarding module 220 acts as a switch to determine whether to allow the decoded data to be forwarded under the condition of being controlled by the enable signal ENB, in which case decoding and data reconstruction are almost completed synchronously. A local clock circuit, not illustrated by data transmission module DAT2, provides a number of clock signals having a predetermined number that can be used to detect the length of time that the high level of each return-to-zero code bit is high. Considering that the duration of the high level of the 1 code in each coding cycle time is longer than the duration of the high level of the 0 code, the decoding process may detect the length of the high level time in each coding cycle time by using a predetermined number of clock signals, and if the high level of the return-to-zero code bit is ended earlier than before the predetermined number of clock signals are ended, the decoding result is the 0 code, whereas if the high level of the return-to-zero code bit is not ended yet after the predetermined number of clock signals are ended, the decoding result is the 1 code. The decoder 210 outputs reconstruction data in addition to visually reflecting the decoding result: when the rising edge of the high level of the return-to-zero bit of the communication data comes, the serial clock signals with the predetermined number are triggered to start sampling the bit, and when the high level of the return-to-zero bit is sampled by the first clock signal in the serial clock signals with the predetermined number, the decoder 210 starts outputting the high level and is forwarded by the data forwarding module 220. The designated clock signal with determined ordering, for example, the clock signal with the second ordering, is selected from the series of clock signals with a predetermined number to continue to sample the high level of the return-to-zero code bit, if the designated clock signal with determined ordering is sampled to the low level, the decoder 210 starts to switch from the output high level to the output low level and the output is synchronously forwarded by the data forwarding module 220, and if the designated clock signal with determined ordering is sampled to the high level, the decoder 210 still outputs the high level and is forwarded by the data forwarding module 220. The end of the predetermined number of clock signals in the series triggers decoder 210 to return to an output low level and to be forwarded low by data forwarding module 220 regardless of whether the return-to-zero code bit is high or not. Through the explanation of decoding and data reconstruction, the data forwarding is equivalent to that the input data is decoded and re-encoded and then forwarded, and the communication data is completely recovered into encoded data with a preset encoding format under the sampling of the clock resource of the data transmission module and transmitted to a data receiver cascaded with the data receiver.
Referring to fig. 20, slightly different from the first forwarding path Sel1 and the second forwarding path Sel2, an alternative implementation of data forwarding is a re-encoding technique, i.e., a third forwarding path Sel 3. The data transmission module DAT2 achieves the re-encoding purpose to utilize the encoder 240 additionally configured. Completely different from the foregoing forwarding modes, after being decoded, the communication data is temporarily stored in the storage space of the data transmission module DAT2, and then the encoder 240 capable of re-encoding the binary data re-encodes and outputs the temporarily stored data, and the relay function of decoding and storing the data and re-encoding and outputting the data according to the predetermined encoding format ensures that the data can be transmitted smoothly. The aim of the data trimming or shaping means of any forwarding path is to forward the trimmed correct data to the lower-level data receiver, so as to ensure that the communication data is not distorted in the transmission and forwarding stage, the aforementioned data transmission attenuation distortion does not reduce the cascade connection number of the data receivers on the single-line transmission line of the toggle, and the data receivers can be in infinite cascade connection theoretically by leaving aside the data refresh rate factor. It should be emphasized that although the communication data transfer process is described by way of example as a single-wire communication, substantially alternative multi-wire communication is also applicable to the present application for transferring the communication data to the current source module PCS and the driving circuit. The display technology is generally used for realizing the transmission of cascade signals by adopting four or other transmission lines, a clock signal line, a data signal line, a loading signal line and an output enabling signal line work simultaneously, communication data are sequentially transmitted in series respectively, and the control of each cascade data receiver is realized by the matching of four-line signals. A communication protocol using three lines in total, a data line and a clock line, and a latch line, is also the mainstream communication scheme of the display technology. When the pixel pitch is larger, double-line transmission is adopted, and the double-line transmission of a data line and a clock line is the compromise between the number of the data lines and the transmission rate. The universal two-wire protocols such as IIC and SMBUS require parallel connection of slaves and the advantage of the single-wire protocol is that only a single signal wire is needed for data transmission. The first to third forwarding paths Sel1-Sel3 and so-called transparent transmission or even multi-line communication may optionally have one of them as a communication scheme of the data transmission modules DAT1-DAT 2. If the serial cascade signals are connected with all the data receivers in sequence by adopting a single cascade transmission line, the transmission process of the cascade signals is simpler without considering the time sequence cooperation of the cascade signals, the transmission failure rate is low, the use amount of cables is reduced, and the cost is saved.
Referring to FIG. 21, a K-level driver circuit or device is illustrated as a cascade of driver chips IC1 through ICK (natural number K ≧ 1). The data transmitting end transmits communication data GSD to each level of driving chips, the data transmitting end can use a server or a microprocessor MCU or other similar data transmitting ends, and the driving chips are also called display control chips.
Referring to fig. 21, the cascade drive circuits are arranged in one or more columns in the power supply path. The first driver circuit IN each column, e.g., driver chip IC1, is coupled to the positive supply terminal IN of VCC and the last driver circuit IN each column, e.g., driver chip ICK, is coupled to the negative supply terminal OUT of VCC. The power supply input of the following driver circuit is also arranged in each column to be coupled to the potential reference of the preceding driver circuit. IN an alternative example, the power supply input terminal IN of the succeeding driver chip IC2 is coupled to the potential reference terminal OUT of the adjacent preceding driver chip IC1, and the power supply input terminal IN of the succeeding driver chip IC3 is coupled to the potential reference terminal OUT of the preceding driver chip IC2, etc., which are disposed, for example, IN the first column CL 1. The power supply is repeated until the power input terminal IN of the last driver circuit at the column tail, e.g., driver chip ICK, is coupled to the potential reference terminal OUT of its neighboring previous driver circuit, i.e., the K-1 th driver chip, etc. The cascade drive circuit couples the power input end of the rear drive circuit to the potential reference end of the adjacent front drive circuit in each column in power supply relation until all the drive circuits in each column are connected in series or superposed between the positive pole and the negative pole of the power supply or connected in series between the positive pole and the ground end of the power supply. A capacitor CZ may be provided between the power input terminal IN and the potential reference terminal OUT of each driver circuit as a voltage stabilization option. Therefore, the total output current of the previous driving circuit in each row can be regarded as the total input current of the adjacent subsequent driving circuit. In an alternative example a current source module PCS is provided on the supply lines of each column of driver circuits, e.g. IC1-ICK, to maintain the total input current of each driver circuit in this column at a predetermined value. IN the first column CL1, a driving circuit such as IC1-ICK and a current source module PCS are connected IN series between the positive pole and the negative pole of the power supply, and the power input terminal IN of the driving chip IC1 is not directly coupled to the positive pole of the power supply but indirectly coupled to the positive pole of the power supply through the current source module PCS. The power receiving terminal VI of the current source module is connected to the positive terminal of the power VCC, and the potential reference terminal VR is connected to the power input terminal IN of the driver IC 1. The total input current of any one of the driving circuits in each row is equal to the output current of the current source module.
Referring to fig. 21, at the stage that the previous frame of communication data received by each driving circuit is refreshed to the next frame of communication data to adjust the respective gray scale data of the multiple light emitting diodes, the current adjustment data received by the current source module PCS is also refreshed by frames so that the output current of the current source module PCS is also refreshed by frames and flows to the driving circuits, and the total input current of each driving circuit is updated from the preset value corresponding to the current adjustment data of the previous frame to the preset value corresponding to the current adjustment data of the next frame. Note that the current adjustment data of the previous frame is decoded from the communication data of the previous frame and the current adjustment data of the next frame is decoded from the communication data of the next frame. The foregoing technical features describe the driver circuit and the current source module PCS in a column as a basic unit, and it is also permissible to configure the current source module PCS and the driver circuit not in a column basic unit. A typical application of a single driver circuit and its current manager current source module PCS combination as a single pixel or point source is a breathing lamp. Therefore, whether a single driving circuit or a row is used as a basic unit, the current regulation data received by the current source module PCS are refreshed according to frames, and the total input current of the driving circuit is updated from the preset value corresponding to the current regulation data of the previous frame to the preset value corresponding to the current regulation data of the next frame. Even if a single current source module PCS is matched with a single driving circuit as a point light source, the current flowing out of the current source module PCS is still equal to the total input current of the driving circuit. Further, IN the present embodiment, the plurality of driving circuits are connected IN series to form a column, and it is an alternative embodiment if the plurality of driving circuits are arranged IN parallel, that is, the power input terminal IN of each driving circuit is coupled to the positive electrode of the power source VCC, and the potential reference terminal OUT of each driving circuit is coupled to the negative electrode GND of the power source, but IN this case, the power voltage is adaptively reduced to satisfy the degree of withstand voltage of the driving circuits.
Referring to fig. 21, the foregoing solves the power supply problem of the cascade driver IC 1-ICK. In the multi-stage driving circuit, the signal input end of the rear stage driving circuit is coupled to the signal output end of the front stage driving circuit. Typically, for example, the signal input terminal DI of the rear driver IC2 is coupled to the signal output terminal DO of the front driver IC1, and the signal input terminal DI of the rear driver IC3 is coupled to the signal output terminal DO of the front driver IC2, and so on in a single-wire communication manner: the signal input terminal DI of the last stage in the cascade connection relationship, e.g., the driver chip ICK, is coupled to the signal output terminal DO of its adjacent previous stage driver circuit, e.g., the K-1 th stage driver chip. It will be appreciated from the description of this embodiment that each frame of communication data is transferred from the head of the column to the tail of the column, i.e., from the IC1 to the ICK. The signal input terminal of the optional post-stage driving circuit can be coupled to the signal output terminal of the pre-stage driving circuit through a coupling capacitor C. For example, the signal input terminal DI of the rear driver IC2 may be configured to be coupled to the signal output terminal of the driver IC1 through a capacitor C, and the signal input terminal DI of the driver IC3 may be configured to be coupled to the signal output terminal of the driver IC2 through a capacitor C. The signal input end DI of the current source module PCS with data forwarding function receives communication data, and the signal output end DO of the current source module PCS forwarding data is coupled to the signal input end DI of the primary driver IC1 through a capacitor C. The current source module and the driving circuit with data forwarding function can both forward communication data to the opposite party.
Referring to fig. 21, the cascade driver IC1-ICK is transferred in serial data from the head of a column to the tail of the column, i.e., serial data is first given to the IC1, the second IC2, the third IC3, and then to the last IC 3. This direction of transferring serial data may also be modified to: serial data is first given to the ICK at the end of the column, second to the second last driver chip at level K-1 and third to the third last driver chip at level K-2 until finally to IC 1. At this point, serial data is considered to be transferred in reverse from the tail of the column to the head of the column, i.e., from the ICK to the IC 1. Therefore, the connection relationship between the signal transmitting and receiving ends in fig. 21 needs to be modified as follows: the signal input terminal DI of the last driving chip IC1 is coupled to the signal output terminal DO of the previous driving chip IC2, the signal input terminal DI of the next driving chip IC2 is coupled to the signal output terminal DO of the previous driving chip IC3, and so on, until the single-wire communication, the signal output terminal DO of the first stage, e.g., the driving chip ICK, in the cascade relation is coupled to the signal input terminal DI of the next driving circuit, i.e., the K-1 stage driving chip. The signal input DI of the current source block is coupled to the signal output DO of the final driver chip IC1 through a capacitor C. It can be understood from the description of this embodiment that each frame of gray data is transferred from the end of the column to the head of the column. And the signal input end of the rear stage driving circuit can be coupled to the signal output end of the front stage driving circuit through a coupling capacitor. Whether serial data is transferred from the head of a column to the tail of a column or from the tail of a column to the head of a column among the driver chips IC1-ICK, their column driver circuits may be arranged to be connected IN series with a current source block PCS that provides a constant current source, which maintains the current flowing from the power supply input terminal IN of each driver chip among the driver chips of the column of IC1-ICK to the potential reference terminal OUT thereof at a predetermined value. The specific position of the current source module can be adjusted from the power input end of the IC1 of the IC1-ICK to the position between the potential reference end of the ICK and the power negative pole, the power receiving end VI of the current source module is connected to the potential reference end OUT of the driving chip ICK, and the potential reference end VR of the current source module is connected to the power negative pole GND. Or the current source module is arranged between any two adjacent driving chips in each column of driving chips, namely between the potential reference terminal of the previous driving chip and the power input terminal of the adjacent next driving chip, for example, the power receiving terminal VI of the current source module is connected to the potential reference terminal of the driving chip IC2 and the potential reference terminal VR of the current source module is connected to the power input terminal of the driving chip IC 3.
Referring to fig. 21, the foregoing describes a single column of cascaded driver chips IC1-ICK to characterize a cascade of connected multi-stage driver circuits, but in practice a display system constructed with multiple columns of driver chips may display more complex content. The multi-level driver circuit is arranged in a plurality of columns and the second column driver chip CL2 is part of the multi-level driver circuit in addition to the first column CL1 of the driver chips IC1-ICK, limited by space limitations not shown in more columns. In essence the cascaded multi-stage drive circuit can be divided into more columns than the two columns shown, just as an example two columns. The second column driver chip CL2 and the first column driver chip CL1 do not have a great difference in power supply and communication, and therefore, it is not described in detail but should be emphasized that each driver circuit in the second column driver chip CL2 is connected in series with a plurality of current source modules PCS providing constant current sources. The current source module PCS maintains the current flowing from the power supply input terminal IN of each of the second column driver chips CL2 to the potential reference terminal OUT thereof at a predetermined value. The specific position of each current source module can be between the power supply input end of the IC1 of the IC1-ICK and the positive electrode of a power supply or between the potential reference end of the ICK and the negative electrode of the power supply, or the current source module is arranged between any two adjacent driving chips in the second column of driving chips, namely between the potential reference end of the previous driving chip and the power supply input end of the next driving chip.
Referring to fig. 21, the first column driver chip CL1 and the second column driver chip CL2 are part of a whole cascade driver circuit, and serial data needs to be transferred from the first column driver chip to the second column driver chip or from the second column driver chip to the first column driver chip. Each frame of communication data may be transferred from the head or tail of a column of any one of the column driver circuits to the head or tail of another column driver circuit. Each frame communication data is transferred from a column head of the first column driving chip CL1 such as the driving chip IC1 to the column head driving chip IC1 of the second column driving chip CL2 or may be transferred to the column tail driving chip ICK of the driving chip CL2 of the second column. The signal output terminal of the driver chip IC1 of the first column driver circuit CL1 is coupled to the signal input terminal of the driver chip IC1 of the second column driver chip CL2 or the signal output terminal of the column head driver chip IC1 of the first column driver circuit CL1 is coupled to the column tail ICK signal input terminal of the second column driver chip CL 2. If the head or tail of the second row driver chip CL2 is not a driver chip but a current source module PCS, the data of each frame communication is changed to be transferred from the head of the first row driver chip CL1, such as the driver chip IC1, to the head of the second row driver chip CL2 or to the tail of the second row driver chip CL 2.
Referring to fig. 21, in an alternative example, each frame of communication data may be transferred from the column-end driver chip ICK in the first column driver chip CL1 to the column-head driver chip IC1 of the second column driver chip CL2, and each frame of communication data may be transferred from the column-end driver chip ICK in the first column driver chip CL1 to the column-end driver chip ICK in the second column driver chip CL 2. In this case, the signal output terminal of the driver chip ICK in the first column driver chip CL1 may be configured to be coupled to the signal input terminal of the head-column driver chip IC1 in the second column driver chip CL2 through a coupling capacitor, or to the signal input terminal of the tail-column driver chip ICK in the second column driver chip CL2 through a coupling capacitor. If the head or tail of the second row driver chip is not a driver chip but an alternative current source module PCS, the communication data of each frame is transferred from the tail of the first row driver chip CL1, such as the driver chip ICK, to the head current source module of the second row driver chip CL2 or may be transferred to the tail current source module of the second row driver chip CL 2. Of course, each frame of communication data is allowed to be reversely transferred from the second column driver chip CL2 to the first column driver chip CL 1.
Referring to fig. 21, the communication data GSD of the display system or the independent pixel is sent to the display system frame by frame, and the current adjusting data sent to the current source module PCS sets the magnitude of the output current of the constant current source, and the constant current adjusting data sent to the driving circuit sets the magnitude of the constant current provided by the constant current unit. The constant current adjustment data sent to the driving circuit in this application may also be referred to as first current adjustment data, and the current adjustment data sent to the current source module PCS may also be referred to as second current adjustment data. The driving circuit can adjust the magnitude of the constant current provided by the constant current unit in the driving circuit according to the first current adjusting data, and the current source module PCS can adjust the magnitude of the output current of the programmable constant current source in the current source module according to the second current adjusting data. When the first current adjustment data and the second current adjustment data are set under the condition of the same frame of communication data, it is preferable that the magnitude of the constant current provided by the constant current unit is set by the first current adjustment data sent to the driving device in each frame of communication data, and the magnitude of the output current of the constant current source is set by the second current adjustment data sent to the current source module, and when the first current adjustment data and the second current adjustment data are set, the current flowing through any one path of light emitting diode is limited not to exceed the output current of the constant current source in the current source module.
Referring to fig. 21, the first to third light emitting diodes LED1-LED3 are taken as an example. The current regulation data allocated to the current source module PCS are asserted in the same frame of communication data to set the output current IT generated by the constant current source of the current source module PCS, and the constant current regulation data allocated to the driving circuit are asserted to set the values of the constant currents I1 to I3 supplied from the constant current cells CC1 to CC3, respectively. The currents flowing through the first to third light emitting diodes LED1-LED3 under the driving of the driving circuit are denoted as I1 and I2 and I3, respectively. IT is required that the currents I1 or I2 or I3 flowing through the LEDs 1-3 respectively do not exceed the output current IT of the constant current source of the current source module when designing the first current regulation data and the second current regulation data. This applies to the embodiment of the combined point light source of the single driving circuit and the single current source module as well as to the embodiments of the driving circuits and the current source modules configured in the basic unit of columns. Since the result of the NOR logic operation performed by the PWM signals is regarded as the control signal DX of a bypass module connected in parallel with the LEDs 1-3, the bypass module is turned on and shunted when the control signal DX is a valid logic value. The shunt current when the bypass module shunts is known to be determined by a constant current cell, such as CC1 of fig. 9-10 or CC5 of fig. 11. When the first and second current regulation data are set, IT is limited that the shunt current or shunt value flowing through the bypass module does not exceed the output current of the constant current source in the current source module, i.e., the shunt current provided by the CC1 flowing through the resistor RX or LED5 in fig. 9-10 does not exceed the output current IT of the constant current source, or the shunt current provided by the CC5 flowing through the resistor RX in fig. 11 does not exceed the output current IT of the constant current source. Considering that the currents supplied from the constant current cells CC1 and CC5 allow the driving circuit to be modified on-line by the received communication data, it is easy to define the shunt current not to exceed the output current of the constant current source.
Referring to fig. 21, the same as the above is that a current source module PCS having a constant current source is also provided on a line for supplying power to the driving circuits and is used to maintain the total input current of the driving circuits at a preset value, the output current of the constant current source, that is, the output current of the current source module PCS, flows to each driving circuit, and the total input current of each driving circuit is equal to the output current from the current source module. But instead of setting the programmable constant current source in the output current adjustable mode, the constant current source is set in the output current fixed mode. In this case, the current source module PCS may not use the decoding and data forwarding functions, and the output current provided by the constant current source of the current source module PCS is fixed without programmability but still clamps the total input current of the driving circuit. For the sake of convenience and clarity, the constant current unit of the driving circuit may be defined as a first constant current module, the constant current source of the current source module PCS may be defined as a second constant current module, the constant current adjustment data sent to the driving circuit may be defined as first current adjustment data, and the current adjustment data sent to the current source module PCS may be defined as second current adjustment data. It is observed that the number of current source modules used by the two column driving circuits of the first column driving chip CL1 and the second column driving chip CL2 of the display system are allowed to be different, and it is needless to say that the same number of current source modules may be used, but when there is a difference in the power supply voltages of different columns, different numbers of current source modules may be introduced to balance the voltage difference. The power supply lines for supplying power have distributed parasitic resistances and further cause slightly different power supply voltages for different columns, the columns with higher power supply voltages use a larger number of current source modules and the columns with lower power supply voltages use a smaller number of current source modules, that is, so-called, different numbers of current source modules are introduced to balance the power supply voltage difference between different columns.
While the present invention has been described with reference to the preferred embodiments and illustrative embodiments, it is to be understood that the invention as described is not limited to the disclosed embodiments. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. It is therefore intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (40)

1. A driving device for driving multiple light emitting diodes, comprising:
each pulse width modulation module forms a corresponding path of pulse width modulation signal according to the gray scale data matched with one path of light emitting diode matched with the pulse width modulation module, and the multiple paths of light emitting diodes correspond to the multiple paths of pulse width modulation signals;
each path of constant current unit is connected in series with one path of light emitting diode;
whether any path of light emitting diode flows through the constant current provided by the constant current unit connected in series with the light emitting diode is controlled by one path of pulse width modulation signal corresponding to any path of light emitting diode;
the common cycle period of each pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lightened in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals of each sub-time period is a preset value;
determining the time length of each sub-time period according to the clock signals distributed by each sub-time period and the number of the clock signals in a clock counting mode;
the frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
2. The drive device according to claim 1, characterized in that:
at least multiple paths of light-emitting diodes with three primary colors of red, green and blue are equipped, the gray data of each path of light-emitting diode is adjusted under the condition of mixing the colors of the three primary colors, and different colors are obtained by the change of the gray data matched with the multiple paths of light-emitting diodes respectively.
3. The drive device according to claim 1, characterized in that:
the pulse width modulation modules are provided with a counter, the multi-bit counting data output by the counter comprises appointed high-bit data and appointed low-bit data, and the number of the sub-time periods in each cycle period is determined by the number of the appointed high-bit data;
the time length of each sub-period is counted by a clock signal trigger counter matched with the sub-period, and the preset value related to the number of clock signals in each sub-period is determined by the number of bits of the specified low-bit data.
4. The drive device according to claim 3, characterized in that:
setting the digit Z of the appointed high-order data and the digit F of the appointed low-order data to be natural numbers larger than zero;
the number of sub-periods per cycle does not exceed 2ZAnd the preset value in each sub-period is 2F。
5. The drive device according to claim 3, characterized in that:
the counter is provided with a data selector, a plurality of clock signals distributed for a plurality of sub-time periods are input to a plurality of data input ends of the data selector, and the appointed high-order data is regarded as a channel selection signal of the data selector;
in each cycle period, the appointed low-bit data triggers the appointed high-bit data carry once after the count is full, and further triggers the data selector to switch and output different clock signals;
the different channel selection signals map different clock signals output by the data selector, thereby distributing one clock signal for each sub-period and triggering the counter to count.
6. The drive device according to claim 3, characterized in that:
each pulse width modulation module is provided with a data comparator;
the appointed low-level data is reordered according to a rule that the weight is from low to high to obtain reverse-order data;
in any sub-time period, the gray data and the reverse data matched with one path of light emitting diode paired with the pulse width modulation module are sent to a data comparator for comparison by the corresponding pulse width modulation module:
the pulse width modulation signal has an effective logic value when the reverse order data is lower than the gradation data.
7. The drive device according to claim 6, characterized in that:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of the cycle periods, so that the average value of the duty ratio of each pulse width modulation signal in a plurality of the cycle periods is adjusted by the jitter signal;
the effective logic values of one pulse width modulation signal generated by each pulse width modulation module in a corresponding sub-time period are in discrete distribution, and when any pulse width modulation module outputs a jitter signal, the jitter signal is immediately output after the last effective logic value in the pulse width modulation signals generated by the pulse width modulation module is set.
8. The drive device according to claim 1, characterized in that:
the effective logic values of each pulse width modulation signal in a corresponding sub-time period are arranged in a continuous mode; or
The effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a scattered manner.
9. The drive device according to claim 8, characterized in that:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of cycle periods, and when any pulse width modulation module outputs the jitter signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, the jitter signals are immediately output after the effective logic values of the pulse width modulation signals generated by any pulse width modulation module are set; or
If the effective logic values of the pulse width modulation signals are distributed in a scattered manner, the jitter signal is output immediately after the end of setting the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module.
10. The drive device according to claim 1, characterized in that:
the driving device comprises a shunting module connected with a plurality of paths of light-emitting diodes in parallel and used for stabilizing the input voltage supplied to the driving device;
the LED driving circuit comprises a power input end and a potential reference end, wherein the power input end receives input voltage, each light emitting diode and one constant current unit are coupled between the power input end and the potential reference end in series, and a shunt module is also coupled between the power input end and the potential reference end;
the shunt module comprises an adjustable parallel voltage reference circuit, the cathode of the adjustable parallel voltage reference circuit is coupled to the power input end through a resistor or not, the anode of the adjustable parallel voltage reference circuit is coupled to the potential reference end, and a resistor voltage divider is arranged between the power input end and the potential reference end;
the reference terminal of the adjustable parallel type voltage reference circuit is coupled to a voltage dividing node of the resistor voltage divider.
11. The drive device according to claim 1, characterized in that:
the first data transmission module is provided with a decoder and is used for decoding gray data from received communication data;
the driving device intercepts the communication data belonging to the driving device from each frame of communication data by the first data transmission module, and then forwards the rest other received communication data.
12. The drive device according to claim 1, characterized in that:
setting a constant current unit in a mode in which the supplied constant current is fixed; or
The programmable constant current unit is set in a mode that the supplied constant current can be adjusted, the driving device comprises a first data transmission module with a decoder, the first data transmission module is used for decoding first current adjusting data from received communication data, and the driving device adjusts the magnitude of the constant current supplied by the constant current unit according to the first current adjusting data.
13. The drive device according to claim 1, characterized in that:
the method comprises the following steps that multiple paths of constant current units are arranged, each path of light emitting diode is independently connected with a corresponding path of constant current unit in series in a one-to-one mode, when one path of pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the any path of light emitting diode is lightened, and the path of constant current unit connected with the light emitting diode in series is started; or
And a single and common constant current unit is provided, each path of light emitting diode is connected with the common constant current unit in series, and when one path of pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the common constant current unit is started and any path of light emitting diode is switched to be connected with the common constant current unit in series to be lightened.
14. The drive device according to claim 1, characterized in that:
the bypass module is connected with the multiple paths of light-emitting diodes in parallel, the result obtained by executing NOR logic operation on the multiple paths of pulse width modulation signals is regarded as a control signal of the bypass module, and the bypass module is triggered to shunt the total input current of the driving device when the control signal has an effective logic value.
15. The drive of claim 14, wherein:
the load of the bypass module and one path of constant current unit are set to be connected in series;
each path of light emitting diode and each load are respectively provided with a constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the constant current unit connected in series with the light emitting diode is started, and when the control signal has an effective logic value, the constant current unit connected in series with the load is started; or
The multiple paths of light emitting diodes and the load share a common constant current unit, when the pulse width modulation signal corresponding to any path of light emitting diode has an effective logic value, the pulse width modulation signal is switched to be connected in series with the common constant current unit, and when the control signal has an effective logic value, the load is switched to be connected in series with the common constant current unit.
16. The drive of claim 15, wherein:
the load comprises a light emitting diode or a non-emitting diode or a resistor.
17. The drive device according to claim 1, characterized in that:
a current source module with a constant current source is arranged on a line for supplying power to the driving device and is used for maintaining the total input current of the driving device at a preset value;
the constant current source is set in a mode of fixed output current or the programmable constant current source is set in a mode of adjustable output current.
18. The drive of claim 17, wherein:
the second data transmission module configured by the current source module is provided with a decoder and is used for decoding second current regulation data from the communication data received by the current source module;
the current source module adjusts the output current of the programmable constant current source according to the second current adjustment data.
19. The drive of claim 18, wherein:
as the second current regulation data received by the current source module is refreshed, the total input current is updated from a predetermined value corresponding to the second current regulation data before the refresh to a predetermined value corresponding to the second current regulation data after the refresh.
20. The drive of claim 18, wherein:
after the second data transmission module intercepts the communication data belonging to the current source module from each frame of communication data, the current source module forwards the rest of the received communication data.
21. The drive of claim 18, wherein:
the driving device also comprises a first data transmission module with a decoder, the first data transmission module is used for decoding gray data from received communication data and also used for decoding first current regulation data from the communication data, and the driving device regulates the magnitude of constant current provided by the programmable constant current unit according to the first current regulation data;
in each frame of communication data, setting the magnitude of constant current provided by the constant current unit by first current regulation data sent to the driving device, and setting the magnitude of output current of the constant current source by second current regulation data sent to the current source module;
when the first current regulation data and the second current regulation data are set, the current flowing through any path of light-emitting diode is limited not to exceed the output current of the constant current source in the current source module.
22. The drive of claim 21, wherein:
the result of the multi-channel pulse width modulation signal executing the NOR logic operation is regarded as a control signal of a bypass module which is connected with the multi-channel light-emitting diode in parallel, and the bypass module is triggered to be conducted and shunt when the control signal has an effective logic value;
the shunt current when the bypass module shunts is determined by one constant current unit, and the shunt current is limited not to exceed the output current of the constant current source in the current source module when the first and second current regulation data are set.
23. A display control chip comprising a driving device according to any one of claims 1 to 22.
24. A display control chip for driving multiple Light Emitting Diodes (LEDs), comprising:
each pulse width modulation module forms a corresponding path of pulse width modulation signal according to the gray scale data matched with one path of light emitting diode matched with the pulse width modulation module, and the multiple paths of light emitting diodes correspond to the multiple paths of pulse width modulation signals;
each path of pulse width modulation signal is used for driving a path of light emitting diode corresponding to the pulse width modulation signal to perform display control;
the common cycle period of each pulse width modulation signal is divided into a plurality of sub-time periods, the effective logic value of each pulse width modulation signal is distributed in a corresponding sub-time period, and a plurality of paths of light emitting diodes are sequentially lightened in a time-sharing manner in the cycle period;
each sub-time period is distributed with a clock signal, and the number of the clock signals of each sub-time period is a preset value;
the time length of each sub-time period is triggered by a clock signal matched with the sub-time period to count by a counter;
the frequencies of the plurality of clock signals allocated for the plurality of sub-periods of each cycle period are set to be the same or different.
25. A display device based on the driving apparatus of claim 1, comprising:
each stage of driving device intercepts communication data belonging to each stage of communication data from each frame of communication data through a first data transmission module of each stage of driving device, and transmits the received other rest communication data to a rear stage of driving device which is in cascade connection with the driving device, so that each stage of driving device captures gray data belonging to the stage;
each level of driving device drives the matched multi-path light emitting diodes to carry out display control according to the gray scale data of the level.
26. The display device according to claim 25, wherein:
each driving device further comprises a power input terminal for receiving an input voltage and a potential reference terminal;
any path of light emitting diode in each driving device is coupled between the power input end and the potential reference end in series with a corresponding path of constant current unit, and a shunt module is also coupled between the power input end and the potential reference end.
27. The display device according to claim 26, wherein:
the plurality of driving means are arranged in one or more columns, a power supply input terminal of a first driving means as a column head in each column is coupled to a power supply positive terminal and a potential reference terminal of a last driving means as a column tail is coupled to a power supply negative terminal, and a power supply input terminal of a subsequent driving means in each column is arranged to be coupled to a potential reference terminal of an adjacent previous driving means.
28. The display device according to claim 27, wherein:
each row driving device is connected in series with at least one current source module with a constant current source, and the current source module is used for limiting the total input current flowing from the power supply input end of any one driving device in each row driving device to the potential reference end to a preset value, and setting the constant current source in a mode of fixed output current or setting the programmable constant current source in a mode of adjustable output current.
29. The display device according to claim 28, wherein:
under the condition that the programmable constant current source is arranged, the second data transmission module configured by the current source module is provided with a decoder used for decoding second current regulation data from the received communication data, and the current source module regulates the output current of the constant current source according to the second current regulation data; and
each current source module and the multi-stage driving device are arranged in a cascade connection relationship, so that the current source module with the data forwarding function and the driving device can forward communication data to each other.
30. The display device according to claim 29, wherein:
after the previous frame of communication data transmitted to the current source modules and the driving device is refreshed to the next frame of communication data, the second current adjusting data received by each current source module is refreshed synchronously according to frames;
the total input current of each driving device in each row of driving devices is also determined again by the current source module connected in series in each row of driving devices according to the refreshed second current regulation data.
31. The display device according to claim 29, wherein:
the first data transmission module of the driving device is also used for decoding first current regulation data from the communication data, and the driving device regulates the magnitude value of the constant current provided by the programmable constant current unit according to the first current regulation data;
after the previous frame of communication data transmitted to the current source module and the driving devices is refreshed to the next frame of communication data, the first current regulation data received by each driving device is refreshed synchronously according to the frame, so that the constant current provided by each constant current unit in each driving device is redetermined according to the refreshed first current regulation data.
32. The display device according to claim 31, wherein:
each driving device is provided with a bypass module connected with the multiple paths of light-emitting diodes in parallel, the result obtained by executing NOR logic operation on the multiple paths of pulse width modulation signals corresponding to the multiple paths of light-emitting diodes in each driving device is regarded as a control signal of the bypass module, and the bypass module is triggered to shunt the total input current of the driving device when the control signal has an effective logic value;
the shunt value of the bypass module in each driving device during shunting is determined by the constant current provided by one constant current unit, and after the previous frame of communication data transmitted to the current source module and the driving device is refreshed to the next frame of communication data, the constant current of one constant current unit distributed for the bypass module in each driving device is determined again according to the refreshed first current regulation data.
33. The display device according to claim 29, wherein:
the current source module and the multi-stage driving device transmit communication data in a mode based on a single-wire communication protocol.
34. A display control method for driving multiple light emitting diodes, comprising:
any path of light emitting diode and one path of constant current unit are connected in series;
forming a pulse width modulation signal corresponding to each path of light emitting diode by using a pulse width modulation module according to the gray scale data matched to each path of light emitting diode, wherein the plurality of paths of light emitting diodes correspond to the plurality of paths of pulse width modulation signals;
whether each path of light-emitting diode flows through the constant current provided by the constant current unit connected in series with the light-emitting diode is controlled by a path of pulse width modulation signal corresponding to the light-emitting diode;
dividing a common cycle period of each pulse width modulation signal into a plurality of sub-time periods, and arranging an effective logic value of each pulse width modulation signal in a corresponding sub-time period;
distributing a clock signal for each sub-time period and setting the number of the clock signals of each sub-time period as a preset value;
determining the time length of each sub-time period according to the clock signals distributed in each sub-time period and the number of the clock signals in a clock counting mode;
the frequencies of the plurality of clock signals assigned to the plurality of sub-periods of each cycle period are set to be the same or different.
35. The method of claim 34, wherein:
the bypass module playing a role in shunting and the shunting module playing a role in stabilizing voltage are connected with the multiple paths of light-emitting diodes in parallel;
whether the bypass module is switched on or not is controlled by a control signal, a result obtained by executing NOR logic operation on the multipath pulse width modulation signals is defined as the control signal, and the current of the bypass module under the condition of switching on and shunting is a preset constant current value;
in each cycle period, when the multiple paths of light emitting diodes are not conducted, at least the bypass module and the shunt module carry out shunt together.
36. The method of claim 34, wherein:
the effective logic values of each pulse width modulation signal in a corresponding sub-time period are arranged in a continuous mode; or
The effective logic values of each pulse width modulation signal in a corresponding sub-period are arranged in a scattered manner.
37. The method of claim 36, wherein:
each pulse width modulation module outputs a jitter signal with an effective logic value once every a plurality of cycle periods, and when any pulse width modulation module outputs the jitter signal:
if the effective logic values of the pulse width modulation signals are arranged in a continuous mode, the jitter signals are immediately output after the effective logic values of the pulse width modulation signals generated by any pulse width modulation module are set; or
If the effective logic values of the pulse width modulation signals are distributed in a scattered manner, the jitter signal is output immediately after the end of setting the last effective logic value in the pulse width modulation signals generated by any pulse width modulation module.
38. The method of claim 34, wherein:
triggering a counter to count by a clock signal matched with the time length of any sub-time period to obtain a count value of any sub-time period, and reordering the count values according to a rule that the weight is from low to high to obtain reverse data;
and comparing the reverse data of the count value of any sub-time period with the gray scale data matched with the lighted one path of light emitting diode in any sub-time period, wherein the pulse width modulation signal has an effective logic value when the reverse data is lower than the gray scale data.
39. The method of claim 34, wherein:
the time length of each sub-period is adjusted in a mode of adjusting the frequency of one clock signal distributed to each sub-period, and then the total time length of the cycle period shared by all paths of pulse width modulation signals is adjusted.
40. The method of claim 34, wherein:
the plurality of clock signals allocated to the plurality of sub-periods are obtained by dividing an initial clock signal output from one oscillator by a plurality of times, respectively.
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