CN113691263B - Multi-bit parallel checking method and device, storage medium and Turbo decoder - Google Patents
Multi-bit parallel checking method and device, storage medium and Turbo decoder Download PDFInfo
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Abstract
The invention discloses a multi-bit parallel checking method and device, a storage medium and a Turbo decoder, wherein the method comprises the following steps: in the half iterative decoding process of the Turbo decoder, determining hard decision bits which are output by each decoding unit in the Turbo decoder at the same time; and when each decoding unit outputs the hard decision bits simultaneously, performing cyclic redundancy check according to the hard decision bits output by each decoding unit simultaneously. Therefore, the CRC check is started immediately after each decoding unit in the semi-iterative decoding process outputs the hard decision bits, the CRC check is not started after the hard decision bits of all code blocks are not required to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a multi-bit parallel checking method and apparatus, a storage medium, and a Turbo decoder.
Background
After the downlink Turbo decoder in the LTE (Long Term Evolution ) system decodes, each transport block performs a CRC (Cyclic Redundancy Check ) check to determine whether to terminate the decoding of the Turbo decoder in advance, so as to save power consumption, and determine whether the decoding is correct, so as to finish reporting, so that the CRC result of the present half-iterative decoding needs to be known after each half-iterative decoding of the Turbo decoder.
In the related art, the CRC check is started after each half iterative decoding is completed, and the next half iterative decoding is started after the CRC check result is obtained, and in this process, the decoding duration of the Turbo decoder is increased due to the need of an independent CRC check time, which results in a low utilization rate of the Turbo decoder.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present invention is to provide a multi-bit parallel checking method, which starts CRC checking immediately after each decoding unit outputs hard decision bits in a half-iterative decoding process, without waiting for the hard decision bits of all code blocks to be output before starting CRC checking, thereby reducing delay caused by CRC checking and improving the utilization rate of a Turbo decoder.
A second object of the present invention is to propose a computer readable storage medium.
A third object of the present invention is to propose a Turbo decoder.
A fourth object of the present invention is to provide a multi-bit parallel checking device.
To achieve the above objective, an embodiment of a first aspect of the present invention provides a multi-bit parallel checking method, applied to a Turbo decoder, including: in the half iterative decoding process of the Turbo decoder, determining hard decision bits which are output by each decoding unit in the Turbo decoder at the same time; and when each decoding unit outputs the hard decision bits simultaneously, performing cyclic redundancy check according to the hard decision bits output by each decoding unit simultaneously.
According to the multi-bit parallel checking method provided by the embodiment of the invention, in the half-iterative decoding process of the Turbo decoder, the hard decision bits output by each decoding unit in the Turbo decoder are determined, and when each decoding unit outputs the hard decision bits simultaneously, the cyclic redundancy check is performed according to the hard decision bits output by each decoding unit simultaneously. Therefore, the CRC check is started immediately after each decoding unit in the semi-iterative decoding process outputs the hard decision bits, the CRC check is not started after the hard decision bits of all code blocks are not required to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.
According to one embodiment of the present invention, performing cyclic redundancy check according to hard decision bits simultaneously output from each decoding unit includes: comparing the hard decision bit output by each decoding unit simultaneously with the hard decision bit output correspondingly in the previous half iterative decoding process to obtain updated hard decision bit corresponding to each decoding unit; determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit; and carrying out operation according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a verification result.
According to one embodiment of the present invention, when the hard decision bits outputted by each decoding unit simultaneously are compared with the hard decision bits outputted correspondingly in the previous half iterative decoding process, the same bits are set to 0, so as to obtain updated hard decision bits corresponding to each decoding unit.
According to one embodiment of the present invention, determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit includes: determining a first lookup table according to an offset address corresponding to each hard decision bit for each decoding unit; establishing a relation table between the hard decision bit of each decoding unit and the output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit and the relation table corresponding to each decoding unit.
According to one embodiment of the present invention, for each decoding unit, determining a first lookup table according to an offset address corresponding to each hard decision bit includes: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modular operation result into a plurality of phases, wherein the number of the phases is the same as the number of offset addresses corresponding to each decoding unit; and reading out a lookup table of each phase according to the offset address corresponding to each hard decision bit.
According to one embodiment of the invention, the calculation parameters are determined according to the following formula:
F(i)＝f(P-1-i)，
wherein F (i) is the calculated parameter, 0.ltoreq.i.ltoreq.P-1, P is the number of decoding units, F (0) =predetermined base value, F (1) =x M mod g (x), f (i+1) =f (i) +f (1), x is an element on a finite field, M is a ratio between a length of a data block and the number of decoding units in a half-iterative decoding process, mod is a modular operation, and g (x) is a generator polynomial of a cyclic redundancy check.
According to one embodiment of the present invention, the operation is performed according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters, to obtain the verification result, including: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on the second modulo operation result obtained by the M times to obtain a verification result, wherein M is the ratio of the length of the data block to the number of the decoding units in the half iterative decoding process.
To achieve the above object, a second aspect of the present invention provides a computer-readable storage medium having stored thereon a multi-bit parallel check program which, when executed by a processor, implements a multi-bit parallel check method as described above.
According to the computer readable storage medium of the embodiment of the invention, through the multi-bit parallel checking method, CRC checking is started immediately after each decoding unit in the half iterative decoding process outputs hard decision bits, CRC checking is not started after hard decision bits of all code blocks are not required to be output, delay caused by CRC checking is reduced, and the utilization rate of a Turbo decoder is improved.
In order to achieve the above objective, an embodiment of a third aspect of the present invention provides a Turbo decoder, which includes a memory, a processor, and a multi-bit parallel check program stored in the memory and capable of running on the processor, where the processor implements the multi-bit parallel check method when executing the multi-bit parallel check program.
According to the Turbo decoder provided by the embodiment of the invention, through the multi-bit parallel checking method, CRC checking is started immediately after each decoding unit in the half-iterative decoding process outputs hard decision bits, and the CRC checking is not started after the hard decision bits of all code blocks are not required to be output, so that delay caused by the CRC checking is reduced, and the utilization rate of the Turbo decoder is improved.
To achieve the above object, a fourth aspect of the present invention provides a multi-bit parallel checking device, which is applied to a Turbo decoder, and the device includes: the determining module is used for determining hard decision bits which are output by each decoding unit in the Turbo decoder simultaneously in the half-iterative decoding process of the Turbo decoder; and the checking module is used for performing cyclic redundancy check according to the hard decision bits output by each decoding unit at the same time when the hard decision bits are output by each decoding unit at the same time.
According to the multi-bit parallel checking device provided by the embodiment of the invention, the hard decision bits which are simultaneously output by each decoding unit in the Turbo decoder are determined by the determining module in the half-iterative decoding process of the Turbo decoder, and the cyclic redundancy check is carried out according to the hard decision bits which are simultaneously output by each decoding unit when the hard decision bits are simultaneously output by each decoding unit by the checking module. Therefore, the CRC check is started immediately after each decoding unit in the semi-iterative decoding process outputs the hard decision bits, the CRC check is not started after the hard decision bits of all code blocks are not required to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1a is a flow chart of CRC check in the related art;
FIG. 1b is a flow chart of a related art verification process after CRC calculation parallelism is improved;
FIG. 2 is a schematic diagram of a CRC check structure after improving the parallelism of CRC calculation in the related art;
FIG. 3 is a flow chart of a multi-bit parallel check method according to an embodiment of the present invention;
FIG. 4 is a flow chart of a multi-bit parallel check method according to one embodiment of the invention;
FIG. 5 is a flow chart of a multi-bit parallel check method according to another embodiment of the present invention;
FIG. 6 is a diagram illustrating the internal structure of a lookup table according to one embodiment of the invention;
FIG. 7 is a schematic representation of the generation of calculated parameters according to one embodiment of the invention;
FIG. 8 is a schematic diagram of a multi-bit parallel checking method according to one embodiment of the present invention;
fig. 9 is a schematic structural diagram of a multi-bit parallel checking device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
After the downlink Turbo decoder in the LTE system decodes, each transmission block performs CRC check to judge whether to terminate the decoding of the Turbo decoder in advance so as to save power consumption, and judge whether the decoding is correct so as to finish reporting, so that the CRC check result of the half iterative decoding needs to be known after each half iterative decoding of the Turbo decoder.
In the related art, the CRC check process flow is as shown in fig. 1 a: starting CRC after the Turbo decoder finishes half iterative decoding each time, and starting the next half iterative decoding after the CRC result is obtained, wherein the Turbo decoder is in a waiting state in the CRC period, so that the decoding duration of the Turbo decoder is prolonged, and the utilization rate of the Turbo decoder is low. In order to reduce the time taken for the CRC check to achieve the result shown in fig. 1b, this is currently achieved mainly by increasing the parallelism of the CRC check. Specifically, referring to fig. 2, during CRC check, hard decision bit data obtained by the Turbo decoder is first divided into a plurality of segments, such as P segments, and stored in P transport blocks, and CRC check is performed on each transport block to obtain a CRC check result of each transport block, and then the CRC check results of each transport block are serially connected by dot multiplication and exclusive or operation using parameters stored in a memory to obtain a CRC check result of the whole data. In order to reduce the time taken for the CRC check, the parallelism of the CRC check is generally increased by increasing the number of transport blocks, or the bit width of the CRC parallel check (e.g. 32 bits or 64 bits).
Although the two modes can reduce the time occupied by CRC to a certain extent so as to reduce the decoding time of the Turbo decoder, the independent CRC time is still needed, and the utilization rate of the Turbo decoder is still not high; meanwhile, the increase of the number of the transmission blocks can lead to the reduction of the depth of the hard decision bit memory, the increase of the width of the CRC parallel check bits can lead to the increase of the width of the hard decision bit memory, both modes can lead to the increase of the area of the hard decision bit memory, and the realization difficulty is increased; meanwhile, the computational resources are required to be increased to improve the parallelism of CRC (cyclic redundancy check), so that the CRC area overhead is large.
In view of the above technical problems, the present application provides a multi-bit parallel checking method and apparatus, a storage medium, and a Turbo decoder, where the CRC check is set in a half-iterative decoding process of the Turbo decoder, specifically, the CRC check starts when a decoding unit of the Turbo decoder starts to output hard decision bits, as shown in fig. 3, after each half-iterative decoding is completed, the CRC check of the whole code block is also completed synchronously, and a CRC check result is obtained, and immediately after the hard decision, the next half-iterative decoding is started, and the Turbo decoder is always in a working state, so that the utilization rate of the Turbo decoder is greatly improved, and the hard decision bit memory of the present application is easier to manage, and there is no problem of memory depth and width variation caused by parallelism.
The multi-bit parallel checking method and device, the storage medium and the Turbo decoder provided by the application are described in detail below.
Fig. 4 is a flowchart of a multi-bit parallel checking method according to an embodiment of the present invention, and the multi-bit parallel checking method may include the following steps, as shown in reference to fig. 4, by taking the method applied to a Turbo decoder as an example:
step S100, in the half iterative decoding process of the Turbo decoder, determining the hard decision bits output by each decoding unit in the Turbo decoder at the same time.
For example, first, a length of a data block to be decoded is defined as K, a maximum value of K in the LTE system is 6144, and assuming that the Turbo decoder has P decoding units, each decoding unit decodes data with a length of M, m=p=k, and each decoding unit outputs at least one hard decision bit at the same time. In the half iterative decoding process of the Turbo decoder, judging whether each decoding unit outputs hard decision bits at the same time, and if so, acquiring the hard decision bits output by each decoding unit.
Step S200, when each decoding unit outputs hard decision bits simultaneously, cyclic redundancy check is performed according to the hard decision bits output by each decoding unit simultaneously.
Specifically, in the half iterative decoding process, if each decoding unit outputs hard decision bits simultaneously, the CRC check is immediately started according to the hard decision bits output by each decoding unit at the same time, instead of starting the CRC check after waiting for the hard decision bits output of all the code blocks, so that after each half iterative decoding is finished, the CRC check of all the code blocks is also finished synchronously, and then the next half iterative decoding is performed, thereby saving the time occupied by the CRC check alone.
In this embodiment, in the half iterative decoding process of the Turbo decoder, the CRC check is started immediately after each decoding unit of the Turbo decoder outputs hard decision bits simultaneously, instead of waiting for the hard decision bits of all code blocks to be output, that is, starting the CRC check after the end of the present half iterative decoding, thereby eliminating the delay caused by the CRC check and greatly improving the utilization rate of the Turbo decoder.
Further, in some embodiments, referring to fig. 5, performing CRC check according to the hard decision bits simultaneously output by each decoding unit includes:
step S201, comparing the hard decision bit outputted by each decoding unit simultaneously with the hard decision bit outputted correspondingly in the previous half iterative decoding process, and obtaining the updated hard decision bit corresponding to each decoding unit.
Specifically, during CRC check, the hard decision bits output by each decoding unit at the same time may be compared with the hard decision bits output correspondingly in the previous half-iterative decoding process, so as to obtain new hard decision bits, i.e., updated hard decision bits. It should be noted that, the half-iterative decoding includes a plurality of half-iterative loops, where the last half-iterative decoding specifically refers to the last half-iterative loop, for example, the odd half-iterative decoding shown in fig. 3 includes a plurality of half-iterative loops, and when the CRC check is performed, the hard decision bits output by each decoding unit in the current half-iterative loop at the same time are compared with the hard decision bits output by each decoding unit in the last half-iterative loop, so as to obtain new hard decision bits.
Optionally, when comparing the hard decision bit output by each decoding unit simultaneously with the hard decision bit output correspondingly in the previous half iterative decoding process, the same bit is set to 0 so as to obtain the updated hard decision bit corresponding to each decoding unit. For example, assume that each decoding unit outputs 4 hard decision bits simultaneously, taking one decoding unit as an example, the 4 hard decision bits output during the present half iterative decoding are { A1, A2, A3, A4}, the 4 hard decision bits output during the last half iterative decoding are { a11, a21, a31, a41}, if A1 is the same as a11, the bit is set to 0, otherwise, the bit is kept unchanged; if A2 is the same as A21, the bit is set to 0, otherwise, the bit is kept unchanged; and so on, finally updated hard decision bits such as {0, A2, 0, A4}. The other decoding units have the same processing manner as the decoding unit, and are not described herein. Therefore, when the hard decision bit output under a certain cycle of the current iteration is the same as the hard decision bit output at the same bit position of the last iteration, the hard decision bit is set to 0, so that CRC calculation of the corresponding bit under the cycle can be omitted, and the power consumption of CRC check can be effectively reduced when the Turbo decoder is about to converge.
Step S202, determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit.
It should be noted that, each hard decision bit has an offset address, and taking 4 hard decision bits as an example, the offset addresses corresponding to the 4 hard decision bits may be represented as { oa3, oa2, oa1, oa0}, and the offset addresses corresponding to each hard decision bit are all in the range of [0, M-1], where M is the data length decoded by the corresponding decoding unit. Alternatively, the offset addresses corresponding to the hard decision bits at the same position in all the decoding units are the same, that is, the offset addresses corresponding to the 4 hard decision bits in each of all the decoding units may be { oa3, oa2, oa1, oa0}.
Assuming that the obtained 4 updated hard decision bits corresponding to each decoding unit are { b3, b2, b1, b0}, and the offset addresses corresponding to the 4 hard decision bits are { oa3, oa2, oa1, oa0}, the lookup table corresponding to each decoding unit may be determined according to the 4 updated hard decision bits { b3, b2, b1, b0} corresponding to each decoding unit and the offset addresses corresponding to the 4 hard decision bits { oa3, oa2, oa1, oa0}. It should be noted that, the Look-Up Table (LUT) is essentially a RAM, and after data is written into the RAM (RaMdom Access Memory, random access memory) in advance, each time a signal is input, it is equal to inputting an address to perform Look-Up, find out the content corresponding to the address, and output.
Optionally, in some embodiments, determining the lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit includes: determining a first lookup table according to an offset address corresponding to each hard decision bit for each decoding unit; establishing a relation table between the hard decision bit of each decoding unit and the output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit and the relation table corresponding to each decoding unit.
Specifically, when determining the lookup table corresponding to each decoding unit, taking one decoding unit as an example, the first lookup table may be determined according to the offset addresses { oa3, oa2, oa1, oa0} corresponding to 4 hard decision bits, so as to obtain 4 first lookup tables { lut3, lut2, lut1, lut0}, then the relation table between the hard decision bits { b3, b2, b1, b0} of the decoding unit and the output lookup table L (i) is established according to the 4 first lookup tables { lut3, lut, lut1, lut }, that is, the relation between the two first lookup tables { lut3, lut2, lut1, lut0} is determined, and finally the lookup table L (i) corresponding to the decoding unit is determined according to the updated hard decision bits { b3, b2, b1, b0} and the relation table.
Optionally, in some embodiments, for each decoding unit, determining the first lookup table according to the offset address corresponding to each hard decision bit includes: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modular operation result into a plurality of phases, wherein the number of the phases is the same as the number of offset addresses corresponding to each decoding unit; and reading out a lookup table of each phase according to the offset address corresponding to each hard decision bit.
Specifically, the look-up table has an overall depth of K/P, when K is 6144, the overall depth is 6144/P, the width can be 24 bits, and x is stored internally i mod g (x), wherein x is an element on a finite field, i is more than or equal to 0 and less than or equal to M-1, M is the data length decoded by each decoding unit, mod represents a modulo operation, and here represents taking x i Dividing the remainder by g (x), g (x) being the generator polynomial for the CRC check. The lookup table may be divided into a plurality of phases according to a first modulo operation result obtained by performing modulo operation on the offset address corresponding to the decoding unit, for example, modulo 4 operation (such as modulo 4 addition) is performed on the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits to obtain a first modulo operation result, then the first modulo operation result is divided into 4 phases and recorded as { phase3, phase2, phase1, phase0}, and the specific structure is shown in fig. 6, and finally the lookup table of each phase is read out according to the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits to obtain 4 first lookup tables { lut, lut2, lut1, lut0}. It should be noted that, since the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard-decision bits output by the decoding unit exactly satisfy the 4 different phase conditions, there is no problem of address collision when the lookup table is read.
Further, after obtaining the 4 first lookup tables, a table of relation between the hard decision bits { b3, b2, b1, b0} of the decoding unit and the output lookup table L (i) can be established according to the 4 first lookup tables { lut3, lut2, lut1, lut0} as shown in table 1:
TABLE 1
In the table 1 of the description of the present invention,representing an exclusive or operation.
Finally, the lookup table L (i) corresponding to the decoding unit is determined according to the hard decision bits { b3, b2, b1, b0} of the decoding unit and the relation table. For example, when the hard decision bits { b3, b2, b1, b0} are {0000}, the corresponding lookup table L (i) is 0x000000; as another example, when the hard decision bits { b3, b2, b1, b0} are {0111}, the corresponding lookup table L (i) is
Step S203, operation is performed according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters, and a verification result is obtained.
Specifically, after the lookup table L (i) corresponding to each decoding unit is obtained in the foregoing manner, an operation is performed according to the lookup table L (i) corresponding to each decoding unit and a predetermined calculation parameter F (i), and finally a CRC check result is obtained. It should be noted that, each decoding unit corresponds to one calculation parameter F (i). Alternatively, the generation process of the calculation parameter F (i) is as shown in fig. 7, and satisfies F (i) =f (P-1-i), where 0.ltoreq.i.ltoreq.p-1, P is the number of decoding units, F (0) =a predetermined base value, e.g., F (0) =0x800000, F (1) =x M mod g (x), f (i+1) =f (i) +f (1), x is an element on the finite field, M is a ratio between a length of a data block and a number of decoding units in the half-iterative decoding process, that is, a length of data decoded by the decoding units, mod is a modulo operation, where x is taken i Dividing the remainder of g (x), g (x) being the generator polynomial of the cyclic redundancy check.
In fig. 7, the convolution operation unit convolves two 24-bit inputs to obtain 47-bit data, and the modulo operation unit performs mod g (x) on the 47-bit input to obtain 24-bit data.
Optionally, in some embodiments, performing an operation according to a lookup table corresponding to each decoding unit and a predetermined calculation parameter to obtain a verification result includes: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on the second modulo operation result obtained by the M times to obtain a verification result, wherein M is the ratio of the length of the data block to the number of the decoding units in the half iterative decoding process.
Specifically, after obtaining the lookup table L (i) corresponding to each decoding unit, performing convolution operation on the lookup table L (i) corresponding to each decoding unit and the corresponding calculation parameter F (i) to obtain P convolution operation results, then performing accumulation calculation (i.e. summation) on the P convolution operation results to obtain an accumulation operation result, performing modulo-2 operation (e.g. modulo-2 summation) on the accumulation operation result to obtain a second modulo operation result, repeating M times (i.e. K/P), and finally performing modulo-2 operation (e.g. modulo-2 summation) on the second modulo operation result obtained by M times to obtain a CRC check result.
As a specific example, referring to fig. 8, the multi-bit parallel check may include the following process:
taking the length k=6144 of the data block and the number p=16 of decoding units as an example. 16 calculation parameters F (i), F (i) =f (15-i), where 0.ltoreq.i.ltoreq.15, may be generated in advance according to the calculation parameter generation method corresponding to fig. 7, and the calculation result is:
f(0)＝0x800000；
f(1)＝x M mod g (x), wherein m=k/P;
f(2)＝f(1)+f(1)mod 2；
f(3)＝f(2)+f(1)mod 2；
f(i+1)＝f(i)+f(1)mod 2；
f(15)＝f(14)+f(1)mod 2。
in the half iterative decoding process of the Turbo decoder, when 16 decoding units output hard decision bits at the same time, CRC check is started immediately. In CRC check, each decoding unit outputs 4 hard decision bits to a comparing unit, the comparing unit compares the 4 hard decision bits output by each decoding unit with the hard decision bits at the same position output by the previous half iteration, the hard decision bits of the same bit are set to 0, 4 updated hard decision bits { b3, b2, b1, b0} are obtained, offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits are output, and the offset addresses corresponding to the 4 hard decision bits are subjected to modulo 4 operation and stored in 4 phases. Then, the lookup table unit searches the corresponding first lookup table according to the offset addresses { oa3, oa2, oa1, oa0} corresponding to the 4 hard decision bits to obtain 4 first lookup tables { lut, lut2, lut1, lut0}, and selects the corresponding lookup table L (i) according to the 4 hard decision bits { b3, b2, b1, b0} corresponding to each decoding unit, where 0.ltoreq.i.ltoreq.15. And then, the convolution operation unit carries out convolution calculation on the lookup table L (i) corresponding to each decoding unit and the corresponding calculation parameter F (i) to obtain 16 convolution results, and the 16 convolution results are accumulated through the accumulation unit to obtain an accumulation operation result, and the accumulation operation result is subjected to modulo 2 operation through the modulo operation unit to obtain a CRC check result. Repeating K/P times, and accumulating the results to obtain the modulo-2 operation to obtain the CRC result of the whole code block.
Therefore, in the half iterative decoding process of the Turbo decoder, after the decoding units output hard decision bits simultaneously, CRC check starts immediately, instead of waiting for the start of all code block hard decision bits to be output, delay caused by CRC check in the related art is reduced, the utilization rate of the Turbo decoder is improved, the hard decision bit memory is easier to manage, namely the lookup table unit in FIG. 8 is easier to manage, the problem of depth and width change caused by parallelism is avoided, for example, the number of the decoding units is unchanged, the corresponding depth is unchanged, and the corresponding bit can be 24 and the width is unchanged.
It should be noted that the convolution operation unit and the modulo operation unit in fig. 8 may be shared with the convolution operation unit and the modulo operation unit shown in fig. 7, that is, may be multiplexed in different calculation processes, so that calculation resources may be saved and the utilization rate may be improved.
In summary, by starting the CRC check immediately after each decoding unit in the half-iterative decoding process outputs the hard decision bits, it is not necessary to wait for all decoding units to start the CRC check after outputting the hard decision bits, thereby reducing the delay caused by the CRC check and improving the utilization rate of the Turbo decoder. In addition, the hard decision bit buffer is easier to manage, and the problem that the depth and width of the buffer are changed due to parallelism is solved.
In some embodiments, embodiments of the present invention also provide a computer readable storage medium having stored thereon a multi-bit parallel check program that when executed by a processor implements a multi-bit parallel check method as described above.
According to the computer readable storage medium of the embodiment of the invention, through the multi-bit parallel checking method, CRC checking is started immediately after each decoding unit in the half iterative decoding process outputs hard decision bits, CRC checking is not started after hard decision bits of all code blocks are not required to be output, delay caused by CRC checking is reduced, and the utilization rate of a Turbo decoder is improved.
In some embodiments, the present invention further provides a Turbo decoder, which includes a memory, a processor, and a multi-bit parallel check program stored in the memory and capable of running on the processor, where the processor implements the multi-bit parallel check method when executing the multi-bit parallel check program.
According to the Turbo decoder provided by the embodiment of the invention, through the multi-bit parallel checking method, CRC checking is started immediately after each decoding unit in the half-iterative decoding process outputs hard decision bits, and the CRC checking is not started after the hard decision bits of all code blocks are not required to be output, so that delay caused by the CRC checking is reduced, and the utilization rate of the Turbo decoder is improved.
Fig. 9 is a schematic structural diagram of a multi-bit parallel checking device according to an embodiment of the present invention, and taking the device applied to a Turbo decoder as an example, referring to fig. 9, the multi-bit parallel checking device 90 includes: a determination module 91 and a verification module 92.
The determining module 91 is configured to determine, in a half-iterative decoding process of the Turbo decoder, hard decision bits that are output by each decoding unit in the Turbo decoder at the same time. The checking module 92 is configured to perform cyclic redundancy check according to the hard decision bits output by each decoding unit simultaneously when each decoding unit simultaneously outputs the hard decision bits.
In some embodiments, the verification module 92 is specifically configured to: comparing the hard decision bit output by each decoding unit simultaneously with the hard decision bit output correspondingly in the previous half iterative decoding process to obtain updated hard decision bit corresponding to each decoding unit; determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit; and carrying out operation according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a verification result.
In some embodiments, the verification module 92 is specifically configured to: and when the hard decision bit output by each decoding unit simultaneously is compared with the hard decision bit output correspondingly in the previous half iterative decoding process, the same bit is set to 0 so as to obtain the updated hard decision bit corresponding to each decoding unit.
In some embodiments, the verification module 92 is specifically configured to: determining a first lookup table according to an offset address corresponding to each hard decision bit for each decoding unit; establishing a relation table between the hard decision bit of each decoding unit and the output lookup table according to the first lookup table; and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit and the relation table corresponding to each decoding unit.
In some embodiments, the verification module 92 is specifically configured to: performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result; dividing the first modular operation result into a plurality of phases, wherein the number of the phases is the same as the number of offset addresses corresponding to each decoding unit; and reading out a lookup table of each phase according to the offset address corresponding to each hard decision bit.
In some embodiments, the verification module 92 is specifically configured to determine the calculated parameters according to the following formula:
F(i)＝f(P-1-i)，
wherein F (i) is a calculation parameter, 0.ltoreq.i.ltoreq.P-1, P is the number of decoding units, F (0) =a predetermined base value, F (1) =x M mod g (x), f (i+1) =f (i) +f (1), x is an element on a finite field, M is a ratio between a length of a data block and the number of decoding units in a half-iterative decoding process, mod is a modular operation, and g (x) is a generator polynomial of a cyclic redundancy check.
In some embodiments, the verification module 92 is specifically configured to: performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results; performing accumulation operation on the convolution operation results to obtain an accumulation operation result; performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result; and repeatedly executing M times, and performing modulo-2 operation on the second modulo operation result obtained by the M times to obtain a verification result, wherein M is the ratio of the length of the data block to the number of the decoding units in the half iterative decoding process.
It should be noted that, for the description of the multi-bit parallel checking device in the present application, please refer to the description of the multi-bit parallel checking method in the present application, and detailed descriptions thereof are omitted herein.
According to the multi-bit parallel checking device provided by the embodiment of the invention, the hard decision bits which are simultaneously output by each decoding unit in the Turbo decoder are determined by the determining module in the half-iterative decoding process of the Turbo decoder, and the cyclic redundancy check is carried out according to the hard decision bits which are simultaneously output by each decoding unit when the hard decision bits are simultaneously output by each decoding unit by the checking module. Therefore, the CRC check is started immediately after each decoding unit in the semi-iterative decoding process outputs the hard decision bits, the CRC check is not started after the hard decision bits of all code blocks are not required to be output, the delay caused by the CRC check is reduced, and the utilization rate of the Turbo decoder is improved.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (8)
1. A multi-bit parallel checking method, characterized in that it is applied to a Turbo decoder, said method comprising:
in the half iterative decoding process of the Turbo decoder, determining hard decision bits which are output by each decoding unit in the Turbo decoder at the same time;
when each decoding unit outputs at least one hard decision bit at the same time, performing cyclic redundancy check according to the hard decision bit output by each decoding unit at the same time;
and performing cyclic redundancy check according to the hard decision bits simultaneously output by each decoding unit, including:
comparing the hard decision bits output by each decoding unit simultaneously with the corresponding hard decision bits output in the previous half iterative decoding process to obtain updated hard decision bits corresponding to each decoding unit;
determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit;
calculating according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a verification result;
wherein the calculation parameters are determined according to the following formula:
，
wherein,for the calculated parameter, 0.ltoreq.i.ltoreq.P-1, P being the number of decoding units,/>，，/>X is an element on a finite field, M isAnd the ratio between the length of the data block and the number of the decoding units in the semi-iterative decoding process is mod, modulo operation is performed, and g (x) is a cyclic redundancy check generating polynomial.
2. The multi-bit parallel checking method according to claim 1, wherein when comparing the hard decision bits outputted by each decoding unit simultaneously with the corresponding hard decision bits outputted in the previous half iterative decoding process, the same bits are set to 0 to obtain updated hard decision bits corresponding to each decoding unit.
3. The multi-bit parallel checking method according to claim 1, wherein determining the lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit comprises:
determining a first lookup table according to an offset address corresponding to each hard decision bit for each decoding unit;
establishing a relation table between the hard decision bit of each decoding unit and an output lookup table according to the first lookup table;
and determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the relation table.
4. A multi-bit parallel checking method according to claim 3, wherein for each decoding unit, determining a first lookup table from the offset address corresponding to each hard decision bit comprises:
performing modular operation on the offset address corresponding to each decoding unit to obtain a first modular operation result;
dividing the first modular operation result into a plurality of phases, wherein the number of the phases is the same as the number of offset addresses corresponding to each decoding unit;
and reading out a lookup table of each phase according to the offset address corresponding to each hard decision bit.
5. The multi-bit parallel checking method according to claim 1, wherein the calculating according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain the checking result comprises:
performing convolution operation on the lookup table corresponding to each decoding unit and the calculation parameters corresponding to each decoding unit to obtain a plurality of convolution operation results;
performing accumulation operation on the convolution operation results to obtain an accumulation operation result;
performing modulo-2 operation on the accumulated operation result to obtain a second modulo operation result;
and repeatedly executing M times, and carrying out modulo-2 operation on a second modulo operation result obtained by the M times to obtain the verification result, wherein M is the ratio of the length of the data block in the half iterative decoding process to the number of the decoding units.
6. A computer readable storage medium, characterized in that a multi-bit parallel check program is stored thereon, which multi-bit parallel check program, when executed by a processor, implements the multi-bit parallel check method according to any of claims 1-5.
7. A Turbo decoder comprising a memory, a processor and a multi-bit parallel check program stored on the memory and executable on the processor, wherein the processor implements the multi-bit parallel check method according to any one of claims 1-5 when executing the multi-bit parallel check program.
8. A multi-bit parallel checking device for use in a Turbo decoder, said device comprising:
the determining module is used for determining hard decision bits which are output by each decoding unit in the Turbo decoder simultaneously in the half-iteration decoding process of the Turbo decoder;
the checking module is used for performing cyclic redundancy check according to the hard decision bits output by each decoding unit at the same time when each decoding unit outputs at least one hard decision bit at the same time;
the verification module is specifically used for: comparing the hard decision bits output by each decoding unit simultaneously with the corresponding hard decision bits output in the previous half iterative decoding process to obtain updated hard decision bits corresponding to each decoding unit;
determining a lookup table corresponding to each decoding unit according to the updated hard decision bit corresponding to each decoding unit and the offset address corresponding to each hard decision bit;
calculating according to the lookup table corresponding to each decoding unit and the predetermined calculation parameters to obtain a verification result;
wherein the calculation parameters are determined according to the following formula:
，
wherein,for the calculated parameter, 0.ltoreq.i.ltoreq.P-1, P being the number of decoding units,/>，，/>X is an element on a finite field, M is a ratio between a length of a data block and the number of decoding units in the semi-iterative decoding process, mod is a modular operation, and g (x) is a generator polynomial of cyclic redundancy check.
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