CN108768407A - A kind of Hard decision decoding device framework of low hardware cost, high-throughput - Google Patents
A kind of Hard decision decoding device framework of low hardware cost, high-throughput Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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Abstract
The present invention relates to a kind of low hardware cost, the Hard decision decoding device frameworks of high-throughput, realize that improvements include following several aspects based on mCS-RiBM Hard decision decoding device frameworks：(1) function of SC modules is realized using parallel organization；(2) second step of decoding process is to carry out key equation solving, folding is introduced into the KES modules based on mCS-RiBM algorithms, the two neighboring processing unit using identical update mode is fused into a collapsible processing unit, general multipliers are substituted for pipeline multiplier using weight timing technology；(3) after completing key equation solving, obtained error location polynomial and wrong estimate multinomial are admitted to CSEE modules, and CSEE modules are also designed to two degree of parallel architectures.
Description
Technical field
The invention belongs to the error control coding field in channel coding, it is related to a kind of low hardware cost, high-throughput
Hard decision decoding device framework.
Background technology
The development of information-intensive society, the requirement to data transmission credibility increasingly improve, how to control and introduced by transmission channel
Mistake, ensure that the transmitting of data becomes system design the problem of must paying close attention to.From the transmission reason of Shannon in 1948
After appearance, error control coding becomes the research hotspot for ensureing reliable data transmission.As a kind of important mistake control
Code processed, Reed-Solomon (Reed-Solomon, RS) code are extensive with its outstanding error correcting capability and relatively simple construction
Applied to numerous areas such as data storage, digital video broadcasting, survey of deep space, wireless communication, wireless MANs.
The decoding algorithm of RS codes mainly has two major classes：Soft decision decoding algorithm and Hard decision decoding algorithm.Although hard decision
Cannot obtain with the comparable decoding gain of soft-decision, but decoding algorithm and VLSI realize it is all fairly simple, therefore as current
Industrial realization in mainstream algorithm.Hard decision RS decoders include mainly three modules：Syndrome computation (Syndrome
Computation, SC), key equation solving (KeyEquation Solver, KES), money search with wrong estimate (Chien
Search and Error Evaluation, CSEE).As most classical KES algorithms, RiBM (Reformulated
Inversionless Berlekamp-Massey) hardware structure of algorithm contains the homogeneous processing units of 3t+1
(ProcessingElement, PE), queueing discipline, it is only necessary to 2t clock cycle can complete error location polynomial and
The polynomial calculating of wrong estimate, in the present note, t represents the error correcting capability of RS codes.It is derived on the basis of RiBM algorithms
mCS-RiBM(modified Compensated Simplified-Reformulated inversionless
Berlekamp-Massey) algorithm eliminates the processing unit of several redundancies, significantly reduces hardware resource consumption.
It is worth noting that, in existing Hard decision decoding device framework, the minimum delay of KES modules is 2t-1 clock
When period, the very little for the n clock cycle of delay of other two modules, thus KES modules have a large amount of idle
Between, cause the profligacy of hardware resource.In addition, due to including that 1 group of multiplier-adder combines (2 gals in each PE
The domains Luo Hua multiplier and 1 Galois field adder), thus in KES modules be critical path delay longest in entire decoder,
Occupy the most module of hardware resource.In conclusion the decoder area occupied being directly realized by is big, area utilization is low, handles up
Rate is low.Therefore a kind of Hard decision decoding device architecture design method that can effectively reduce hardware cost, improve throughput needs
To further research.
Invention content
The purpose of the present invention is to provide a kind of low hardware cost, the Hard decision decoding device frameworks of high-throughput, are ensureing
Under the premise of decoding performance, the quantity of the multiplier and adder that occupy great amount of hardware resources is reduced, while shortening decoder
Critical path delay, to realize the target for reducing area, improving throughput.Main technical schemes are as follows：
The Hard decision decoding device framework of a kind of low hardware cost, high-throughput is based on mCS-RiBM Hard decision decoding device framves
Structure realizes that improvements include following several aspects：
(1) syndrome is divided into odd number part and even segments is distinguished by the function that SC modules are realized using parallel organization
It is calculated, is finally summed up, calculate 2t syndrome, the parallelism factor of syndrome computation circuit is 2, according to from a high position
Sequence to low level sequentially inputs every road symbol, and within a clock cycle, syndrome computation circuit handles 2 symbols simultaneously,
After n/2 clock cycle, calculated syndrome is sent to KES modules come the operation after completing；
(2) second step of decoding process is to carry out key equation solving, and folding is introduced and is based on mCS-RiBM algorithms
KES modules, the two neighboring processing unit using identical update mode is fused into a collapsible processing unit,
That is, by the preceding t processing unit collapsible PE1 of two twenty percents only with RiBM update modes, RiBM can be used more by rear t+1
New paragon and the collapsible PE4 of two twenty percent of processing unit that CS-RiBM update modes can be used；In addition, designing and collapsible place
The collapsible compensating unit that reason unit matches is generated using three kinds of renewal model cycles, transmits the multinomial coefficient being related to,
In collapsible processing unit and collapsible compensating unit, register series is compared had increase originally, utilized weight timing technology
General multipliers are substituted for pipeline multiplier；
(3) after completing key equation solving, obtained error location polynomial and wrong estimate multinomial are admitted to
CSEE modules, CSEE modules are also designed to two degree of parallel architectures, i.e., within a clock cycle, circuit can handle 2 simultaneously
Symbol, CSEE modules need n/2 clock cycle to calculate all errors presents and error value.
The present invention will succeed for the problem that the decoder hardware based on mCS-RiBM algorithms is of high cost, throughput is low
Be combined applied to the folding of other hard decision algorithms, weight timing technology etc. and mCS-RiBM algorithms, at the same SC modules and
CSEE modules use pipeline parallel method framework.It is based ultimately upon the processing that a small amount of deep pipeline is only existed in the framework of new algorithm
Unit and a compensating unit corresponding with original mCS-RiBM algorithms, to reduce decoder area, saved hardware at
This.And critical path delay is shortened, substantially increase the throughput of decoder.
Description of the drawings
Fig. 1 is two degree of parallel SC modules after being modified to Traditional parallel SC units.
Fig. 2 is collapsible PE1 and PE4.(1) collapsible PE1；(2) collapsible PE4.
Fig. 3 is collapsible CS circuit diagrams.
Fig. 4 is two degree of parallel money search and its basic unit.
Fig. 5 is 16 raceway groove, two degree of parallel FEC frameworks based on RS codes.
Specific implementation mode
The present invention mainly on the basis of mCS-RiBM Hard decision decoding device frameworks, is reduced by introducing folding
The use of multiplier and adder greatly reduces the hardware cost of decoder, improves the utilization rate of hardware resource；Lead to simultaneously
The introducing of overweight timing technology further shortens the critical path delay of overall architecture, is finally obtained higher throughput.
Meanwhile to be suitable for high speed decoder, syndrome computation module, money search have merged concurrent technique and stream with wrong estimate module
Waterline technology.
The present invention is described in detail with example below in conjunction with the accompanying drawings.For convenience, most wide with purposes without exception in this explanation
General RS (255,239) code (n=255, t=8) is illustrated as example.
(1) first step of decoding process is to calculate 2t syndrome Si, 0≤i≤2t-1, if 2t syndrome is all
0, then mean that an error has occurred, it is on the contrary then represent and occur mistake in the transmission.The most basic formula of syndrome computation is：In order to improve the speed and throughput of decoder, the present invention is using fusion flowing water
Two degree of parallel organizations of line technology realize the function of SC modules.Above-mentioned formula is changing into following form：si=(... (rn-1
αi(q-1)+rn-2αi(q-2)+…+rn-q+1αi+rn-q)αiq+…+rq)αiq+rq-1αi(q-1)+rq-2αi(q-2)+…+r1αi+r0, the circuit
Parallelism factor is q, and every road symbol, within a clock cycle, syndrome are sequentially input according to the sequence from a high position to low level
Counting circuit can handle q symbol simultaneously, and in this way after n/q period, the result in register is exactly required
Terminal check subvalue.But this traditional more degree parallel organizations can undoubtedly increase the critical path delay of module, in order to solve
Syndrome is divided into odd number part and even segments is respectively calculated, finally summed up by this problem.I.e.：si=R (αi)
=Rodd(αi)+Reven(αi), Fig. 1 illustrates two degree of parallel modules after being modified to Traditional parallel SC units.Simultaneously at two degree
In row structure, 128 clock cycle is needed to complete the calculating of syndrome.Calculated syndrome is sent to KES modules and has come
At operation later.
(2) the KES frameworks folded.Due to mCS-RiBM algorithms about the part of key equation solving include two in terms of in
Hold：Processing unit and compensating unit, therefore the mCS-RiBM frameworks folded also include these two aspects.
The processing unit of folding：Obviously, former framework is folded up, occupies the multiplier and adder number of more resource
It will die-off, and since KES postpones to increase, can arrange in pairs or groups and use with SC the and CSEE modules of relatively low degree of parallelism.To sum up, entire framework
The gross area will greatly reduce.It is worth noting that, with the increase of folding factor, throughput will be reduced accordingly, this be because
Higher to fold degree, whole time delay increases therewith.By to being analyzed using the case where different folding factors it is found that being folded
The factor can obtain the optimal compromise of area and throughput when being 2.It is in the design, two adjacent uses are identical more
The processing unit of new paragon is merged, i.e., preceding t two twenty percents of processing unit only with RiBM update modes is collapsible
PE1 by rear t+1 or using RiBM update modes or uses two twenty percent of processing unit of CS-RiBM update modes collapsible
PE4.Folding processing unit is as shown in Figure 2.Modified collapsible processing unit contains 2 assembly line galois fields and multiplies
Musical instruments used in a Buddhist or Taoist mass, 1 Galois field adder, 2 2-1 selectors, 15 latch.Collapsible PE4 and collapsible PE1 is slightly different
3 selectors that have been more.Two rows latch δ in processing unit after foldingk l#And θk l#It is respectively used to storage multinomial Δ
The coefficient of (r, z) and Θ (r, z), in the present note, Δ (r, z) refers to error location polynomial Λ (r, z) and syndrome is multinomial
The product of formula S (z), Θ (r, z) refer to the product of intermediate multinomial B (r, z) and S (z).Subscript k and unfolded preceding processing list
First serial number is consistent, and subscript l then indicates raceway groove serial number.In folding framework, since each iteration is all that 4 raceway grooves serially execute, because
This starts Θ (r, the z) coefficient for exporting first raceway groove after 15 × 2 × 4-3=117 clock cycle, 124 clock weeks
An iteration is completed after phase.
The compensating unit unit of folding：In mCS-RiBM algorithms, compensating unit is used for storing spilling coefficient, output compensation
Coefficient δcAnd processing unit is passed at the time of suitable.Fig. 3 illustrates collapsible compensating unit circuit diagram, it can be seen that each
It can be selected D in a clock cycle3, D4Or DMIn data leftmost register, i.e. compensating unit are sent by selector
There are L in framework3, L4And LmThree kinds of feedback cycle circuits.Since folding factor is 2 in the folding framework, and it is that 4 raceway grooves are parallel,
So iteration is completed to need 8 clock cycle every time.In proposition suitable for the compensating unit unit for folding framework, there are three
Kind renewal model is used to recycle generation, transmits the multinomial coefficient being related to.Pattern 1 is applied to k (r) >=0&flag (r) >=0
Part (k (r) and flag (r) is the intermediate variable in mCS-RiBM control units), it is therefore an objective to which current coefficient is moved to the left one
Position simultaneously receives a new spilling coefficient after the completion of current iteration.Specific implementation step is that shilling current coefficient passes through a L4
Backfeed loop, coefficient returns to original position after 4 periods in this way, and later since the 5th clock cycle, it is anti-to complete a L3
It is fed back to road, at the same time D5And DmValue remain unchanged, when the 8th clock cycle arrives, by new spilling coefficient θfIt is sent into most
The register on the right.Pattern 2 is applied to 0 conditions of k (r) <, it is therefore an objective to current whole coefficients are multiplied by γ (r) and move right one
Position.Concrete operation step is that current coefficient is enabled to pass through Lm backfeed loops in preceding 4 clock cycle, whole at the 5th period
Data start to complete L4Backfeed loop.Pattern 3 is applied under the conditions of k (r) >=0&flag (r) < 0, and effect is once to change
All coefficients keep original position motionless after the completion of generation.Current coefficient experience L twice is enabled in the secondary iteration4Backfeed loop,
Keep D simultaneously5Value it is constant.
(3) after completing key equation solving, obtained error location polynomial and wrong estimate multinomial are admitted to
CSEE modules.Wherein, money search module calculates the root of error location polynomial.Good fortune Buddhist nun algoritic module is then to calculate each mistake
Value.In order to be suitable for High-Speed RS decoder, CSEE modules are also required to use pipelining.Since there are backfeed loops, flowing
Waterline money is searched for adjusts sequential with needing to adjust the coefficient of α in good fortune Buddhist nun's algorithm structure.Fig. 4 shows two degree of parallel pipeline money
The framework of search module.Good fortune Buddhist nun algoritic module is only that C8 units are removed in original basis, and rest part is substantially similar.It is exporting
First receives have the delay in 7 periods before code word, and the calculating for completing all error values needs 128 clock cycle.
Fig. 5 is that 16 raceway groove proposed in this paper spends parallel RS-FEC frameworks more, contains the more two degree of parallel RS of four 4 raceway grooves and translates
Code device.Q in figure represents degree of parallelism.Wherein, syndrome computation needs 128 clock cycle, and collapsible KES frameworks are the 245th
A clock cycle starts to export the error location polynomial and the polynomial coefficient of wrong estimate of first raceway groove, and output is tied
Fruit is sent into CSEE modules, and all error location polynomials and wrong estimate multinomial coefficient are completed after 252 clock cycle
Output.
Claims (1)
1. the Hard decision decoding device framework of a kind of low hardware cost, high-throughput is based on mCS-RiBM Hard decision decoding device frameworks
It realizes, improvements include following several aspects：
(1) syndrome is divided into odd number part and even segments and carried out respectively by the function that SC modules are realized using parallel organization
It calculates, finally sums up, calculate 2t syndrome, the parallelism factor of syndrome computation circuit is 2, according to from a high position to low
The sequence of position sequentially inputs every road symbol, and within a clock cycle, syndrome computation circuit handles 2 symbols simultaneously, is passing through
After spending n/2 clock cycle, calculated syndrome is sent to KES modules come the operation after completing；
(2) second step of decoding process is to carry out key equation solving, and folding is introduced the KES based on mCS-RiBM algorithms
The two neighboring processing unit using identical update mode is fused into a collapsible processing unit by module, that is, will
The preceding t processing unit collapsible PE1 of two twenty percents only with RiBM update modes can use the update sides RiBM by rear t+1
Formula and the collapsible PE4 of two twenty percent of processing unit that CS-RiBM update modes can be used；In addition, designing single with collapsible processing
The collapsible compensating unit that member matches is generated using three kinds of renewal model cycles, transmits the multinomial coefficient being related to, rolled over
In stacked processing unit and collapsible compensating unit, register series is compared had increase originally, will be general using weight timing technology
Logical multiplier is substituted for pipeline multiplier；
(3) after completing key equation solving, obtained error location polynomial and wrong estimate multinomial are admitted to CSEE
Module, CSEE modules are also designed to two degree of parallel architectures, i.e., within a clock cycle, circuit can handle 2 symbols simultaneously,
CSEE modules need n/2 clock cycle to calculate all errors presents and error value.
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Cited By (3)
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| CN110971244A (en) * | 2019-10-18 | 2020-04-07 | 天津大学 | Forward error correction decoding decoder based on burst error detection |
| CN112436842A (en) * | 2021-01-27 | 2021-03-02 | 睿迪纳(南京)电子科技有限公司 | Method for realizing signal processing device based on fractional folding |
| CN113691263A (en) * | 2021-08-19 | 2021-11-23 | Oppo广东移动通信有限公司 | Multi-bit parallel checking method and device, storage medium and Turbo decoder |
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