CN113690233B - Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof - Google Patents
Unidirectional ESD protection device capable of enhancing current capacity and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000002708 enhancing effect Effects 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 197
- 229910052751 metal Inorganic materials 0.000 claims abstract description 96
- 239000002184 metal Substances 0.000 claims abstract description 96
- 238000001259 photo etching Methods 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000002161 passivation Methods 0.000 claims abstract description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 50
- 229910052796 boron Inorganic materials 0.000 claims description 50
- 238000002513 implantation Methods 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 21
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 14
- 239000000956 alloy Substances 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 7
- -1 aluminum silicon copper Chemical compound 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000013021 overheating Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009024 positive feedback mechanism Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a unidirectional ESD protection device capable of enhancing the current capacity and a manufacturing method thereof, comprising a P-type monocrystalline material, an N+ diffusion region, a P+ diffusion region, a P diffusion region, a surface passivation layer, a metal layer I and a metal layer II, wherein the concentration of the P diffusion region between the N+ diffusion region below the metal layer I and the N+ diffusion region below the metal layer II is gradually reduced, and in the design of a photoetching window of the P diffusion region, the size of the window can be named as follows: the dimensions of the window spacing may be named in order of L1, L2, L3, L4, L5: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region, wherein the concentration of the P diffusion region gradually decreases from an N+ diffusion region (below a metal layer II) to an N+ diffusion region (below a metal layer I), a built-in electric field from left to right is formed, so that higher through-flow capacity can be obtained, and compared with a conventional structure, the through-flow capacity can be improved by 20-40% by reasonably designing the photoetching window size of the P diffusion region.
Description
Technical Field
The invention relates to the field of electronic science and technology, in particular to a unidirectional ESD protection device capable of enhancing the current capacity and a manufacturing method thereof.
Background
Electrostatic discharge (ESD) phenomena are a significant cause of damage and even failure of integrated circuit products. Integrated circuit products are extremely susceptible to ESD during their production, manufacture, assembly and operation, resulting in internal damage and reduced reliability. Therefore, research into high-performance and high-reliability ESD protection devices has a crucial role in improving yield and reliability of integrated circuits. In general, the design of ESD protection devices requires consideration of the following three aspects: firstly, the ESD protection device can discharge large current; secondly, the ESD protection device has a specific trigger voltage and a low holding voltage. Thirdly, the ESD protection device requires ultra-low parasitic capacitance.
Devices commonly used as ESD protection are diodes, BJTs (transistors), SCR (silicon controlled rectifier), etc. The BJT structure achieves the shallow retrace characteristic due to the injection modulation effect. The SCR structure realizes deep flyback characteristics through a positive feedback mechanism of PNPN. Therefore, the SCR structure is lowest and the BJT structure is next highest from the residual voltage parameter. The voltage after deep retrace of the SCR structure is only about 2V and is obviously lower than common power supply voltages of 3.3V, 5V and the like, so that the SCR structure device is always in latch-up effect and cannot recover to a blocking state after the ESD pulse is released, and the SCR structure device is limited in application. Therefore, from a comprehensive consideration, the BJT structure is a relatively reasonable choice, the residual voltage parameter is reduced, and the application scene limitation is relatively small. For the unidirectional ESD protection device with the BJT structure, an n+ diffusion region 102, a p+ diffusion region 103, a P diffusion region 104 and a surface passivation layer 105 are formed on a P-type monocrystalline material 101, so that the surface passivation layer 105 plays a role in dielectric isolation, and a metal layer 107 and a metal layer 106 respectively represent two electrode ports of the unidirectional ESD protection device, namely an anode and a cathode, so that the current passing capability is low.
The prior art discloses a unidirectional ESD protection device with high current capacity and a manufacturing method thereof (publication No. CN 111599805A), the unidirectional ESD protection device comprises an N-type substrate material, an N-type epitaxial layer is epitaxially arranged on the front surface of the N-type substrate material, a P-type diffusion region with PN junctions with different depths is arranged in the N-type epitaxial layer, an isolation medium layer is deposited on the N-type epitaxial layer, a front metal region is sputtered or evaporated on the front surface outside the isolation medium layer and the P-type diffusion region, and the back surface of the N-type substrate material is thinned and metallized to form a back metal region. The preparation method comprises the following steps: preparing an N-type substrate material, and growing an N-type epitaxial layer; growing a sacrificial oxide layer on the N-type epitaxial layer to obtain PN junctions with different depths; front boron is implanted to form a P-type diffusion region; depositing an isolation medium layer on the front surface, and photoetching the front surface to form a contact hole area; sputtering or evaporating metal on the front surface; and forming a front metal region and a back metal region, and forming deep and shallow junctions with different junction depths, so as to obtain higher current capacity, wherein the introduced conductivity modulation effect is not strong, and the current capacity is required to be optimized and enhanced.
Disclosure of Invention
The invention aims to provide a unidirectional ESD protection device and a manufacturing method thereof, wherein the unidirectional ESD protection device can enhance the current passing capability under the conditions of unchanged chip area and unchanged chip processing procedures.
The technical scheme adopted by the invention is as follows:
the utility model provides a unidirectional ESD protection device that can strengthen through-flow ability, includes P type monocrystalline material, N+ diffusion zone, P+ diffusion zone, P diffusion zone, surface passivation layer, metal layer I, metal layer II, P type monocrystalline material interior top is established to N+ diffusion zone, P diffusion zone, N+ diffusion zone, P+ diffusion zone in proper order, and P type monocrystalline material top surface is equipped with metal layer I, metal layer II, be equipped with the surface passivation zone between metal layer I and N+ diffusion zone edge, P diffusion zone and the N+ diffusion zone juncture respectively, metal layer II establishes the surface passivation zone respectively at N+ diffusion zone and P diffusion zone juncture, N+ diffusion zone and P+ diffusion zone juncture, P+ diffusion zone edge, P diffusion zone concentration gradually reduces between N+ diffusion zone below metal layer I to N+ diffusion zone below metal layer II.
A manufacturing method of a unidirectional ESD protection device capable of enhancing current capacity comprises the following steps:
step 1: preparing P-type monocrystalline material with crystal orientation of <100> and resistivity of 5-50Ω cm;
step 2: growing a layer of sacrificial oxide layer with the thickness of 680-1000A, forming N+ diffusion region pattern by front photoetching, and performing front phosphorus implantation with the phosphorus implantation dosage of 3E15-8E15cm -2 The energy is 80-120KeV;
step 3: front side photoetching to form P+ diffusion regionGraph, front side boron implantation, boron promotion, formation of N+ diffusion region and P+ diffusion region, boron implantation dosage of 1E15-3E15cm -2 The energy is 30-80KeV, the boron pushing temperature is 1050-1150 ℃, and the time is 60-180min, so that a P+ diffusion region and an N+ diffusion region are formed;
step 4: forming a P diffusion region pattern by front photoetching, and forming a P diffusion region photoetching pattern;
step 5: front side boron implantation, boron promotion, P diffusion region formation, boron implantation dose of 1E14-5E14cm -2 The energy is 50-100KeV, the boron propulsion temperature is 1000-1100 ℃, the time is 30-90min, a P diffusion region is formed, and the boron injection and boron propulsion process conditions are selected and optimized according to the PN junction breakdown voltage requirements;
step 6: depositing an isolation medium layer on the front surface, and photoetching a contact hole area on the front surface, wherein the contact hole area is as follows: l1, L2, L3, L4, L5 positions, the corresponding contact hole spacing regions are: d1, D2, D3, D4, the regions being isolation dielectric layers;
step 7: the front side is sputtered or evaporated with metal, alloy.
Further, the isolation medium layer in the step 6 is tetraethoxysilane TEOS, the thickness is 5000-10000A, and after photoetching the contact hole, a layer of TI/TIN is deposited, so that the contact resistance is reduced, and the failure proportion of metal overheating can be effectively reduced.
Preferably, the isolation dielectric layer in step 6 is tetraethoxysilane TEOS, the thickness is 7000A, and a layer of TI/TIN is deposited after contact hole lithography.
Further, the metal sputtered or evaporated on the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2-4um, the temperature of the alloy is 360-430 ℃ and the time is 25-45min.
Preferably, the metal sputtered or evaporated on the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35min.
The invention has the advantages that: 1. the invention can obtain higher through-flow capacity under the condition of unchanged chip area and unchanged chip processing procedures;
2. in the photoetching process of the P diffusion region, photoetching windows with different sizes are designed, and the spacing between the large window and the small window is reasonably optimized, so that after the P diffusion region is subjected to the diffusion process, the gradual change depth which gradually decreases from the N+ diffusion region (below the metal layer II) to the N+ diffusion region (below the metal layer I) can be obtained. In the design of P-diffusion photolithographic windows, the dimensions of the windows may be sequentially named: the dimensions of the window spacing may be named in order of L1, L2, L3, L4, L5: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region, wherein the concentration of the P diffusion region gradually decreases from an N+ diffusion region (below a metal layer II) to an N+ diffusion region (below a metal layer I), a built-in electric field from left to right is formed, so that higher through-flow capacity can be obtained, and compared with a conventional structure, the through-flow capacity can be improved by 20-40% by reasonably designing the photoetching window size of the P diffusion region.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a cross-sectional structural view of the present invention;
FIG. 2 is a schematic diagram of the IV characteristics of the present invention;
FIG. 3 is a schematic process diagram of step 1 of the present invention;
FIG. 4 is a schematic process diagram of step 2 of the present invention;
FIG. 5 is a schematic process diagram of step 3 of the present invention;
FIG. 6 is a schematic process diagram of step 4 of the present invention;
FIG. 7 is a schematic process diagram of step 5 of the present invention.
Wherein: 101. p-type single crystal material; 102. an N+ diffusion region; 103. a P+ diffusion region; 104. a P diffusion region; 105. a surface passivation layer; 106. a metal layer I; 107. a metal layer II; 108. a sacrificial oxide layer; 109. and isolating the dielectric layer.
Detailed Description
Example 1
As shown in FIGS. 1-7, the unidirectional ESD protection device capable of enhancing the current capacity comprises a P-type monocrystalline material 101, an N+ diffusion region 102, a P+ diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer I106 and a metal layer II 107, wherein the top inside the P-type monocrystalline material 101 is sequentially provided with the N+ diffusion region 102, the P diffusion region 104, the N+ diffusion region 102 and the P+ diffusion region 103, the top surface of the P-type monocrystalline material 101 is provided with the metal layer I106 and the metal layer II 107, a surface passivation region 105 is respectively arranged between the edges of the metal layer I106 and the N+ diffusion region 102 and between the P diffusion region 104 and the boundary of the P+ diffusion region 104, the boundary of the N+ diffusion region 102 and the P+ diffusion region 103, the surface passivation region 105 is respectively arranged at the edges of the P+ diffusion region 103, and the concentration between the N+ diffusion region 102 below the metal layer I16 and the N+ diffusion region 102 is gradually reduced, so that a built-in electric field from left to right is formed, and the chip can not reach the current capacity through the conventional chip, the current capacity is improved by designing the invention, compared with the conventional chip, the current capacity is improved, and the current capacity is 40, and the current capacity is improved by the conventional through the design.
When the metal layer II 107 is connected with high potential and the metal layer I106 is connected with low potential, current sequentially passes through the P+ diffusion region 103, the P-type monocrystalline material 101 and the N+ diffusion region 102 (below the metal layer I106), and the diode is characterized by forward conduction, and when the metal layer I106 is connected with high potential and the metal layer II 107 is connected with low potential, current sequentially passes through the N+ diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N+ diffusion region 102 (below the metal layer II 107), and the diode is characterized by shallow flyback breakdown.
A manufacturing method of a unidirectional ESD protection device capable of enhancing current capacity comprises the following steps:
step 1: preparing a P-type monocrystalline material 101, wherein the crystal direction is <100>, and the resistivity is 5 omega cm;
step 2: growing a layer of sacrificial oxide layer 108, wherein the thickness of the sacrificial oxide layer 108 is 680A, forming an N+ diffusion region 102 pattern by front photoetching, and performing front phosphorus implantation with a phosphorus implantation dosage of 3E15cm -2 The energy is 80KeV;
step 3: forming P+ diffusion region 103 pattern by front photoetching, front boron implantation, boron promotion, forming N+ diffusion region 102, P+ diffusion region 103, and boron implantation dosage of 1E15-3E15cm -2 Energy of 30KeV, boron drive temperature 1050 ℃, time 60min, forming P+ diffusion region 103, N+ diffusion region 102;
step 4: forming a P diffusion region 104 pattern by front side photoetching, forming a P diffusion region 104 photoetching pattern, designing photoetching windows with different sizes in the photoetching process of the P diffusion region 104, and reasonably optimizing the spacing between the large and small windows, so that after the P diffusion region 104 is subjected to the diffusion process, gradually reduced gradual depth from an n+ diffusion region (below a metal layer II 107) to an n+ diffusion region (below a metal layer I106) can be obtained, as shown in fig. 6, in the design of the photoetching windows of the P diffusion region 104, the sizes of the windows can be sequentially named as: the dimensions of the window spacing may be named in order of L1, L2, L3, L4, L5: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
step 5: front side boron implantation, boron drive-in, to form P diffusion region 104, boron implant dose of 1E14cm -2 The energy is 50KeV, the boron advancing temperature is 1000 ℃ and the time is 30min, a P diffusion region 104 is formed, and the boron injecting and advancing process conditions are selected and optimized according to the PN junction breakdown voltage requirement;
step 6: as shown in fig. 6, an isolation dielectric layer is deposited on the front surface, and contact hole areas formed by front surface photoetching are as follows: l1, L2, L3, L4, L5 positions, the corresponding contact hole spacing regions are: d1, D2, D3, D4, are all isolation dielectric layers 109 in the regions;
step 7: the front side is sputtered or evaporated with metal, alloy.
Further, the isolation medium layer in the step 6 is tetraethoxysilane TEOS, the thickness is 5000-10000A, and after photoetching the contact hole, a layer of TI/TIN is deposited, so that the contact resistance is reduced, and the failure proportion of metal overheating can be effectively reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2um, the temperature of the alloy is 360 ℃, and the time is 25min.
Example 2
As shown in FIGS. 1-7, the unidirectional ESD protection device capable of enhancing the current capacity comprises a P-type monocrystalline material 101, an N+ diffusion region 102, a P+ diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer I106 and a metal layer II 107, wherein the top inside the P-type monocrystalline material 101 is sequentially provided with the N+ diffusion region 102, the P diffusion region 104, the N+ diffusion region 102 and the P+ diffusion region 103, the top surface of the P-type monocrystalline material 101 is provided with the metal layer I106 and the metal layer II 107, a surface passivation region 105 is respectively arranged between the edges of the metal layer I106 and the N+ diffusion region 102 and between the P diffusion region 104 and the boundary of the P+ diffusion region 104, the boundary of the N+ diffusion region 102 and the P+ diffusion region 103, the surface passivation region 105 is respectively arranged at the edges of the P+ diffusion region 103, and the concentration between the N+ diffusion region 102 below the metal layer I16 and the N+ diffusion region 102 is gradually reduced, so that a built-in electric field from left to right is formed, and the chip can not reach the current capacity through the conventional chip, the current capacity is improved by designing the invention, compared with the conventional chip, the current capacity is improved, and the current capacity is 40, and the current capacity is improved by the conventional through the design.
When the metal layer II 107 is connected with high potential and the metal layer I106 is connected with low potential, current sequentially passes through the P+ diffusion region 103, the P-type monocrystalline material 101 and the N+ diffusion region 102 (below the metal layer I106), and the diode is characterized by forward conduction, and when the metal layer I106 is connected with high potential and the metal layer II 107 is connected with low potential, current sequentially passes through the N+ diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N+ diffusion region 102 (below the metal layer II 107), and the diode is characterized by shallow flyback breakdown.
A manufacturing method of a unidirectional ESD protection device capable of enhancing current capacity comprises the following steps:
step 1: preparing a P-type monocrystalline material 101, wherein the crystal direction is <100>, and the resistivity is 50Ω & cm;
step 2: growing a layer of sacrificial oxide layer 108, wherein the thickness of the sacrificial oxide layer 108 is 1000A, forming an N+ diffusion region 102 pattern by front photoetching, and performing front phosphorus implantation with the phosphorus implantation dosage of 8E15cm -2 The energy is 120KeV;
step 3: forming P+ diffusion region 103 pattern by front photoetching, front boron implantation, boron promotion, and N+ diffusionRegion 102, P+ diffusion region 103, boron implant dose of 3E15cm -2 The energy is 80KeV, the boron advancing temperature is 1150 ℃, and the time is 180min, so that a P+ diffusion region 103 and an N+ diffusion region 102 are formed;
step 4: forming a P diffusion region 104 pattern by front side photoetching, forming a P diffusion region 104 photoetching pattern, designing photoetching windows with different sizes in the photoetching process of the P diffusion region 104, and reasonably optimizing the spacing between the large and small windows, so that after the P diffusion region 104 is subjected to the diffusion process, gradually reduced gradual depth from an n+ diffusion region (below a metal layer II 107) to an n+ diffusion region (below a metal layer I106) can be obtained, as shown in fig. 6, in the design of the photoetching windows of the P diffusion region 104, the sizes of the windows can be sequentially named as: the dimensions of the window spacing may be named in order of L1, L2, L3, L4, L5: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
step 5: front side boron implantation, boron drive-in, forming P diffusion region 104, boron implant dose of 5E14cm -2 The energy is 100KeV, the boron propulsion temperature is 1100 ℃, the time is 90min, a P diffusion region 104 is formed, and the boron injection and boron propulsion process conditions are selectively optimized according to the PN junction breakdown voltage requirements;
step 6: as shown in fig. 6, an isolation dielectric layer is deposited on the front surface, and contact hole areas formed by front surface photoetching are as follows: l1, L2, L3, L4, L5 positions, the corresponding contact hole spacing regions are: d1, D2, D3, D4, are all isolation dielectric layers 109 in the regions;
step 7: the front side is sputtered or evaporated with metal, alloy.
Further, the isolation dielectric layer in the step 6 is tetraethoxysilane TEOS, the thickness is 10000A, and after photoetching the contact hole, a layer of TI/TIN is deposited, so that the contact resistance is reduced, and the failure proportion of metal overheating can be effectively reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 4um, the temperature of the alloy is 430 ℃ and the time is 45min.
Example 3
As shown in FIGS. 1-7, the unidirectional ESD protection device capable of enhancing the current capacity comprises a P-type monocrystalline material 101, an N+ diffusion region 102, a P+ diffusion region 103, a P diffusion region 104, a surface passivation layer 105, a metal layer I106 and a metal layer II 107, wherein the top inside the P-type monocrystalline material 101 is sequentially provided with the N+ diffusion region 102, the P diffusion region 104, the N+ diffusion region 102 and the P+ diffusion region 103, the top surface of the P-type monocrystalline material 101 is provided with the metal layer I106 and the metal layer II 107, a surface passivation region 105 is respectively arranged between the edges of the metal layer I106 and the N+ diffusion region 102 and between the P diffusion region 104 and the boundary of the P+ diffusion region 104, the boundary of the N+ diffusion region 102 and the P+ diffusion region 103, the surface passivation region 105 is respectively arranged at the edges of the P+ diffusion region 103, and the concentration between the N+ diffusion region 102 below the metal layer I16 and the N+ diffusion region 102 is gradually reduced, so that a built-in electric field from left to right is formed, and the chip can not reach the current capacity through the conventional chip, the current capacity is improved by designing the invention, compared with the conventional chip, the current capacity is improved, and the current capacity is 40, and the current capacity is improved by the conventional through the design.
When the metal layer II 107 is connected with high potential and the metal layer I106 is connected with low potential, current sequentially passes through the P+ diffusion region 103, the P-type monocrystalline material 101 and the N+ diffusion region 102 (below the metal layer I106), and the diode is characterized by forward conduction, and when the metal layer I106 is connected with high potential and the metal layer II 107 is connected with low potential, current sequentially passes through the N+ diffusion region 102 (below the metal layer 106I), the P diffusion region 104 and the N+ diffusion region 102 (below the metal layer II 107), and the diode is characterized by shallow flyback breakdown.
A manufacturing method of a unidirectional ESD protection device capable of enhancing current capacity comprises the following steps:
step 1: preparing a P-type monocrystalline material 101, wherein the crystal direction is <100>, and the resistivity is 25 Ω & cm;
step 2: growing a layer of sacrificial oxide layer 108, wherein the thickness of the sacrificial oxide layer 108 is 840A, forming an N+ diffusion region 102 pattern by front photoetching, and performing front phosphorus implantation with a phosphorus implantation dosage of 6E15cm -2 The energy is 100KeV;
step 3: front side lithographyForming P+ diffusion region 103 pattern, front boron implantation, boron promotion, forming N+ diffusion region 102, P+ diffusion region 103, boron implantation dose of 2E15cm -2 The energy is 55KeV, the boron advancing temperature is 1100 ℃, and the time is 120min, so that a P+ diffusion region 103 and an N+ diffusion region 102 are formed;
step 4: forming a P diffusion region 104 pattern by front side photoetching, forming a P diffusion region 104 photoetching pattern, designing photoetching windows with different sizes in the photoetching process of the P diffusion region 104, and reasonably optimizing the spacing between the large and small windows, so that after the P diffusion region 104 is subjected to the diffusion process, gradually reduced gradual depth from an n+ diffusion region (below a metal layer II 107) to an n+ diffusion region (below a metal layer I106) can be obtained, as shown in fig. 6, in the design of the photoetching windows of the P diffusion region 104, the sizes of the windows can be sequentially named as: the dimensions of the window spacing may be named in order of L1, L2, L3, L4, L5: d1, D2, D3, D4, L5> L4> L3> L2> L1, D1> D2> D3> D4, thereby obtaining a P diffusion region 104 as shown in fig. 6;
step 5: front side boron implantation, boron drive-in, to form P diffusion region 104, boron implant dose of 3E14cm -2 The energy is 70KeV, the boron advancing temperature is 1050 ℃, the time is 60min, a P diffusion region 104 is formed, and the boron injecting and advancing process conditions are selected and optimized according to the PN junction breakdown voltage requirement;
step 6: as shown in fig. 6, an isolation dielectric layer is deposited on the front surface, and contact hole areas formed by front surface photoetching are as follows: l1, L2, L3, L4, L5 positions, the corresponding contact hole spacing regions are: d1, D2, D3, D4, are all isolation dielectric layers 109 in the regions;
step 7: the front side is sputtered or evaporated with metal, alloy.
Further, in the step 6, the isolation medium layer is tetraethoxysilane TEOS, the thickness is 7000A, and after the contact hole is photoetched, a layer of TI/TIN is deposited, so that the contact resistance is reduced, and the failure proportion of metal overheat can be effectively reduced.
Further, the metal sputtered or evaporated from the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35min.
The above examples are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should be included in the scope of protection defined by the claims of the present invention without departing from the spirit of the design of the present invention.
Claims (5)
1. A method for manufacturing a unidirectional ESD protection device capable of enhancing the current passing capability, the protection device comprises a P-type monocrystalline material, an N+ diffusion region, a P+ diffusion region, a P diffusion region, a surface passivation layer, a metal layer I and a metal layer II, and is characterized in that: the top is set up into N+ diffusion zone, P diffusion zone, N+ diffusion zone, P+ diffusion zone in proper order in the P type monocrystalline material, and P type monocrystalline material top surface is equipped with metal level I, metal level II, be equipped with the surface passivation district respectively between metal level I and N+ diffusion zone edge, P diffusion zone and N+ diffusion zone juncture, metal level II establishes the surface passivation district respectively at N+ diffusion zone and P diffusion zone juncture, N+ diffusion zone and P+ diffusion zone juncture, P+ diffusion zone edge, P diffusion zone concentration gradually increases between N+ diffusion zone to metal level II below in metal level I, the manufacturing method of protection device includes the following steps:
step 1: preparing P-type monocrystalline material with crystal orientation of <100> and resistivity of 5-50Ω cm;
step 2: growing a layer of sacrificial oxide layer on the front surface, wherein the thickness of the sacrificial oxide layer is 680-1000A, forming an N+ diffusion region pattern by front surface photoetching, and performing front surface phosphorus injection, wherein the phosphorus injection dosage is 3E15-8E15cm & lt-2 & gt, and the energy is 80-120KeV;
step 3: forming P+ diffusion region graph by front photoetching, front boron injection and boron promotion, forming N+ diffusion region and P+ diffusion region, wherein the boron injection dosage is 1E15-3E15cm < -2 >, the energy is 30-80KeV, the boron promotion temperature is 1050-1150 ℃, and the boron promotion time is 60-180min, forming P+ diffusion region and N+ diffusion region;
step 4: forming a P diffusion region pattern by front photoetching, and forming a P diffusion region photoetching pattern;
step 5: front side boron implantation and boron propulsion to form a P diffusion region, wherein the boron implantation dosage is 1E14-5E14cm < -2 >, the energy is 50-100KeV, the boron propulsion temperature is 1000-1100 ℃ and the time is 30-90min, the P diffusion region is formed, and the process conditions of boron implantation and boron propulsion are selectively optimized according to the requirement of PN junction breakdown voltage;
step 6: depositing an isolation medium layer on the front surface, and photoetching a contact hole area on the front surface, wherein the contact hole area is as follows: l1, L2, L3, L4, L5 positions, the corresponding contact hole spacing regions are: d1, D2, D3, D4, the regions being isolation dielectric layers;
step 7: the front side is sputtered or evaporated with metal, alloy.
2. The method for manufacturing the unidirectional ESD protection device capable of enhancing current capacity of claim 1, wherein: and (3) the isolation medium layer in the step (6) is tetraethoxysilane TEOS, the thickness is 5000-10000A, and a layer of TI/TIN is deposited after contact holes are photoetched.
3. The method for manufacturing the unidirectional ESD protection device capable of enhancing current capacity of claim 1, wherein: and (3) the isolation dielectric layer in the step (6) is tetraethoxysilane TEOS, the thickness is 7000A, and a layer of TI/TIN is deposited after contact holes are photoetched.
4. The method for manufacturing the unidirectional ESD protection device capable of enhancing current capacity of claim 1, wherein: the metal sputtered or evaporated on the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 2-4um, the temperature of the alloy is 360-430 ℃ and the time is 25-45min.
5. The method for manufacturing the unidirectional ESD protection device capable of enhancing current capacity of claim 1, wherein: the metal sputtered or evaporated on the front surface in the step 7 is aluminum or aluminum copper or aluminum silicon copper, the thickness is 3um, the temperature of the alloy is 400 ℃, and the time is 35min.
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