CN113688079B - Multi-level switching circuit for realizing communication flow control - Google Patents
Multi-level switching circuit for realizing communication flow control Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention provides a multi-level switching circuit for realizing communication flow control, which has the advantages of simple circuit, low cost and compatibility of TTL, 485 and 422 level conversion; the CPU is provided with a UART interface and is used for outputting TTL level; the switching module is connected with the CPU and used for controlling the level signal sent by the CPU to switch the level working state; the level conversion module is connected with the switching module and is used for converting the TTL level into an RS485 level or an RS422 level working mode according to the signal sent by the switching module; the output module is connected with the peripheral equipment and the level conversion module and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment; the level conversion module comprises an RS422 level conversion module for carrying out TTL and RS422 level mutual conversion, and the RS422 level conversion module is connected between the switching module and the output module; and the RS485 level conversion module is used for carrying out mutual conversion between TTL and RS485 levels, and the RS485 level conversion module is connected between the switching module and the output module.
Description
Technical Field
The invention relates to the technical field of level conversion, in particular to a multi-level switching circuit for realizing communication flow control.
Background
Along with the rapid development of digital signal processing technology, electronic products accelerate digitization, and when a digital circuit and an analog circuit are communicated, the conversion problem of different levels needs to be solved firstly, and the conversion is mainly realized by using a conversion chip and peripheral elements at present, but the conversion chip is complex in circuit and high in cost, cannot be compatible with TTL (transistor-transistor logic) levels, 485 levels and 422 levels which are widely adopted at present, and brings difficulty to practical application; and especially in domestic market, the current domestic chip can not realize that one chip can switch 485 and 422 levels by changing the configuration of peripheral elements, thereby causing a plurality of inconveniences.
Disclosure of Invention
Aiming at the problems, the invention provides a multi-level switching circuit for realizing communication flow control, which has simple circuit and low cost and can be compatible with TTL, 485 and 422 level conversion.
The technical scheme is as follows: a multi-level switching circuit for realizing communication flow control is characterized in that: comprising the following steps:
the CPU is provided with at least one UART interface and is used for outputting TTL level;
The switching module is connected with the UART interface on the CPU and used for controlling the level signal sent by the CPU to switch the level working state;
The level conversion module is connected with the switching module and is used for converting TTL level into an RS485 level or an RS422 level working mode according to signals sent by the switching module;
The output module is connected with the peripheral equipment and the level conversion module and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment;
the level shift module includes:
the RS422 level conversion module is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module is connected between the switching module and the output module;
and the RS485 level conversion module is used for carrying out mutual conversion between the TTL level and the RS485 level, and the RS485 level conversion module is connected between the switching module and the output module.
It is further characterized by:
The CPU is provided with two UART interfaces which are respectively marked as a first data transmitting end UART 0-TX 1, a second data transmitting end UART 0-TX 2, a first data receiving end UART 0-RX 1 and a second data receiving end URAT 0-RX 2;
The switching module comprises switches SW1 and SW2, wherein the switch SW1 adopts an 8-pin DIP dial switch, and the switch SW2 adopts a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are connected to the first data receiving terminal uart0_rx1, and pins 3 and 5 of the switch SW1 are connected to the second data receiving terminal urat0_rx2; the 4 pin of the switch SW2 is connected to the first data transmitting end uart0_tx1, and the 3 pin of the switch SW2 is connected to the second data transmitting end uart0_tx2;
The level conversion module is provided with two groups and is respectively and independently connected between the switching module and the output module;
The RS422 level conversion module comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a model CBM3485AS chip; one ends of the resistors R3, R4 and R6 are respectively correspondingly connected to the pins 2, 3 and 4 of the conversion chip U1, the other ends of the resistors R3, R4 and R6 are connected and then grounded, one end of the resistor R1 is connected to the pin 1 of the conversion chip U1, the other end of the resistor R1 is connected to the pin 2 of the switch SW1, the pin 5 of the conversion chip U1 is grounded, one end of the resistor R5 is connected with one end of the resistor R2 and the pin 7 of the conversion chip U1, the other end of the resistor R5 is connected with one end of the resistor R7 and the pin 6 of the conversion chip U1, the pin 8 of the conversion chip U1 is connected with one end of the capacitor C1 and then connected to the power supply end IO_P3V3, and the other end of the capacitor C1 is grounded;
The RS485 level conversion module comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and a MOS tube Q1, wherein the conversion chip U2 adopts a model CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pin of the switch SW 2; the other end of the resistor R15 is connected to the power supply end IO_P3V3, and the other end of the resistor R18 is grounded; the grid electrode of the MOS tube Q1 is connected with one ends of the resistors R16 and R19, and the connection point is connected with the 1 pin of the switch SW 2; the other end of the resistor R19 is grounded to the source electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected to the other end of the resistor R16, the 2,3 pins of the conversion chip U2 and one end of the resistor R8, the other end of the resistor R8 is connected to the power supply end IO_P3V3, the 1 pin of the conversion chip U2 is connected to the 8 pin of the switch SW1 after passing through the resistor R10, the 4 pin of the conversion chip U2 is connected to the 4 pin of the switch SW2 after passing through the resistor R13, the 5 pin of the conversion chip U2 is grounded, the 8 pin of the conversion chip U2 is connected to one end of the capacitor C2 and then connected to the power supply end IO_P3V3, the other end of the capacitor C2 is grounded, the 7 pin of the conversion chip U2 is connected to one end of the resistors R9 and R12, the 6 pin of the conversion chip U2 is connected to the other end of the resistor R12 and one end of the resistor R17 is connected to the other end of the resistor R17 and the other end of the resistor R3 is grounded to the power supply end IO_P3V 3;
The output module comprises capacitors C3-C6 and an interface CN1, wherein the interface CN1 is provided with 10 pin pins, pin pins 9 and 10 of the interface CN1 are grounded, one ends of the capacitors C3-C6 are connected and then grounded, the other end of the capacitor C3 is connected with the other end of the resistor R11, the other end of the capacitor C4 is connected with the other end of the resistor R14, the other end of the capacitor C5 is connected with the other end of the resistor R7, the other end of the capacitor C6 is connected with the other end of the resistor R2, and the other ends of the capacitors C3-C6 are respectively correspondingly connected with the pin pins 1, 3, 5 and 7 of the interface CN 1.
The invention has the advantages that the circuit is simple, the cost is low, the level signal sent by the CPU can be controlled by the switching module to switch the level working state, and then the TTL level is converted into the RS485 level or the RS422 level working mode by the level conversion module according to the output state of the switching module, namely the mutual conversion of the TTL level and the RS422 level and the mutual conversion of the TTL level and the RS485 level can be realized, thereby realizing the conversion of the compatible TTL level into 485 level and 422 level simultaneously, and having better economic use value.
Drawings
FIG. 1 is a block diagram of the structure of the present invention;
FIG. 2 is a schematic circuit diagram of a switching module connected to a CPU in an embodiment of the invention;
FIG. 3 is a schematic circuit diagram of a first level shifter module according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a second level shift module according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of an output module in an embodiment of the invention.
Detailed Description
As shown in fig. 1 to 5, a multi-level switching circuit for implementing communication flow control according to the present invention includes:
a CPU having at least one UART interface for outputting TTL level;
The switching module 1 is connected with the UART interface on the CPU and is used for controlling the level signal sent by the CPU to switch the level working state;
The level conversion module is connected with the switching module 1 and is used for converting TTL level into an RS485 level or an RS422 level working mode according to signals sent by the switching module 1;
the output module 2 is connected with the peripheral equipment 3 and the level conversion module, and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment 3;
The level conversion module includes:
The RS422 level conversion module 6 is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module 6 is connected between the switching module 1 and the output module 2;
and the RS485 level conversion module 7 is used for carrying out mutual conversion between the TTL level and the RS485 level, and the RS485 level conversion module 7 is connected between the switching module 1 and the output module 2.
The CPU is provided with two UART interfaces which are respectively marked as a first data transmitting end UART0_TX1, a second data transmitting end UART0_TX2, a first data receiving end UART0_RX1 and a second data receiving end URAT0_RX2; the first data transmitting end uart0_tx1 and the second data transmitting end uart0_tx2 can be understood as data transmitting signals (TX) on the CPU, and the first data receiving end uart0_rx1 and the second data receiving end urat0_rx2 are data receiving signals (RX) on the CPU.
The switching module 1 comprises switches SW1 and SW2, wherein the switch SW1 adopts an 8-pin DIP dial switch, and the switch SW2 adopts a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are connected with a first data receiving end UART0_RX1, and pins 3 and 5 of the switch SW1 are connected with a second data receiving end URAT0_RX2; the 4 pin of the switch SW2 is connected to the first data transmitting terminal uart0_tx1, and the 3 pin of the switch SW2 is connected to the second data transmitting terminal uart0_tx2.
In this embodiment, two groups of level conversion modules are provided, which are denoted as a first level conversion module 4 and a second level conversion module 5, and the first level conversion module 4 and the second level conversion module 5 are respectively and independently connected between the switching module 1 and the output module 2; the number of the level conversion modules can be set according to actual needs.
The RS422 level conversion module 6 in the first level conversion module 4 comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a model CBM3485AS chip; one end of each resistor R3, R4 and R6 is correspondingly connected to the pins 2,3 and 4 of the conversion chip U1 respectively, the other ends of the resistors R3, R4 and R6 are connected and then grounded, one end of each resistor R1 is connected to the pin 1 of the conversion chip U1, the other end of each resistor R1 is connected to the pin 2 of the switch SW1, the pin 5 of the conversion chip U1 is grounded, one end of each resistor R5 is connected with one end of each resistor R2 and the pin 7 of the conversion chip U1, the other end of each resistor R5 is connected with one end of each resistor R7 and the pin 6 of the conversion chip U1, the pin 8 of the conversion chip U1 is connected with one end of the capacitor C1 and then connected to the power supply end IO_P3V3, and the other end of the capacitor C1 is grounded, wherein the power supply end IO_P3V3 is the power supply source 3.3V.
The RS485 level conversion module 7 in the first level conversion module 4 comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and a MOS tube Q1, wherein the conversion chip U2 adopts a model CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pin of the switch SW 2; the other end of the resistor R15 is connected with the power supply end IO_P3V3, and the other end of the resistor R18 is grounded; the grid electrode of the MOS tube Q1 is connected with one ends of the resistors R16 and R19, and the connection point is connected with the 1 pin of the switch SW 2; the other end of the resistor R19 is grounded with the source electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected with the other end of the resistor R16, the 2 pins and 3 pins of the conversion chip U2 and one end of the resistor R8, the other end of the resistor R8 is connected with the power supply end IO_P3V3, the 1 pin of the conversion chip U2 is connected with the 8 pin of the switch SW1 after passing through the resistor R10, the 4 pin of the conversion chip U2 is connected with the 4 pin of the switch SW2 after passing through the resistor R13, the 5 pin of the conversion chip U2 is grounded, the 8 pin of the conversion chip U2 is connected with one end of the capacitor C2 and then connected with the power supply end IO_P3V3, the other end of the capacitor C2 is grounded, the 7 pin of the conversion chip U2 is connected with one ends of the resistors R9 and R12, the 6 pin of the conversion chip U2 is connected with the other end of the resistor R12 and one end of the resistor R17, the other end of the resistor R17 is connected with the power supply end IO_P3V3, and the other end of the resistor R9 is grounded.
The RS422 level conversion module 6 in the second level conversion module 5 comprises a capacitor C12, resistors R32-R38 and a conversion chip U4, wherein the conversion chip U4 adopts a model CBM3485AS chip; the RS485 level conversion module 7 in the second level conversion module 5 comprises a capacitor C11, resistors R20-R31, a conversion chip U3 and a MOS tube Q2, wherein the conversion chip U3 adopts a model CBM3485AS chip; the circuit connection of the second level shift module 5 is the same as the circuit connection in the first level shift module 4, and the principle is the same, and details are not repeated here.
The output module 2 comprises capacitors C3-C10 and an interface CN1, the interface CN1 is provided with 10 pin pins, pin 9 and pin 10 of the interface CN1 are grounded, one ends of the capacitors C3-C10 are connected and then grounded, the other end of the capacitor C3 is connected with the other end of a resistor R11, the other end of the capacitor C4 is connected with the other end of a resistor R14, the other end of the capacitor C5 is connected with the other end of a resistor R7, the other end of the capacitor C6 is connected with the other end of a resistor R2, the other end of the capacitor C7 is connected with the other end of a resistor R23, the other end of the capacitor C8 is connected with the other end of a resistor R26, the other end of the capacitor C9 is connected with the other end of a resistor R38, and the other ends of the capacitors C3-C10 are respectively correspondingly connected with pin 1, pin 3, pin 5, pin 7, pin 2, pin 3, pin 6 and pin 8 of the interface CN 1.
The specific working principle is described by the first level conversion module 4 in this embodiment:
Whether the uart0_rx1 signal sent by the CPU is connected to the conversion chip U1 or the conversion chip U2 is controlled by the switches SW1, SW 2;
The conversion chips U1 and U2 in the first level conversion module 4 are all model CBM3485AS chips, the 2 pins and the 3 pins of the CBM3485AS chips are respectively RE (receiver) and DE (driver) output enable, when RE is in a low level, the 1 pin output of the CBM3485AS chip is released, when RE is in a high level, the 1 pin of the CBM3485AS chip is in a high impedance, when DE is in a high level, the 6 pin and the 7 pin output of the CBM3485AS chip are released, and when DE is in a low level, the 6 pin and the 7 pin of the CBM3485AS chip are in a high impedance. It should be noted that the situation that RE is high and DE is low is avoided, so that the CBM3485AS chip can enter a shutdown mode; RS485 is half duplex communication, that is, the transmission and the reception cannot be performed simultaneously, and only a single state of receiving or transmitting can exist, so that the configuration needs to be performed on the 2 pins and the 3 pins of the CBM3485AS chip, and the state of one on and one off is kept. In fig. 3, the conversion chip U2 performs initial pull-up configuration on both pins 2 and 3, ensuring an initial state.
Generally, when the 3485 conversion chip is used, a GPIO signal is required to be led out from the CPU end, a pull-up is performed on pins 2 and 3 of the 3485 conversion chip to ensure a high-level initial state, then a pull-up resistor is connected with a signal wire connected with pins 2 and 3 and then connected with a GPIO of the CPU, and then when information is required to be transmitted outwards, the CPU is required to detect whether a TX signal is in action, if TX is in action, the GPIO is required to be internally configured to be high level to ensure that pins 2 and 3 of the 3485 conversion chip are both high level and are changed into a transmission information mode; when external information needs to be received, the CPU needs to detect whether the TX signal is not in action, if the TX signal is not in action, the CPU internally configures GPIO to be in low level, so that the 2 pin and the 3 pin of the 3485 conversion chip are in low level and become in an information receiving mode, but the use has the defects that the detection of the GPIO is carried out again, delay exists, the configuration of software is very complicated, the workload is increased, and if the detection is not in action, the information transmission is easy to make mistakes, and the phenomenon of unstable transmission can occur; in contrast, in the present invention, taking 485 function as an example, the switch SW2 is turned on, the data transmission signal (TX) will be connected to the gate of the MOS transistor Q1, in the initial state, the 2 and 3 pins of the 3485 conversion chip U2 are pulled up with the power supply 3.3V and are in the transmission mode, while the level of the data transmission signal (TX) is actually changed from high to low when the data transmission signal (TX) is transmitted, the data transmission signal (TX) is changed to low, the MOS transistor Q1 is turned off, the 2 and 3 pins of the 3485 conversion chip U2 are in the high level and are in the transmission mode, and when the data transmission signal (TX) is not transmitted, the 2 and 3 pins of the MOS transistor Q1 is turned on, the 3485 conversion chip U2 are in the low level and are in the receiving mode, the design can control the working state of the 3485 conversion chip by the state of the data transmission signal (TX), and the GPIO is not required to be additionally controlled, and software configuration is not required to be additionally used to detect to control the GPIO state, thus reducing unnecessary efficiency and accuracy;
That is, when the data transmission signal (TX) is at a low level, the MOS transistor Q1 is turned off, pins 2 and 3 of the 3485 conversion chip U2 are both at a high level, at this time, the driver output of the 3485 conversion chip U2 is released, the receiver output is turned off, and the uart0_tx1 of the CPU is converted into a 485 level output;
When a data transmission signal (TX) is at a high level, the MOS tube Q1 is opened, pins 2 and 3 of the 3485 conversion chip U2 are both at a low level, the driver output is turned off, the output of the receiver is released, the 485 level is converted into a TLL level through the 3485 conversion chip U2 and is transmitted to the CPU through the UART0_RX1, so that an RE DE state is controlled without using an additional GPIO pin, the control can be controlled by the state of the TTL, and great convenience is brought to a designer.
In particular, the method comprises the steps of,
When the RS485 level is needed to be used, the pins 1 and 8 of the switch SW1 are turned on, the pins 2 and 7 are disconnected, the UART0_RX1 signal sent by the CPU is connected to the pin 1 of the conversion chip U2, meanwhile, the pins 1 and 4 of the switch SW2 are turned on, the UART0_TX1 signal is connected to the grid electrode of the MOS tube Q1, the grid electrode of the MOS tube Q1 is grounded through the resistor R19, an initial low level is given to the source electrode of the MOS tube Q1, the DE output of the conversion chip U2 is released, the RE output is turned off, and the UART0_TX1 of the CPU is converted into 485 level output, so that 485 communication can be realized;
When the RS422 level is to be used, the pins 1 and 8 of the switch SW1 are disconnected, the pins 2 and 7 are connected, the UART0_RX1 signal sent by the CPU is received to the pin 1 of the conversion chip U1, meanwhile, the pins 1 and 4 of the switch SW2 are disconnected, the state of the conversion chip U2 is controlled without sending a data sending signal through the CPU, the conversion chip U2 is always in the DE output release state, the pins 2, 3 and 4 of the conversion chip U1 are grounded through resistors, and the conversion chip U1 is always in the RE output release state, so 422 communication can be realized.
Therefore, the invention realizes the purpose of automatically controlling the communication state in the transmission process through multi-level conversion.
The conversion chips U3 and U4 in fig. 4 and their corresponding components form a second level conversion module 5, so as to implement level switching of the second group 485 422, and the circuit implementation principle is the same as that of the first level conversion module 4; in addition, if multiple groups 485 422 of level switching is needed, only a level conversion module is needed to be additionally arranged, and an output interface is expanded.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (1)
1. A multi-level switching circuit for realizing communication flow control is characterized in that: comprising the following steps:
The CPU is provided with at least one UART interface and is used for outputting TTL level; the CPU is provided with two UART interfaces which are respectively marked as a first data transmitting end UART 0-TX 1, a second data transmitting end UART 0-TX 2, a first data receiving end UART 0-RX 1 and a second data receiving end URAT 0-RX 2;
The switching module is connected with the UART interface on the CPU and used for controlling the level signal sent by the CPU to switch the level working state;
The level conversion module is connected with the switching module and is used for converting TTL level into an RS485 level or an RS422 level working mode according to signals sent by the switching module;
The output module is connected with the peripheral equipment and the level conversion module and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment;
the level shift module includes:
the RS422 level conversion module is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module is connected between the switching module and the output module;
The RS485 level conversion module is used for carrying out mutual conversion between TTL level and RS485 level, and the RS485 level conversion module is connected between the switching module and the output module;
The switching module comprises switches SW1 and SW2, wherein the switch SW1 adopts an 8-pin DIP dial switch, and the switch SW2 adopts a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are connected to the first data receiving terminal uart0_rx1, and pins 3 and 5 of the switch SW1 are connected to the second data receiving terminal urat0_rx2; the 4 pin of the switch SW2 is connected to the first data transmitting end uart0_tx1, and the 3 pin of the switch SW2 is connected to the second data transmitting end uart0_tx2; the level conversion module is provided with two groups and is respectively and independently connected between the switching module and the output module; the RS422 level conversion module comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a model CBM3485AS chip; one ends of the resistors R3, R4 and R6 are respectively correspondingly connected to the pins 2, 3 and 4 of the conversion chip U1, the other ends of the resistors R3, R4 and R6 are connected and then grounded, one end of the resistor R1 is connected to the pin 1 of the conversion chip U1, the other end of the resistor R1 is connected to the pin 2 of the switch SW1, the pin 5 of the conversion chip U1 is grounded, one end of the resistor R5 is connected with one end of the resistor R2 and the pin 7 of the conversion chip U1, the other end of the resistor R5 is connected with one end of the resistor R7 and the pin 6 of the conversion chip U1, the pin 8 of the conversion chip U1 is connected with one end of the capacitor C1 and then connected to the power supply end IO_P3V3, and the other end of the capacitor C1 is grounded; the RS485 level conversion module comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and a MOS tube Q1, wherein the conversion chip U2 adopts a model CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pin of the switch SW 2; the other end of the resistor R15 is connected to the power supply end IO_P3V3, and the other end of the resistor R18 is grounded; the grid electrode of the MOS tube Q1 is connected with one ends of the resistors R16 and R19, and the connection point is connected with the 1 pin of the switch SW 2; the other end of the resistor R19 is grounded to the source electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected to the other end of the resistor R16, the 2, 3 pins of the conversion chip U2 and one end of the resistor R8, the other end of the resistor R8 is connected to the power supply end IO_P3V3, the 1 pin of the conversion chip U2 is connected to the 8 pin of the switch SW1 after passing through the resistor R10, the 4 pin of the conversion chip U2 is connected to the 4 pin of the switch SW2 after passing through the resistor R13, the 5 pin of the conversion chip U2 is grounded, the 8 pin of the conversion chip U2 is connected to one end of the capacitor C2 and then connected to the power supply end IO_P3V3, the other end of the capacitor C2 is grounded, the 7 pin of the conversion chip U2 is connected to one end of the resistors R9 and R12, the 6 pin of the conversion chip U2 is connected to the other end of the resistor R12 and one end of the resistor R17 is connected to the other end of the resistor R17 and the other end of the resistor R3 is grounded to the power supply end IO_P3V 3; the output module comprises capacitors C3-C6 and an interface CN1, the interface CN1 is provided with 10 pin pins, pin pins 9 and 10 of the interface CN1 are grounded, one ends of the capacitors C3-C6 are connected and then grounded, the other end of the capacitor C3 is connected with the other end of the resistor R11, the other end of the capacitor C4 is connected with the other end of the resistor R14, the other end of the capacitor C5 is connected with the other end of the resistor R7, the other end of the capacitor C6 is connected with the other end of the resistor R2, and the other ends of the capacitors C3-C6 are respectively correspondingly connected with the pin pins 1,3, 5 and 7 of the interface CN 1.
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| CN202110924464.1A CN113688079B (en) | 2021-08-12 | 2021-08-12 | Multi-level switching circuit for realizing communication flow control |
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| CN202110924464.1A CN113688079B (en) | 2021-08-12 | 2021-08-12 | Multi-level switching circuit for realizing communication flow control |
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| JPS62211764A (en) * | 1986-03-12 | 1987-09-17 | Oki Electric Ind Co Ltd | Inter-circuit connection structure |
| CN101140557A (en) * | 2007-10-23 | 2008-03-12 | 中兴通讯股份有限公司 | System and method of RS232/RS48 compatibility interface |
| CN106571990A (en) * | 2016-10-31 | 2017-04-19 | 青岛海信电器股份有限公司 | Automatic communication mode switching circuit, display and display system |
| CN209708119U (en) * | 2019-06-14 | 2019-11-29 | 山东山大华天科技集团股份有限公司 | A kind of half-duplex RS 232-RS485 automatic switching circuit and communication equipment |
| CN210297899U (en) * | 2019-07-18 | 2020-04-10 | 江苏嘉擎信息技术有限公司 | Dual-mode DP switching circuit |
| CN212009333U (en) * | 2020-05-07 | 2020-11-24 | 山东超越数控电子股份有限公司 | Interface board compatible with multiple interface signals |
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2021
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62211764A (en) * | 1986-03-12 | 1987-09-17 | Oki Electric Ind Co Ltd | Inter-circuit connection structure |
| CN101140557A (en) * | 2007-10-23 | 2008-03-12 | 中兴通讯股份有限公司 | System and method of RS232/RS48 compatibility interface |
| CN106571990A (en) * | 2016-10-31 | 2017-04-19 | 青岛海信电器股份有限公司 | Automatic communication mode switching circuit, display and display system |
| CN209708119U (en) * | 2019-06-14 | 2019-11-29 | 山东山大华天科技集团股份有限公司 | A kind of half-duplex RS 232-RS485 automatic switching circuit and communication equipment |
| CN210297899U (en) * | 2019-07-18 | 2020-04-10 | 江苏嘉擎信息技术有限公司 | Dual-mode DP switching circuit |
| CN212009333U (en) * | 2020-05-07 | 2020-11-24 | 山东超越数控电子股份有限公司 | Interface board compatible with multiple interface signals |
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| CN113688079A (en) | 2021-11-23 |
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