CN113688079A - Multi-level switching circuit for realizing communication current control - Google Patents
Multi-level switching circuit for realizing communication current control Download PDFInfo
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Abstract
The invention provides a multi-level switching circuit for realizing communication flow control, which has the advantages of simple circuit, low cost and compatibility with TTL, 485 and 422 level conversion; the method comprises the following steps: CPU with UART interface to output TTL level; the switching module is connected with the CPU and used for controlling a level signal sent by the CPU to switch a level working state; the level conversion module is connected with the switching module and used for converting the TTL level into an RS485 level or an RS422 level according to a signal sent by the switching module; the output module is connected with the peripheral equipment and the level conversion module and used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment; the level conversion module includes: the RS422 level conversion module is used for carrying out mutual conversion between TTL level and RS422 level and is connected between the switching module and the output module; and the RS485 level conversion module is used for performing mutual conversion between the TTL level and the RS485 level, and the RS485 level conversion module is connected between the switching module and the output module.
Description
Technical Field
The invention relates to the technical field of level conversion, in particular to a multi-level switching circuit for realizing communication flow control.
Background
With the rapid development of digital signal processing technology, electronic products are also digitized rapidly, and when a digital circuit is communicated with an analog circuit, the problem of conversion of different levels needs to be solved at first, which is mainly realized by using a conversion chip and peripheral elements at present, but the circuit is complex and high in cost, and cannot be compatible with TTL, 485 and 422 levels which are widely adopted at present, so that difficulty is brought to practical application; in particular, in the domestic market, the 485 and 422 levels of a chip cannot be switched by changing the configuration of peripheral elements in the current domestic chip, which causes inconvenience.
Disclosure of Invention
In view of the above problems, the present invention provides a multilevel switching circuit for implementing communication flow control, which has simple circuit and low cost, and is compatible with TTL, 485 and 422 level conversion.
The technical scheme is as follows: a multi-level switching circuit for realizing communication flow control is characterized in that: the method comprises the following steps:
the CPU is provided with at least one UART interface and is used for outputting TTL level;
the switching module is connected with the UART interface on the CPU and used for controlling a level signal sent by the CPU to switch a level working state;
the level conversion module is connected with the switching module and used for converting the TTL level into an RS485 level or an RS422 level according to a signal sent by the switching module;
the output module is connected with peripheral equipment and the level conversion module, and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment;
the level conversion module includes:
the RS422 level conversion module is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module is connected between the switching module and the output module;
and the RS485 level conversion module is used for performing mutual conversion between a TTL level and an RS485 level, and the RS485 level conversion module is connected between the switching module and the output module.
It is further characterized in that:
the CPU is provided with two UART interfaces which are respectively marked as a first data transmitting terminal UART0_ TX1, a second data transmitting terminal UART0_ TX2, a first data receiving terminal UART0_ RX1 and a second data receiving terminal URAT0_ RX 2;
the switching module comprises switches SW1 and SW2, the switch SW1 is an 8-pin DIP dial switch, and the switch SW2 is a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are both connected to the first data receiving terminal UART0_ RX1, pins 3 and 5 of the switch SW1 are both connected to the second data receiving terminal URAT0_ RX 2; the 4 pin of the switch SW2 is connected to the first data transmitting terminal UART0_ TX1, and the 3 pin of the switch SW2 is connected to the second data transmitting terminal UART0_ TX 2;
the two groups of level conversion modules are respectively and independently connected between the switching module and the output module;
the RS422 level conversion module comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a CBM3485AS chip; one end of each of the resistors R3, R4 and R6 is correspondingly connected to pins 2, 3 and 4 of the conversion chip U1, the other ends of the resistors R3, R4 and R6 are connected and then grounded, one end of the resistor R1 is connected to pin 1 of the conversion chip U1, the other end of the resistor R1 is connected to pin 2 of the switch SW1, pin 5 of the conversion chip U1 is grounded, one end of the resistor R5 is connected to one end of the resistor R2 and pin 7 of the conversion chip U1, the other end of the resistor R5 is connected to one end of the resistor R7 and pin 6 of the conversion chip U1, pin 8 of the conversion chip U1 is connected to one end of the capacitor C1 and then connected to the power supply terminal IO _ P3V3, and the other end of the capacitor C1 is grounded;
the RS485 level conversion module comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and an MOS transistor Q1, wherein the conversion chip U2 adopts a CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pins of the switch SW 2; the other end of the resistor R15 is connected to the power supply terminal IO _ P3V3, and the other end of the resistor R18 is grounded; the gate of the MOS transistor Q1 is connected with one end of each of the resistors R16 and R19, and the connection point is connected with pin 1 of the switch SW 2; the other end of the resistor R19 and the source of the MOS transistor Q1 are all grounded, the drain of the MOS transistor Q1 and the other end of the resistor R16, the pins 2 and 3 of the conversion chip U2 and one end of the resistor R8 are all connected, the other end of the resistor R8 is connected to the power supply terminal IO _ P3V3, the pin 1 of the conversion chip U2 is connected to the pin 8 of the switch SW1 through the resistor R10, the pin 4 of the conversion chip U2 is connected to the pin 4 of the switch SW2 through the resistor R13, the pin 5 of the conversion chip U2 is grounded, the pin 8 of the conversion chip U2 is connected to one end of the capacitor C2 and then connected to the power supply terminal IO _ P3V3, the other end of the capacitor C2 is grounded, the pin 7 of the conversion chip U2 is connected to one ends of the resistors R2 and the resistor R2, the pin 6 of the other end of the conversion chip U2 is connected to the power supply terminal IO _ P2 and the resistor R2 and the pin 3V 2, the other end of the resistor R9 is grounded;
the output module comprises capacitors C3-C6 and an interface CN1, the interface CN1 is provided with 10 pin pins, the pin 9 and the pin 10 of the interface CN1 are both grounded, one ends of the capacitors C3-C6 are grounded after being connected, the other end of the capacitor C3 is connected with the other end of the resistor R11, the other end of the capacitor C4 is connected with the other end of the resistor R14, the other end of the capacitor C5 is connected with the other end of the resistor R7, the other end of the capacitor C6 is connected with the other end of the resistor R2, and the other ends of the capacitors C3-C6 are correspondingly connected with the pin 1, the pin 3, the pin 5 and the pin 7 of the interface CN1 respectively.
The invention has the advantages that the circuit is simple, the cost is low, the level signal sent by the CPU can be controlled by the switching module to switch the level working state, then the TTL level is converted into the RS485 level or the RS422 level working mode by the level conversion module according to the output state of the switching module, namely, the mutual conversion of the TTL level and the RS422 level and the mutual conversion of the TTL level and the RS485 level can be realized, thereby realizing the simultaneous compatibility of the TTL level conversion into the 485 level and the RS422 level, and having better economic use value.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a schematic diagram of a circuit in which a switching module is connected to a CPU according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a first level shifting module according to an embodiment of the present invention;
FIG. 4 is a circuit schematic of a second level shifting module in an embodiment of the invention;
fig. 5 is a circuit schematic of an output module in an embodiment of the invention.
Detailed Description
As shown in fig. 1 to 5, a multi-level switching circuit for implementing communication current control according to the present invention includes:
the CPU is provided with at least one UART interface and is used for outputting TTL level;
the switching module 1 is connected with a UART interface on the CPU and used for controlling a level signal sent by the CPU to switch a level working state;
the level conversion module is connected with the switching module 1 and used for converting the TTL level into an RS485 level or an RS422 level according to a signal sent by the switching module 1;
the output module 2 is connected with the peripheral equipment 3 and the level conversion module, and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment 3;
the level conversion module includes:
the RS422 level conversion module 6 is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module 6 is connected between the switching module 1 and the output module 2;
and the RS485 level conversion module 7 is used for performing mutual conversion between the TTL level and the RS485 level, and the RS485 level conversion module 7 is connected between the switching module 1 and the output module 2.
The CPU is provided with two UART interfaces which are respectively marked as a first data transmitting terminal UART0_ TX1, a second data transmitting terminal UART0_ TX2, a first data receiving terminal UART0_ RX1 and a second data receiving terminal URAT0_ RX 2; the first and second data transmitters UART0_ TX1, UART0_ TX2 may be understood as data transmission signals (TX) on the CPU, and the first and second data receivers UART0_ RX1, URAT0_ RX2 may be understood as data reception signals (RX) on the CPU.
The switching module 1 comprises switches SW1 and SW2, wherein the switch SW1 is an 8-pin DIP dial switch, and the switch SW2 is a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are both connected with the first data receiving terminal UART0_ RX1, and pins 3 and 5 of the switch SW1 are both connected with the second data receiving terminal URAT0_ RX 2; the 4 pin of the switch SW2 is connected to the first data transmitting terminal UART0_ TX1, and the 3 pin of the switch SW2 is connected to the second data transmitting terminal UART0_ TX 2.
In this embodiment, there are two sets of level conversion modules, which are denoted as a first level conversion module 4 and a second level conversion module 5, where the first level conversion module 4 and the second level conversion module 5 are respectively and independently connected between the switching module 1 and the output module 2; the number of the level conversion modules can be set according to actual needs.
The RS422 level conversion module 6 in the first level conversion module 4 comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a CBM3485AS chip; one end of each of the resistors R3, R4, and R6 is respectively and correspondingly connected to pins 2, 3, and 4 of the conversion chip U1, the other ends of the resistors R3, R4, and R6 are connected and then grounded, one end of the resistor R1 is connected to pin 1 of the conversion chip U1, the other end of the resistor R1 is connected to pin 2 of the switch SW1, pin 5 of the conversion chip U1 is grounded, one end of the resistor R5 is connected to one end of the resistor R2 and pin 7 of the conversion chip U1, the other end of the resistor R5 is connected to one end of the resistor R7 and pin 6 of the conversion chip U1, pin 8 of the conversion chip U1 is connected to one end of the capacitor C1 and then connected to the power supply terminal IO _ P3V3, and the other end of the capacitor C1 is grounded, where the power supply terminal _ P3V3 is power supply 3.3V.
The RS485 level conversion module 7 in the first level conversion module 4 comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and an MOS transistor Q1, wherein the conversion chip U2 adopts a CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pins of the switch SW 2; the other end of the resistor R15 is connected with a power supply end IO _ P3V3, and the other end of the resistor R18 is grounded; the grid of the MOS transistor Q1 is connected with one ends of the resistors R16 and R19, and the connection point is connected with pin 1 of the switch SW 2; the other end of the resistor R19 is grounded with the source of the MOS transistor Q1, the drain of the MOS transistor Q1 is grounded with the other end of the resistor R16, the pins 2 and 3 of the conversion chip U2 and one end of the resistor R8, the other end of the resistor R8 is grounded with the power supply terminal IO _ P3V3, the pin 1 of the conversion chip U2 is connected with the pin 8 of the switch SW1 through the resistor R10, the pin 4 of the conversion chip U2 is connected with the pin 4 of the switch SW2 through the resistor R13, the pin 5 of the conversion chip U2 is grounded, the pin 8 of the conversion chip U2 is connected with one end of the capacitor C2 and then connected with the power supply terminal IO _ P3V 2, the other end of the capacitor C2 is grounded, the pin 7 of the conversion chip U2 is connected with one ends of the resistors R2 and R2, the pin 6 of the conversion chip U2 is connected with the other end of the resistor R2 and one end of the power supply terminal IO _ P3V 2, and the other end of the resistor R2 are grounded.
The RS422 level conversion module 6 in the second level conversion module 5 includes a capacitor C12, resistors R32-R38, and a conversion chip U4, and the conversion chip U4 is a CBM3485AS chip; the RS485 level conversion module 7 in the second level conversion module 5 includes a capacitor C11, resistors R20-R31, a conversion chip U3, and a MOS transistor Q2, and the conversion chip U3 adopts a model CBM3485AS chip; the circuit connections of the second level shifting module 5 are identical to the circuit connections in the first level shifting module 4, the principle is the same, and are not detailed here.
The output module 2 comprises capacitors C3-C10 and an interface CN1, the interface CN1 is provided with 10 pin pins, the pin pins 9 and 10 of the interface CN1 are both grounded, one ends of the capacitors C3-C10 are grounded after being connected, the other end of the capacitor C3 is connected with the other end of a resistor R11, the other end of the capacitor C4 is connected with the other end of the resistor R14, the other end of the capacitor C5 is connected with the other end of the resistor R7, the other end of the capacitor C6 is connected with the other end of the resistor R2, the other end of the capacitor C7 is connected with the other end of a resistor R23, the other end of the capacitor C8 is connected with the other end of the resistor R26, the other end of the capacitor C9 is connected with the other end of the resistor R38, the other end of the capacitor C10 is connected with the other end of the resistor R33, and the other ends of the capacitors C3-C10 are respectively and correspondingly connected with pin 1, pin 3, pin 5, pin 7, pin 2, pin 3, pin 6 and pin 8 of the interface CN 1.
In this embodiment, the first level shift module 4 is used to explain the specific working principle:
whether the UART0_ RX1 signal sent by the CPU is connected to the conversion chip U1 or the conversion chip U2 is controlled by the switches SW1 and SW 2;
the conversion chips U1 and U2 in the first level conversion module 4 are all of CBM3485AS chips, the pins 2 and 3 of the CBM3485AS chip are respectively the output enable of RE (receiver) and DE (driver), when RE is low level, the pin 1 output of the CBM3485AS chip is released, when RE is high level, the pin 1 of the CBM3485AS chip is high impedance, when DE is high level, the pin 6 and pin 7 outputs of the CBM34 3485AS chip are released, when DE is low level, the pin 6 and pin 7 of the CBM34 3485AS chip are high impedance. It should be noted that the condition of RE being high and DE being low is avoided, which would cause the CBM3485AS chip to enter the power-off mode; RS485 is half-duplex communication, that is, transceiving cannot be performed simultaneously, and only a single state of receiving or transmitting exists, so that pins 2 and 3 of the CBM3485AS chip need to be configured to maintain a state of one switch. In fig. 3, the switch chip U2 has an initial pull-up configuration for both its 2-pin and 3-pin, ensuring an initial state.
Generally, when a 3485 conversion chip is used, a GPIO signal needs to be led out from a CPU terminal, and a pull-up is performed on pins 2 and 3 of the 3485 conversion chip to ensure a high level initial state, then a pull-up resistor is connected to a signal line connected to the pins 2 and 3 and a GPIO of the CPU, then when information needs to be transmitted to the outside, the CPU needs to detect whether a TX signal is in action, if the TX signal is in action, the GPIO needs to be internally configured to be at a high level to ensure that the pins 2 and 3 of the 3485 conversion chip are both at a high level, and the mode is changed into an information transmission mode; when external information needs to be received, the CPU needs to detect whether a TX signal does not act, if the TX signal does not act, GPIO is configured in the CPU to be low level, and therefore pins 2 and 3 of a 3485 conversion chip are both low level and are changed into a message receiving mode, but the use has the defects that the GPIO detects the action again, time delay exists, the configuration of software is complicated, the workload is increased, and if no action is generated during detection, the information transmission easily makes mistakes, and the phenomenon of unstable transmission can also occur; in contrast, in the present invention, taking the 485 function as an example, the switch SW2 is turned on, the data transmission signal (TX) is connected to the gate of the MOS transistor Q1, and initially, pin 2 and pin 3 of the chip U2 are pulled up by the power supply 3.3V, and is in the transmission mode, and when the data transmission signal (TX) transmits data, its own level is changed from high to low, when the data transmission signal (TX) is transmitted, the data transmission signal (TX) is changed to low, the MOS transistor Q1 is turned off, pin 2 and pin 3 of the chip U2 is changed to high level and is changed to the transmission mode, when the data transmission signal (TX) is not transmitted, the data transmission signal (TX) is changed to high, the MOS transistor Q1 is turned on, pin 2 and pin 3 of the chip U2 are changed to low level and are changed to the reception mode, and this design can control the operating state of the chip 3485 by the state of the data transmission signal (TX), the GPIO is not required to be additionally added for control, and the GPIO state is not required to be controlled by additionally configuring and detecting software, so that unnecessary no action is reduced, and the transmission efficiency and accuracy are ensured;
that is, when the data transmission signal (TX) is at a low level, the MOS transistor Q1 is turned off, the pins 2 and 3 of the 3485 conversion chip U2 are both at a high level, at this time, the driver output of the 3485 conversion chip U2 is released, the output of the receiver is turned off, and the UART0_ TX1 of the CPU is converted into a 485 level output;
when a data transmission signal (TX) is at a high level, the MOS tube Q1 is turned on, the 2 and 3 pins of the 3485 conversion chip U2 are both at a low level, the driver output is turned off at the moment, the output of the receiver is released, the 485 level is converted into the TLL level through the 3485 conversion chip U2 and is transmitted to the CPU through the UART0_ RX1, so that an additional GPIO pin is not needed to control the RE DE state, the RE DE state can be controlled by the TTL state, and great convenience is brought to a designer.
In particular, the amount of the solvent to be used,
when the RS485 level is used, the pin 1 and the pin 8 of the switch SW1 are switched on, the pin 2 and the pin 7 are switched off, the UART0_ RX1 signal sent by the CPU is connected to the pin 1 of the conversion chip U2, meanwhile, the pin 1 and the pin 4 of the switch SW2 are switched on, the UART0_ TX1 signal is connected to the grid electrode of the MOS tube Q1, the grid electrode of the MOS tube Q1 is grounded through the resistor R19, an initial low level is provided for the source electrode of the MOS tube Q1, the DE output of the conversion chip U2 is released, the RE output is switched off, and the UART0_ TX1 of the CPU is converted into a 485 level output, so that 485 communication can be realized;
when the RS422 level is used, the pin 1 and the pin 8 of the switch SW1 are disconnected, the pin 2 and the pin 7 are switched on, the UART0_ RX1 signal sent by the CPU is connected to the pin 1 of the conversion chip U1, meanwhile, the pin 1 and the pin 4 of the switch SW2 are disconnected, the state of the conversion chip U2 is not required to be controlled by sending a data sending signal by the CPU, the conversion chip U2 is always in a DE output release state, the pins 2, 3 and 4 of the conversion chip U1 are grounded through resistors, and the conversion chip U1 is always in a RE output release state, so that 422 communication can be realized.
Therefore, the invention realizes the purpose of automatically controlling the communication state in the transmission process through multi-level conversion.
The conversion chips U3 and U4 in fig. 4 and their corresponding components form a second level conversion module 5, which implements level switching of the second group 485422, and the circuit implementation principle is the same as that of the first level conversion module 4; in addition, if multiple groups of 485422 level switching are required, only a level conversion module needs to be added, and an output interface is expanded.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A multi-level switching circuit for realizing communication flow control is characterized in that: the method comprises the following steps:
the CPU is provided with at least one UART interface and is used for outputting TTL level;
the switching module is connected with the UART interface on the CPU and used for controlling a level signal sent by the CPU to switch a level working state;
the level conversion module is connected with the switching module and used for converting the TTL level into an RS485 level or an RS422 level according to a signal sent by the switching module;
the output module is connected with peripheral equipment and the level conversion module, and is used for receiving the converted level signal output by the level conversion module and transmitting the level signal to the peripheral equipment;
the level conversion module includes:
the RS422 level conversion module is used for carrying out mutual conversion between TTL level and RS422 level, and the RS422 level conversion module is connected between the switching module and the output module;
and the RS485 level conversion module is used for performing mutual conversion between a TTL level and an RS485 level, and the RS485 level conversion module is connected between the switching module and the output module.
2. The multi-level switching circuit for realizing communication flow control according to claim 1, wherein: the CPU has two UART interfaces, which are respectively denoted as a first data transmitting terminal UART0_ TX1, a second data transmitting terminal UART0_ TX2, a first data receiving terminal UART0_ RX1, and a second data receiving terminal URAT0_ RX 2.
3. The multi-level switching circuit for realizing communication flow control according to claim 2, wherein: the switching module comprises switches SW1 and SW2, the switch SW1 is an 8-pin DIP dial switch, and the switch SW2 is a 4-pin DIP dial switch; pins 1 and 7 of the switch SW1 are both connected to the first data receiving terminal UART0_ RX1, pins 3 and 5 of the switch SW1 are both connected to the second data receiving terminal URAT0_ RX 2; the switch SW2 has a pin 4 connected to the first data transmitter UART0_ TX1, and the switch SW2 has a pin 3 connected to the second data transmitter UART0_ TX 2.
4. The multi-level switching circuit for realizing communication flow control according to claim 1, wherein: the level conversion modules are provided with two groups and are respectively and independently connected between the switching module and the output module.
5. The multi-level switching circuit for realizing communication flow control according to claim 3, wherein: the RS422 level conversion module comprises a capacitor C1, resistors R1-R7 and a conversion chip U1, wherein the conversion chip U1 adopts a CBM3485AS chip; one end of each of the resistors R3, R4 and R6 is correspondingly connected to pins 2, 3 and 4 of the conversion chip U1, the other ends of the resistors R3, R4 and R6 are connected and then grounded, one end of the resistor R1 is connected to pin 1 of the conversion chip U1, the other end of the resistor R1 is connected to pin 2 of the switch SW1, pin 5 of the conversion chip U1 is grounded, one end of the resistor R5 is connected to one end of the resistor R2 and pin 7 of the conversion chip U1, the other end of the resistor R5 is connected to one end of the resistor R7 and pin 6 of the conversion chip U1, pin 8 of the conversion chip U1 is connected to one end of the capacitor C1 and then connected to the power supply terminal IO _ P3V3, and the other end of the capacitor C1 is grounded.
6. The multi-level switching circuit for realizing communication flow control according to claim 5, wherein: the RS485 level conversion module comprises a capacitor C2, resistors R8-R19, a conversion chip U2 and an MOS transistor Q1, wherein the conversion chip U2 adopts a CBM3485AS chip; one end of the resistor R15 is connected with one end of the resistor R18, and the connection point is connected with the 4 pins of the switch SW 2; the other end of the resistor R15 is connected to the power supply terminal IO _ P3V3, and the other end of the resistor R18 is grounded; the gate of the MOS transistor Q1 is connected with one end of each of the resistors R16 and R19, and the connection point is connected with pin 1 of the switch SW 2; the other end of the resistor R19 and the source of the MOS transistor Q1 are all grounded, the drain of the MOS transistor Q1 and the other end of the resistor R16, the pins 2 and 3 of the conversion chip U2 and one end of the resistor R8 are all connected, the other end of the resistor R8 is connected to the power supply terminal IO _ P3V3, the pin 1 of the conversion chip U2 is connected to the pin 8 of the switch SW1 through the resistor R10, the pin 4 of the conversion chip U2 is connected to the pin 4 of the switch SW2 through the resistor R13, the pin 5 of the conversion chip U2 is grounded, the pin 8 of the conversion chip U2 is connected to one end of the capacitor C2 and then connected to the power supply terminal IO _ P3V3, the other end of the capacitor C2 is grounded, the pin 7 of the conversion chip U2 is connected to one ends of the resistors R2 and the resistor R2, the pin 6 of the other end of the conversion chip U2 is connected to the power supply terminal IO _ P2 and the resistor R2 and the pin 3V 2, the other end of the resistor R9 is grounded.
7. The multi-level switching circuit for realizing communication flow control according to claim 6, wherein: the output module comprises capacitors C3-C6 and an interface CN1, the interface CN1 is provided with 10 pin pins, the pin 9 and the pin 10 of the interface CN1 are both grounded, one ends of the capacitors C3-C6 are grounded after being connected, the other end of the capacitor C3 is connected with the other end of the resistor R11, the other end of the capacitor C4 is connected with the other end of the resistor R14, the other end of the capacitor C5 is connected with the other end of the resistor R7, the other end of the capacitor C6 is connected with the other end of the resistor R2, and the other ends of the capacitors C3-C6 are correspondingly connected with the pin 1, the pin 3, the pin 5 and the pin 7 of the interface CN1 respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110924464.1A CN113688079B (en) | 2021-08-12 | 2021-08-12 | Multi-level switching circuit for realizing communication flow control |
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| JPS62211764A (en) * | 1986-03-12 | 1987-09-17 | Oki Electric Ind Co Ltd | Inter-circuit connection structure |
| CN101140557A (en) * | 2007-10-23 | 2008-03-12 | 中兴通讯股份有限公司 | System and method of RS232/RS48 compatibility interface |
| CN106571990A (en) * | 2016-10-31 | 2017-04-19 | 青岛海信电器股份有限公司 | Automatic communication mode switching circuit, display and display system |
| CN209708119U (en) * | 2019-06-14 | 2019-11-29 | 山东山大华天科技集团股份有限公司 | A kind of half-duplex RS 232-RS485 automatic switching circuit and communication equipment |
| CN210297899U (en) * | 2019-07-18 | 2020-04-10 | 江苏嘉擎信息技术有限公司 | Dual-mode DP switching circuit |
| CN212009333U (en) * | 2020-05-07 | 2020-11-24 | 山东超越数控电子股份有限公司 | Interface board compatible with multiple interface signals |
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2021
- 2021-08-12 CN CN202110924464.1A patent/CN113688079B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62211764A (en) * | 1986-03-12 | 1987-09-17 | Oki Electric Ind Co Ltd | Inter-circuit connection structure |
| CN101140557A (en) * | 2007-10-23 | 2008-03-12 | 中兴通讯股份有限公司 | System and method of RS232/RS48 compatibility interface |
| CN106571990A (en) * | 2016-10-31 | 2017-04-19 | 青岛海信电器股份有限公司 | Automatic communication mode switching circuit, display and display system |
| CN209708119U (en) * | 2019-06-14 | 2019-11-29 | 山东山大华天科技集团股份有限公司 | A kind of half-duplex RS 232-RS485 automatic switching circuit and communication equipment |
| CN210297899U (en) * | 2019-07-18 | 2020-04-10 | 江苏嘉擎信息技术有限公司 | Dual-mode DP switching circuit |
| CN212009333U (en) * | 2020-05-07 | 2020-11-24 | 山东超越数控电子股份有限公司 | Interface board compatible with multiple interface signals |
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