CN113675057B - Self-aligned graphene field emission grid structure and preparation method thereof - Google Patents
Self-aligned graphene field emission grid structure and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
- H01J1/304—Field-emissive cathodes
- H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/304—Field emission cathodes
- H01J2201/30403—Field emission cathodes characterised by the emitter shape
- H01J2201/30407—Microengineered point emitters
- H01J2201/30411—Microengineered point emitters conical shaped, e.g. Spindt type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/304—Field emission cathodes
- H01J2201/30446—Field emission cathodes characterised by the emitter material
- H01J2201/30453—Carbon types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2209/00—Apparatus and processes for manufacture of discharge tubes
- H01J2209/02—Manufacture of cathodes
- H01J2209/022—Cold cathodes
- H01J2209/0223—Field emission cathodes
Abstract
The invention relates to a self-aligned graphene field emission grid structure and a preparation method thereof, belonging to the field of vacuum electronic devices, wherein the self-aligned graphene field emission grid structure comprises: a substrate; the insulating layers are deposited on the substrate and are arranged at intervals on the substrate; a gate electrode is deposited on the insulating layer; the transmitting cone tip is arranged on the substrate between the insulating layers; graphene is tiled on the grid electrode; one electrode of the grid voltage power supply is arranged on the substrate, and the other electrode of the grid voltage power supply is arranged on the grid electrode and used for applying grid voltages with different sizes between the substrate and the grid electrode, so that the graphene is controllably etched, and a self-aligned grid electrode hole is formed. By applying a small grid voltage between the substrate and the grid electrode, a very large enhanced electric field can be formed at the emission cone tip, and the number of emitted electrons is changed by changing the size of the grid voltage, so that the upper Fang Danmo alkene layer is controllably etched, a self-aligned grid electrode hole is finally formed, the modulation voltage of the grid electrode is greatly reduced, and the electron transmittance is effectively improved.
Description
Technical Field
The invention relates to the field of vacuum electronic devices, in particular to a self-aligned graphene field emission grid structure and a preparation method thereof.
Background
Graphene has ultrahigh carrier mobility and saturation drift velocity, and has attracted wide attention in recent years, and is expected to be applied to the fields of high-speed electrons and radio frequency in the future.
Currently, vacuum electron emission has various forms such as thermionic emission, field electron emission, photoemission, and the like. The electron source has very important application in various vacuum electronic devices such as an X-ray source, a flat panel display, an electron microscope, an ion propeller and the like, but the electron emission cathode has the defects of low emission efficiency, low electron transmittance and incapability of being applied to a process for controllably etching a graphene layer.
As a core electron source of a vacuum electronic device, the Spindt cathode has the advantages of instantaneous starting, low power consumption, room-temperature working, high current density and the like, and is widely applied to the fields of X-ray tubes, flat panel displays, traveling wave tubes and the like, but no related research is currently available to apply the Spindt cathode to a process for controllably etching a graphene layer.
Accordingly, based on the above-mentioned problems, there is a need for a device with a self-aligned graphene field emission gate structure having good tuning performance.
Disclosure of Invention
The invention aims to provide a self-aligned graphene field emission grid structure and a preparation method thereof, which can greatly reduce grid modulation voltage, effectively improve electron transmittance and controllably etch graphene.
In order to achieve the above object, the present invention provides the following solutions:
a self-aligned graphene field emission gate structure, the self-aligned graphene field emission gate structure comprising:
a substrate;
the insulating layers are deposited on the substrate and are arranged on the substrate at intervals;
a gate electrode deposited on the insulating layer;
the emission cone tip is arranged on the substrate between the insulating layers;
graphene tiled on the gate;
and the grid voltage power supply is provided with one electrode which is arranged on the substrate and the other electrode which is arranged on the grid electrode and is used for applying grid voltages with different sizes between the substrate and the grid electrode so as to controllably etch the graphene and form a self-aligned grid electrode hole.
Optionally, the emission cone tip height is less than the total height of the insulating layer and the gate.
Optionally, the material of the insulating layer is any one of the following materials: siO (SiO) 2 、SiON、Al 2 O 3 。
Optionally, the material of the gate is any one of the following materials: molybdenum, niobium, chromium, silicon.
Optionally, the material of the emission cone tip is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide.
Optionally, the radius of curvature of the emission cone tip ranges from 5nm to 20nm.
Optionally, the height of the emission cone tip ranges from 800nm to 1.2 μm.
In order to achieve the above purpose, the present invention also provides the following solutions:
a method for fabricating a self-aligned graphene field emission gate structure, the method comprising:
selecting a substrate material and preparing a substrate;
preparing a transmitting cone tip and an oxide layer corresponding to the transmitting cone tip on the substrate; a mask layer is arranged on the transmitting cone tip;
preparing an insulating layer on the mask layer and the substrate by chemical vapor deposition or atomic layer deposition;
preparing a grid electrode on the insulating layer by using a thin film deposition method;
removing the oxide layer, the mask layer on the transmitting cone tip, the insulating layer and the grid electrode by utilizing a wet etching method to obtain a grid electrode structure;
transferring the graphene to the surface of the grid structure through wet transfer;
one pole of the gate voltage power supply is disposed on the substrate and the other pole is disposed on the gate.
Optionally, the preparing the emission cone tip and the oxide layer corresponding to the emission cone tip on the substrate specifically includes:
preparing a mask layer on a substrate by using a thermal oxidation process or a film deposition method, wherein the mask layer is used as a mask for subsequent etching of cone tips;
spin-coating a layer of glue on the surface of the mask layer;
photoetching the glue through ultraviolet photoetching or electron beam exposure to obtain a mask pattern array, and developing to obtain a pattern area;
etching the mask layer outside the pattern area through a reactive ion etching or inductively coupled plasma etching process;
removing the glue by adopting acetone and isopropanol in sequence to obtain a mask layer pattern array;
etching the mask layer pattern array to obtain a preliminary cone tip;
and sharpening the primary cone tip through a thermal oxidation process to obtain the emission cone tip and a corresponding oxide layer.
Optionally, etching the mask layer pattern array to obtain a preliminary cone tip, which specifically includes:
and etching the mask layer pattern array by adopting a reactive ion etching or inductive coupling plasma etching process to obtain a preliminary cone tip.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the self-aligned graphene field emission grid structure comprises a substrate, an emission cone tip, an insulating layer, a grid and graphene from bottom to top; one pole of the grid voltage power supply is applied to the substrate, the other pole is applied to the grid electrode, and a very large enhanced electric field can be formed at the tip by applying a very small grid voltage between the substrate and the grid electrode, so that the emission cone tip emits electrons. The number of emitted electrons is changed by changing the size of the grid voltage, so that the upper Fang Danmo alkene layer is controllably etched, and finally a self-aligned grid hole is formed, the modulation voltage of the grid is greatly reduced, and the electron transmittance is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic longitudinal cross-sectional view of a self-aligned graphene field emission gate structure of the present invention;
FIG. 2 is a flow chart of a method for fabricating a self-aligned graphene field emission gate structure of the present invention;
FIG. 3 is a schematic longitudinal cross-sectional view of a mask layer;
FIG. 4 is a schematic longitudinal cross-sectional view of a patterned array of a mask layer;
FIG. 5 is a schematic longitudinal cross-sectional view of a prepared cone tip;
FIG. 6 is a schematic longitudinal cross-sectional view of a sharpened tip;
FIG. 7 is a schematic longitudinal cross-sectional view of an insulating layer;
fig. 8 is a schematic longitudinal cross-sectional view of a fabricated gate.
FIG. 9 is a schematic longitudinal cross-sectional view of the removal of the oxide layer, mask layer on the emitter cone tip, insulating layer and gate;
FIG. 10 is a schematic view in longitudinal section after transfer and etching of graphene;
fig. 11 is a scanning electron microscope SEM image of an embodiment of the emission cone tip.
Symbol description:
the device comprises a substrate-1, an insulating layer-2, a grid electrode-3, an emission cone tip-4, graphene-5, a grid voltage power supply-6, a mask layer-7, glue-8, a preliminary cone tip-9 and an oxide layer-10.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a self-aligned graphene field emission grid structure which comprises a substrate, an emission cone tip, an insulating layer, a grid and graphene from bottom to top; one pole of the grid voltage power supply is applied to the substrate, the other pole is applied to the grid electrode, and a very large enhanced electric field can be formed at the tip by applying a very small grid voltage between the substrate and the grid electrode, so that the emission cone tip emits electrons. The number of emitted electrons is changed by changing the size of the grid voltage, so that the upper Fang Danmo alkene layer is controllably etched, and finally a self-aligned grid hole is formed, the modulation voltage of the grid is greatly reduced, and the electron transmittance is effectively improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
As shown in fig. 1, the self-aligned graphene field emission gate structure of the present invention includes: substrate 1, insulating layer 2, grid 3, emission cone point 4, graphite alkene 5 and grid voltage power supply 6.
Wherein the insulating layer 2 is deposited on the substrate 1, and the insulating layers 2 are spaced apart on the substrate 1. The insulating layer 2 is made of a material with a high dielectric constant. The material of the insulating layer 2 is any one of the following materials: siO (SiO) 2 、SiON、Al 2 O 3 But is not limited thereto. The thickness of the insulating layer 2 ranges from 800nm to 1.2 μm.
In this embodiment, the substrate 1 is a silicon wafer, and the thickness of the substrate 1 is 500um.
The gate electrode 3 is deposited on the insulating layer 2. The material of the gate electrode 3 is any one of the following materials: molybdenum, niobium, chromium, silicon, but are not limited thereto. The thickness of the grid electrode 3 ranges from 200nm to 400nm.
The emission cone tip 4 is arranged on the substrate 1 between the insulation layers 2. The material of the transmitting conical tip 4 is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide, but are not limited thereto. The radius of curvature of the transmitting cone tip 4 ranges from 5nm to 20nm. The height of the emission cone tip 4 is in the range of 800nm-1.2 mu m.
In this embodiment, the emission cone tip 4 is a silicon tip.
Preferably, the emission tip cone is obtained through an etching process. The height of the emission cone tip 4 is smaller than and close to the total height of the insulating layer 2 and the grid electrode 3.
The graphene 5 is tiled on the grid electrode 3.
One electrode of the grid voltage power supply 6 is added on the substrate 1, the other electrode of the grid voltage power supply 6 is added on the grid electrode 3, and the grid voltage power supply 6 is used for applying grid voltages with different sizes between the substrate 1 and the grid electrode 3 so as to controllably etch the graphene 5 to form self-aligned grid electrode holes.
Since the tip radius of the emission cone tip 4 is small, a very large enhanced electric field can be formed at the tip of the emission cone tip 4 by applying a small gate voltage between the substrate 1 and the gate electrode 3, so that the emission cone tip 4 emits electrons.
Further, the number of electrons reaching the graphene 5 at the emission cone tip 4 is changed by changing the size of the grid voltage, so that the upper Fang Danmo graphene 5 is controllably etched, and finally a self-aligned grid hole is formed, the modulation voltage of the grid 3 can be greatly reduced, and the electron transmittance is effectively improved.
As shown in fig. 2, the preparation method of the self-aligned graphene field emission gate structure of the present invention includes:
s1: the substrate material is selected and the substrate 1 is prepared. In this embodiment, the material of the substrate 1 is silicon. For ease of processing, the substrate 1 is cut into 1cm x 1cm square pieces.
S2: an emission cone tip 4 and an oxide layer 10 corresponding to the emission cone tip 4 are prepared on the substrate 1. As shown in fig. 3, a mask layer 7 is disposed on the emission cone tip 4. In particular, the height and tip radius of curvature of the emission cone tip 4 are primarily determined by etching parameters. Such as gas flow, pressure, etching time, temperature.
S3: as shown in fig. 7, the insulating layer 2 is prepared by chemical vapor deposition or atomic layer deposition on the mask layer 7 and on the substrate 1. In this embodiment, the material of the insulating layer 2 is SiO 2 。
S4: as shown in fig. 8, a gate electrode 3 is prepared on the insulating layer 2 using a thin film deposition method. Specifically, the gate electrode 3 may be prepared on the insulating layer 2 using an electron beam evaporation, magnetron sputtering, or chemical vapor deposition process. In this embodiment, the material of the gate electrode 3 is niobium Nb.
To match the height of the emission cone tip 4, siO 2 The thickness of the insulating layer is 800nm-1.2 μm, and the thickness of the gate Nb is 200nm-400nm.
S5: as shown in fig. 9, the oxide layer 10, the mask layer 7 on the emission cone tip 4, the insulating layer 2 and the gate electrode 3 are removed by a wet etching method, and a gate electrode structure is obtained. Specifically, the insulating layer 2 and the gate electrode 3 may be removed using hydrofluoric acid or a buffer solution of hydrofluoric acid.
Fig. 11 is an SEM diagram showing a specific example of the emission cone tip, and in this embodiment, the mask layer is etched by using a buffer solution BOE of hydrofluoric acid to obtain a Spindt type emission cone tip array structure. To prevent the insulating layer from being excessively corroded, it is necessary to precisely control the corrosion time.
S6: as shown in fig. 10, graphene 5 is transferred to the surface of the gate 3 structure by wet transfer.
S7: one pole of the gate voltage supply 6 is arranged on the substrate 1 and the other pole is arranged on the gate 3.
Preferably, the thickness of the insulating layer 2 and the gate electrode 3 is matched to the height of the emission cone tip 4. I.e. the sum of the thicknesses of the insulating layer 2 and the gate electrode 3 is greater than or equal to the height of the emission cone tip 4, in order to facilitate the transfer of the graphene 5.
Further, S2: preparing an emission cone tip 4 and an oxide layer 10 corresponding to the emission cone tip 4 on the substrate 1, wherein the method specifically comprises the following steps:
s21: a mask layer is prepared on the substrate 1 by using a thermal oxidation process or a thin film deposition method and is used as a mask for subsequent etching of the taper. Specifically, the mask layer 7 may be prepared using magnetron sputtering, electron beam evaporation, atomic layer deposition, molecular beam epitaxy, or chemical vapor deposition processes. The mask layer 7 is made of SiO 2 Or SiN, but is not limited thereto. The thickness of the mask layer 7 is in the range of 50nm-1um, in this embodiment 300nm.
S22: as shown in part (a) of fig. 4, a layer of glue 8 is spin-coated on the surface of the mask layer. Specifically, a photoresist or an electron beam glue layer is coated on the surface of the mask layer in a spin mode.
S23: as shown in fig. 4 (b), the photoresist 8 is subjected to ultraviolet lithography or electron beam exposure to obtain a mask pattern array, and a pattern region is obtained after development. In this embodiment, the glue used in preparing the mask pattern array by ultraviolet lithography is SUN-9i, and the glue used in preparing the mask pattern array by electron beam exposure is HSQ, but is not limited to these two glues.
S24: as shown in part (c) of fig. 4, the mask layer outside the pattern region is etched by a reactive ion etching or an inductively coupled plasma etching process.
S25: as shown in part (d) of fig. 4, the photoresist 8 is removed using acetone and isopropyl alcohol sequentially, to obtain a mask layer pattern array. Specifically, the pattern array of the mask layer 7 is periodically arranged, and may be square or round, with a diameter or side length of 1.5um and a spacing of 10um.
S26: as shown in fig. 5, the mask layer pattern array is etched to obtain a preliminary cone tip 9. Specifically, a reactive ion etching or an inductively coupled plasma etching process is adopted to etch the mask layer pattern array, so as to obtain the preliminary cone tip 9. Specifically, the height and radius of curvature of the cone tip are determined by the etching parameters. Such as gas flow, pressure, etching time, temperature.
S27: as shown in fig. 6, the preliminary cone tip 9 is sharpened by a thermal oxidation process to obtain the emission cone tip 4 and the corresponding oxide layer 10. The radius of the emission cone tip 4 is between 5 and 20nm.
Further, when the preliminary cone tip 9 is sharpened by adopting a thermal oxidation process, an oxide layer 10 is formed corresponding to the emission cone tip 4. The thickness of the oxide layer 10 is determined by the thermal oxidation temperature and the oxidation time, and the thickness of the oxide layer 10 ranges from 100nm to 200nm. In this embodiment, the thickness of the oxide layer 10 is in the range of 50nm to 1um.
Compared with the prior art, the preparation method of the self-aligned graphene field emission gate structure has the same beneficial effects as the self-aligned graphene field emission gate structure, and is not repeated herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (10)
1. A self-aligned graphene field emission gate structure, the self-aligned graphene field emission gate structure comprising:
a substrate;
the substrate is a semiconductor or conductive substrate;
the insulating layers are deposited on the substrate and are arranged on the substrate at intervals;
a gate electrode deposited on the insulating layer;
the emission cone tip is arranged on the substrate between the insulating layers;
the height of the emission cone tip is smaller than and close to the total height of the insulating layer and the grid electrode;
graphene tiled on the gate;
and the grid voltage power supply is provided with one electrode which is arranged on the substrate and the other electrode which is arranged on the grid electrode and is used for applying grid voltages with different sizes between the substrate and the grid electrode so as to controllably etch the graphene and form a self-aligned grid electrode hole.
2. The self-aligned graphene field emission gate structure according to claim 1, wherein the emission cone tip height is less than the total height of the insulating layer and the gate.
3. The self-aligned graphene field emission gate structure according to claim 1, wherein the material of the insulating layer is any one of the following materials: siO (SiO) 2 、SiON、Al 2 O 3 。
4. The self-aligned graphene field emission gate structure according to claim 1, wherein the material of the gate is any one of the following materials: molybdenum, niobium, chromium, silicon.
5. The self-aligned graphene field emission gate structure according to claim 1, wherein the material of the emission cone tip is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide.
6. The self-aligned graphene field emission gate structure according to claim 1, wherein the radius of curvature of the emission cone tip ranges from 5nm to 20nm.
7. The self-aligned graphene field emission gate structure according to claim 1, wherein the emission cone tip has a height ranging from 800nm to 1.2 μm.
8. The preparation method of the self-aligned graphene field emission gate structure is characterized by comprising the following steps of:
selecting a substrate material and preparing a substrate;
the substrate is a semiconductor or conductive substrate;
preparing a transmitting cone tip and an oxide layer corresponding to the transmitting cone tip on the substrate; a mask layer is arranged on the transmitting cone tip;
preparing an insulating layer on the mask layer and the substrate by chemical vapor deposition or atomic layer deposition;
preparing a grid electrode on the insulating layer by using a thin film deposition method;
removing the oxide layer, the mask layer on the transmitting cone tip, the insulating layer and the grid electrode by utilizing a wet etching method to obtain a grid electrode structure;
the height of the emission cone tip is smaller than and close to the total height of the insulating layer and the grid electrode;
transferring the graphene to the surface of the grid structure through wet transfer;
setting one pole of grid voltage power supply on the substrate and the other pole on the grid;
and applying grid voltages with different magnitudes between the substrate and the grid electrode through a grid voltage power supply, and controllably etching the graphene to form a self-aligned grid electrode hole.
9. The method for preparing a self-aligned graphene field emission gate structure according to claim 8, wherein preparing an emission cone tip and an oxide layer corresponding to the emission cone tip on the substrate specifically comprises:
preparing a mask layer on a substrate by using a thermal oxidation process or a film deposition method, wherein the mask layer is used as a mask for subsequent etching of cone tips;
spin-coating a layer of glue on the surface of the mask layer;
photoetching the glue through ultraviolet photoetching or electron beam exposure to obtain a mask pattern array, and developing to obtain a pattern area;
etching the mask layer outside the pattern area through a reactive ion etching or inductively coupled plasma etching process;
removing the glue by adopting acetone and isopropanol in sequence to obtain a mask layer pattern array;
etching the mask layer pattern array to obtain a preliminary cone tip;
and sharpening the primary cone tip through a thermal oxidation process to obtain the emission cone tip and a corresponding oxide layer.
10. The method for preparing a self-aligned graphene field emission gate structure according to claim 9, wherein the etching the mask layer pattern array to obtain a preliminary cone tip specifically comprises:
and etching the mask layer pattern array by adopting a reactive ion etching or inductive coupling plasma etching process to obtain a preliminary cone tip.
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| CN202110793595.0A CN113675057B (en) | 2021-07-12 | 2021-07-12 | Self-aligned graphene field emission grid structure and preparation method thereof |
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| CN202110793595.0A CN113675057B (en) | 2021-07-12 | 2021-07-12 | Self-aligned graphene field emission grid structure and preparation method thereof |
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