CN113629007A - Method for manufacturing contact hole - Google Patents
Method for manufacturing contact hole Download PDFInfo
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- CN113629007A CN113629007A CN202110856792.2A CN202110856792A CN113629007A CN 113629007 A CN113629007 A CN 113629007A CN 202110856792 A CN202110856792 A CN 202110856792A CN 113629007 A CN113629007 A CN 113629007A
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- etching
- interlayer dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a manufacturing method of a contact hole, which comprises the following steps: providing a substrate, wherein grid electrodes are formed on the substrate, side walls are formed on two sides of the grid electrodes, a silicification blocking layer is formed in the substrate between the grid electrodes, interlayer dielectric layers are formed on the grid electrodes and the side walls, and a multilayer film structure is formed on the interlayer dielectric layers; covering the photoresist by adopting a photoetching process to expose a target area, wherein the target area is positioned between the grids; etching to remove the multilayer film structure and the interlayer dielectric layer in the target area to expose the substrate in the target area, and introducing reaction gas to remove polymers generated in the etching process; removing the photoresist; and etching is carried out, the silicide blocking layer is removed, and a through hole is formed in the target area and is used for forming a contact through hole. According to the method, the polymer generated in the etching process is removed by introducing the reaction gas in the process of etching the multilayer film structure, so that the polymer can be removed more thoroughly, and the reliability and yield of devices are improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a contact hole.
Background
In an integrated circuit, a Contact (CT) is a structure for connecting a front-end device and a back-end interconnection metal, which is formed by filling a metal after forming a via hole by etching in an interlayer dielectric (ILD).
In order to further reduce the critical dimension of the contact hole size, the via hole etching can be carried out by using a polymer-rich etching process in the manufacturing process of the via hole etching. In the process of etching the through hole, a solvent in the wet cleaning process is easy to react with a polymer (the polymer is usually deposited at an etching stop layer and a junction interface) generated in the dry etching process, and is continuously etched transversely to the etching stop layer, so that the phenomena of uneven and discontinuous etching on the side wall of the through hole can occur at a high probability, a wedge-shaped gap can be formed at the junction interface of an interlayer dielectric layer and the etching stop layer in serious conditions, the filling of metal in the contact hole can be influenced by the morphology, and the reliability of a device and the yield of products are reduced.
In view of this, in the related art, after the via etching is completed, a Post Etch Treatment (PET) is performed to remove the polymer. However, the polymer is treated with this method with poor effect, and the yield of the device is still low.
Disclosure of Invention
The application provides a manufacturing method of a contact hole, which can solve the problem that in the manufacturing method of the contact hole provided in the related technology, the polymer removal effect is poor through surface post-etching treatment, so that the reliability and yield of a device are poor.
In one aspect, an embodiment of the present application provides a method for manufacturing a contact hole, including:
providing a substrate, wherein grid electrodes are formed on the substrate, side walls are formed on two sides of the grid electrodes, a silicification blocking layer is formed in the substrate between the grid electrodes, interlayer dielectric layers are formed on the grid electrodes and the side walls, and multilayer film structures are formed on the interlayer dielectric layers;
covering the photoresist by adopting a photoetching process to expose a target region, wherein the target region is positioned between the grids;
etching is carried out, the multilayer film structure and the interlayer dielectric layer of the target area are removed, the substrate of the target area is exposed, and in the etching process, reaction gas is introduced to remove polymers generated in the etching process;
removing the photoresist;
and etching is carried out, the silicide block (SAB) is removed, a through hole is formed in the target area, and the through hole is used for forming the contact through hole.
Optionally, the etching to remove the multilayer film structure and the interlayer dielectric layer in the target region includes:
etching, removing the multilayer film structure of the target area, and introducing the reaction gas to remove the polymer;
etching, removing the interlayer dielectric layer of the target region, and introducing the reaction gas to remove the polymer;
and etching for multiple times, removing the side wall in the target region to expose the substrate in the target region, and introducing the reaction gas to remove the polymer after each etching.
Optionally, the reactant gas comprises oxygen (O)2)。
Optionally, in the process of removing the polymer, the pressure of the introduced reaction gas is.
Optionally, the silicide blocking layer and the interlayer dielectric layer include an oxide, and the sidewall spacer includes a nitride;
and in the process of carrying out multiple times of etching, the etching selection ratio of the oxide to the nitride is more than 5.
Optionally, the etching to remove the interlayer dielectric layer in the target region includes:
and sequentially performing main etching and over-etching to remove the interlayer dielectric layer of the target area.
Optionally, the multilayer film structure sequentially includes an Advanced Patterning Film (APF), a hardmask anti-reflection layer (DARC), and a bottom anti-reflection layer (BARC) from bottom to top.
The technical scheme at least comprises the following advantages:
in the process of etching the multilayer film structure, reaction gas is introduced to remove polymers generated in the etching process, so that the polymers on the side wall of the through hole can be removed more thoroughly, the appearance of the through hole is improved, and the reliability and yield of the device are improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for forming a contact hole according to an exemplary embodiment of the present disclosure;
FIG. 2 is a schematic cross-sectional view of a contact hole formed with a small overlay error;
FIG. 3 is a schematic cross-sectional view of a contact hole formed with a large overlay error by a method for forming a contact hole according to the related art;
fig. 4 is a schematic cross-sectional view of a contact hole formed by the contact hole manufacturing method provided by the present application when an overlay error is large.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, which shows a flowchart of a method for forming a contact hole according to an exemplary embodiment of the present application, as shown in fig. 1, the method includes:
Optionally, the multilayer film structure sequentially comprises an advanced pattern material layer, a hard mask anti-reflection layer and an organic material anti-reflection layer from bottom to top. For example, after a gate and sidewalls on both sides of the gate are formed on a substrate, an oxide is deposited to form an interlayer dielectric layer, and a pattern material layer, a hard mask anti-reflection layer, and an organic material anti-reflection layer are sequentially formed on the interlayer dielectric layer. The grid-connected type silicon-based solar cell comprises a substrate, a grid oxide, a heavily doped region and a silicification blocking layer, wherein a plurality of grids are formed on the substrate, the grid oxide is formed between the grids and the substrate, the heavily doped region is formed in the substrate between the grids, and the silicification blocking layer is formed in the heavily doped region.
Wherein the target region is a region for forming a contact hole. For example, the multilayer film structure may be covered with a photoresist, exposed to a target area, and developed to remove the photoresist in the target area and expose the target area.
103, etching to remove the multilayer film structure and the interlayer dielectric layer in the target area, exposing the substrate in the target area, and introducing reaction gas to remove polymers generated in the etching process.
Optionally, step 103 may be performed by three etchings, which include but are not limited to: etching, removing the multilayer film structure in the target area, and introducing reaction gas to remove the polymer; etching, removing the interlayer dielectric layer of the target region, and introducing reaction gas to remove the polymer; and etching for multiple times, removing the side wall in the target region to expose the substrate in the target region, and introducing reaction gas to remove the polymer after each etching.
In which, Main Etching (ME) and Over Etching (OE) may be sequentially performed to remove the interlayer dielectric layer of the target region.
After each etching, reaction gas is introduced to remove the polymer, so that the polymer on the side wall of the through hole formed by etching can be effectively removed, and particularly the polymer on the joint interface of the interlayer dielectric layer and the etching stop layer (side wall).
Optionally, the introduced reaction gas comprises oxygen, and the pressure of the introduced reaction gas is.
Illustratively, ashing (ashing) may be used to remove the photoresist.
And 105, etching to remove the silicide blocking layer and form a through hole in the target area, wherein the through hole is used for forming a contact through hole.
After step 105, a metal layer may be formed, the metal layer fills the via hole, a planarization process (for example, a Chemical Mechanical Polishing (CMP) process may be used for planarization process) is performed on the metal layer, and the metal layer in the remaining via hole forms a contact hole. The metal layer may be formed by electroplating or Physical Vapor Deposition (PVD), and may include a copper layer, a tungsten layer, or an aluminum layer.
Referring to fig. 2, which shows a schematic diagram of a contact hole formed, as shown in fig. 2, a gate oxide 220 is formed on a substrate 210, a gate 230 is formed on the gate oxide 220, sidewalls 240 are formed on two sides of the gate 230, a heavily doped region 201 is formed in the substrate 210 between the gates 230, the gate 230 and the gate oxide 220 are formed in an interlayer dielectric layer 250, a contact hole 260 is formed between the gates 230, and a bottom end of the contact hole 260 is connected to the heavily doped region 201.
In summary, in the embodiment of the application, the polymer generated in the etching process is removed by introducing the reaction gas in the process of etching the multilayer film structure, so that the polymer on the side wall of the through hole can be removed more thoroughly, the morphology of the through hole is improved, and the reliability and yield of the device are improved.
Optionally, in this embodiment, the sidewall spacer includes nitride, and in step 103, during the process of performing multiple etching and removing the sidewall spacer in the target region, an etching selectivity (etching rate ratio) of the oxide to the nitride is greater than 5 (for example, the etching selectivity may be 10).
With the advance of semiconductor process nodes, the size of a semiconductor device is smaller and smaller, requirements on the size of a heavily doped region are provided in many fields, and the ion implantation area needs to be reduced. However, due to the reduction of the area of the heavily doped region, a higher requirement is also put forward on the alignment precision of the through hole etching, and if the alignment error is larger, the position of the contact hole is shifted, so that the reliability of the device is reduced. As shown in fig. 3, when the overlay error is large, the contact hole 260 is shifted.
In view of this, by setting the etching selection ratio of the oxide to the nitride to be greater than 5 in the process of removing the sidewall in the target region, when the overlay error is large, the removal amount of the sidewall can be reduced in the etching process, so as to prevent the bottom end of the subsequently formed contact hole from shifting to the non-target region, and as shown in fig. 4, the contact hole 260 formed in this way has a large overlay error, but the contact hole 260 is blocked by the sidewall 240, and the offset of the bottom thereof is small.
Taking the CIS as an example, the pixel unit (pixel) can be implemented by reducing the source/drain (source/drain) capacitance of the photodiode in order to enhance the photodiode signal under the condition that the Photodiode (PD) collects a certain amount of light. One way to reduce the capacitance is to reduce the area of ion implantation in the source and drain regions, which is achieved by improving the gate sidewall process, however, this way puts higher demands on the process accuracy of the contact holes in the source and drain regions: the contact hole must be stopped in the ion implantation area of the source drain area, otherwise the junction (junction) capacitance of the photodiode is not easy to control, and the product performance is difficult to reach the standard.
The main influence on the process accuracy of the contact hole is that the contact hole passes through the photoetching and etching steps in the etching process, wherein the control of the critical dimension and the overlay accuracy (overlay) of the photoetching is crucial. To reduce the above mentioned effect, a contact hole self-alignment process can be adopted, and the principle is shown in the figure: with SAB/ILD (both including oxide (e.g., silicon dioxide SiO)2) And sidewalls (including nitride (e.g., silicon nitride, Si)3N4) The contact hole is self-aligned to the source and drain regions due to the high etching selection ratio, even if the alignment precision is poor and the contact hole is offset, the contact hole can still be self-aligned to the source and drain regions, and the cost of the photoetching process is reduced.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for manufacturing a contact hole is characterized by comprising the following steps:
providing a substrate, wherein grid electrodes are formed on the substrate, side walls are formed on two sides of the grid electrodes, a silicification blocking layer is formed in the substrate between the grid electrodes, interlayer dielectric layers are formed on the grid electrodes and the side walls, and multilayer film structures are formed on the interlayer dielectric layers;
covering the photoresist by adopting a photoetching process to expose a target region, wherein the target region is positioned between the grids;
etching is carried out, the multilayer film structure and the interlayer dielectric layer of the target area are removed, the substrate of the target area is exposed, and in the etching process, reaction gas is introduced to remove polymers generated in the etching process;
removing the photoresist;
and etching is carried out, the silicification blocking layer is removed, and a through hole is formed in the target area and is used for forming the contact through hole.
2. The method of claim 1, wherein the etching to remove the multilayer film structure and the interlayer dielectric layer of the target region comprises:
etching, removing the multilayer film structure of the target area, and introducing the reaction gas to remove the polymer;
etching, removing the interlayer dielectric layer of the target region, and introducing the reaction gas to remove the polymer;
and etching for multiple times, removing the side wall in the target region to expose the substrate in the target region, and introducing the reaction gas to remove the polymer after each etching.
3. The method of claim 2, wherein the reactant gas comprises oxygen.
4. The method according to claim 3, wherein the pressure of the reaction gas is introduced during the polymer removal.
5. The method of claim 4, wherein the silicide block layer and the interlevel dielectric layer comprise an oxide, and the sidewall spacers comprise a nitride;
and in the process of carrying out multiple times of etching, the etching selection ratio of the oxide to the nitride is more than 5.
6. The method of any of claims 1 to 5, wherein the etching to remove the interlayer dielectric layer of the target region comprises:
and sequentially performing main etching and over-etching to remove the interlayer dielectric layer of the target area.
7. The method of claim 6, wherein the multilayer film structure comprises an advanced pattern material layer, a hard mask anti-reflection layer and an organic material anti-reflection layer in sequence from bottom to top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110856792.2A CN113629007A (en) | 2021-07-28 | 2021-07-28 | Method for manufacturing contact hole |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110856792.2A CN113629007A (en) | 2021-07-28 | 2021-07-28 | Method for manufacturing contact hole |
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| CN113629007A true CN113629007A (en) | 2021-11-09 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730349A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN104347486A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN104347485A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN111725247A (en) * | 2020-07-23 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Self-alignment etching method for drain-source contact hole of CIS chip |
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2021
- 2021-07-28 CN CN202110856792.2A patent/CN113629007A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730349A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN104347486A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN104347485A (en) * | 2013-08-06 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN111725247A (en) * | 2020-07-23 | 2020-09-29 | 华虹半导体(无锡)有限公司 | Self-alignment etching method for drain-source contact hole of CIS chip |
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