CN113611698A - Semiconductor structure and layout thereof - Google Patents

Semiconductor structure and layout thereof Download PDF

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Publication number
CN113611698A
CN113611698A CN202011201934.3A CN202011201934A CN113611698A CN 113611698 A CN113611698 A CN 113611698A CN 202011201934 A CN202011201934 A CN 202011201934A CN 113611698 A CN113611698 A CN 113611698A
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gate
semiconductor
structures
patterns
pattern
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CN113611698B (en
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张维峻
张幼弟
黄清俊
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor structure and a layout thereof, wherein the semiconductor layout comprises a substrate pattern surrounding an isolation region pattern, a plurality of dummy patterns positioned in the isolation region pattern, a plurality of gate patterns positioned in the isolation region pattern and passing through between the dummy patterns, and a plurality of resistance patterns positioned in the isolation region pattern and overlapping with the gate patterns.

Description

Semiconductor structure and layout thereof
Technical Field
The present invention relates to a semiconductor structure and a layout thereof, and more particularly, to a semiconductor structure including an embedded resistor structure and a semiconductor layout including an embedded resistor pattern.
Background
In advanced semiconductor technology, a system on a chip (SOC) integrates various analog signal circuits, digital signal circuits, and mixed signal circuits into one chip, which can reduce the production cost, increase the performance, and reduce the power consumption. Products such as personal computers, automobile recorders, televisions, mobile phones and the like are all benefited by the design and implementation of a system single chip. The system on a chip often includes passive components such as embedded resistors (embedded resistors) for voltage power regulation, so that the circuit can operate smoothly. How to successfully integrate and fabricate the embedded resistor in the chip is a subject of active research in the field.
Disclosure of Invention
To achieve the above objective, the present invention provides a semiconductor structure including an embedded resistor structure and a semiconductor layout for fabricating the semiconductor structure, which can improve the process margin of the semiconductor structure and the yield of the product.
An embodiment of the present invention provides a semiconductor layout including a substrate pattern surrounding an isolation region pattern, a plurality of dummy patterns in the isolation region pattern, a plurality of gate patterns in the isolation region pattern and passing between the dummy patterns, and a plurality of resistor patterns in the isolation region pattern and overlapping the gate patterns.
Another embodiment of the present invention provides a semiconductor structure, which includes a substrate having an isolation structure surrounding a plurality of island structures. An interlayer dielectric layer is disposed on the substrate. A plurality of first gate structures are located in the interlayer dielectric layer and on the isolation structure. A plurality of resistor structures are positioned on the interlayer dielectric layer and are respectively aligned with the gate structures, wherein the gate structures and the resistor structures comprise different materials.
Drawings
FIG. 1 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 1A is an enlarged plan view of a region A of the semiconductor layout of FIG. 1;
FIG. 1B is an enlarged plan view of a region B of the semiconductor layout of FIG. 1;
FIG. 2 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 3 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 4 is a schematic plan view of a semiconductor layout according to an embodiment of the present invention;
FIG. 5 is a schematic plan view of a semiconductor structure according to an embodiment of the present invention;
FIG. 6A is an enlarged schematic plan view of region A of the semiconductor structure of FIG. 5;
FIG. 6B is an enlarged schematic plan view of region B of the semiconductor structure of FIG. 5;
FIG. 7A is a schematic cross-sectional view taken along line I-I' of FIG. 6A through a semiconductor structure;
FIG. 7B is a schematic cross-sectional view taken along line II-II' of FIG. 6B;
FIG. 8A is a schematic cross-sectional view taken along line I-I' of FIG. 6A through a semiconductor structure; fig. 8B is a cross-sectional view of the semiconductor structure taken along line II-II' shown in fig. 6B.
Description of the main elements
102 pattern of the substrate
104 resistance mark region
106 dummy pattern
107 active (active) region pattern
108 isolation region pattern
110 grid pattern
111 gate pattern
112 resistance pattern
202 substrate
206 island structure
208 isolation structure
210 active region
212 gate body
213 spacer
214 work function metal layer
215 low resistance metal
230 interlayer dielectric layer
232 etch stop layer
100a semiconductor layout
100b semiconductor layout
100c semiconductor layout
100d semiconductor layout
200a semiconductor structure
200b semiconductor structure
234a resistive layer
234b hard mask layer
Region A
Region B
D1 first direction
D2 second direction
Third direction D3
G grid structure
G' grid structure
I-I' tangent line
II-II' tangent line
RS1 gate structure
RS1' gate structure
RS2 resistance structure
S/D source/drain region
Detailed Description
In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.
In order to make the reader easy to understand and the drawings are simplified, the drawings in the present disclosure only show a part of the display device, and the specific elements in the drawings are not drawn to actual scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure. In the drawings, the same or similar elements may be denoted by the same reference numerals. The relative positions of the elements in the figures are described as relative to each other, and thus, the relative positions of the elements in the figures should be understood by those skilled in the art to be equivalent to each other, and all such elements should be considered as falling within the scope of the present disclosure.
Fig. 1, 1A and 1B are schematic plan views of a semiconductor layout 100a according to an embodiment of the invention, in which fig. 1A is an enlarged plan view of a region a of the semiconductor layout 100a, and fig. 1B is an enlarged plan view of a region B of the semiconductor layout 100 a.
The semiconductor layout 100a is an integrated circuit chip (chip) design layout that can be stored and read by a computer system, and includes a plurality of pattern layers for defining a stacked structure of the integrated circuit chip. According to an embodiment of the present invention, the region a of the semiconductor layout 100a is, for example, a passive (passive) device region including an embedded resistor pattern, and the region B is, for example, an active device region including a transistor, which are not overlapped.
Referring to fig. 1A, the region a of the semiconductor layout 100a may include a base pattern 102, an isolation region pattern 108 surrounded by the base pattern 102, a plurality of dummy patterns 106, a plurality of gate patterns 110, and a plurality of resistor patterns 112.
It should be noted that, in a plan view, the shape of the isolation region pattern 108 and the case where the edge thereof is completely surrounded by the base pattern 102 are illustrated for illustrative purposes, and the present invention is not limited thereto. In other embodiments, the isolation region pattern 108 may have a different shape and only a portion of the edge is surrounded by the base pattern 102. In some embodiments, the semiconductor layout 100a further includes a resistance mark region 104 for marking the resistance region of the region a. In some embodiments, the extent of the isolation region pattern 108 of the area a substantially overlaps the extent of the resistive mark region 104.
The dummy patterns 106 are positioned in the isolation region pattern 108, arranged in an array along the first direction D1 and the second direction D2, and spaced apart from the edge of the isolation region pattern 108 by a distance not to overlap the edge of the isolation region pattern 108. In some embodiments, the first direction D1 and the second direction D2 are perpendicular to each other. The shape of the dummy pattern 106 may include a rectangle, but is not limited thereto. In some embodiments, the percentage of the total area of the dummy patterns to the area of the resistive mark region 104 is greater than 0% and less than 50%.
The gate patterns 110 are positioned in the isolation region patterns 108, extend along the first direction D1 and are arranged in parallel along the second direction D2, passing between the dummy patterns 106. The dummy pattern 106 is spaced apart from the edge of the gate pattern 110 by a distance, and does not overlap.
The resistance patterns 112 are positioned in the isolation region patterns 108, extend along the first direction D1 and are arranged in parallel along the second direction D2, pass between the dummy patterns 106, and overlap the gate patterns 110. In some embodiments, the resistive pattern 112 and the gate pattern 110 may be completely overlapped.
Referring to fig. 1B, the region B may include a base pattern 102, an isolation region pattern 108 surrounded by the base pattern 102, an active region pattern 107 surrounded by the isolation region pattern 108, and a gate pattern 111 overlapping the active region pattern 107. The gate pattern 111 extends (e.g., along the first direction D1) across the active region pattern 107.
It should be noted that the base pattern 102, the isolation region pattern 108, and the dummy pattern 106 in the region a and the base pattern 102, the isolation region pattern 108, and the active region pattern 107 in the region B all belong to the same pattern layer of the semiconductor layout 100a, and are output to the same photomask (e.g., a base pattern photomask) for patterning the base of the semiconductor structure (e.g., the base 202 of the semiconductor structure 200a in fig. 7A). The gate pattern 110 of the region a and the gate pattern 111 of the region B belong to the same pattern layer of the semiconductor layout 100a, and are output to the same photomask (e.g., gate pattern photomask) for patterning a gate material layer on the semiconductor structure substrate. The resistive pattern 112 of region a will be output to yet another photomask (e.g., a resistive pattern photomask) for patterning a resistive material layer of the semiconductor structure.
Referring to fig. 2, 3 and 4, which are schematic plan views of a semiconductor layout according to some embodiments of the present invention, it is illustrated that the layout of the dummy pattern 106 may be adjusted according to the design or manufacturing process requirements. For example, as shown in fig. 2, the edges of the dummy pattern 106 and the edges of the partial gate pattern 110 and the resistance pattern 112 of the semiconductor layout 100b may overlap and be aligned. As shown in fig. 3, the dummy patterns 106 of the semiconductor layout 100c may be aligned along the first direction D1 and staggered along the second direction D2. As shown in fig. 4, the dummy patterns 106 of the semiconductor layout 100D may extend along the extending direction (e.g., the first direction D1) of the gate patterns 110, have substantially the same length as the gate patterns 110, and are staggered from the gate patterns 110 along the second direction D2.
Please refer to fig. 5, fig. 6A, fig. 6B, fig. 7A and fig. 7B. Fig. 5 is a schematic plan view of a semiconductor structure 200a according to an embodiment of the invention, fig. 6A and 6B are enlarged schematic plan views of a region a and a region B of fig. 5, respectively, fig. 7A is a schematic cross-sectional view taken along a line I-I 'shown in fig. 6A, and fig. 7B is a schematic cross-sectional view taken along a line II-II' shown in fig. 6B. It is to be noted that, for the sake of simplicity, parts of the structures (such as the interlayer dielectric layer 230 and the etch stop layer 232) in fig. 7A and 7B are not shown in fig. 5, 6A and 6B. The semiconductor structure 200a is fabricated, for example, by a semiconductor fabrication process using a set of photomasks including the pattern of the semiconductor layout 100a shown in fig. 1, 1A, and 1B.
As shown in fig. 5, the semiconductor structure 200a includes a substrate 202, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, or other suitable semiconductor substrate, but not limited thereto. In some embodiments, the substrate is, for example, a silicon wafer. At least a region a and a region B are defined on the substrate 202. The region a is, for example, a passive device region including an embedded resistor structure, and the region B is, for example, an active device region including a transistor, which are not overlapped with each other.
As shown in fig. 6A and 7A, the region a of the semiconductor structure 200a includes a substrate 202, an isolation structure 208 surrounded by the substrate 202, a plurality of island-shaped structures 206 disposed in the isolation structure 208 and surrounded by the isolation structure 208, an interlayer dielectric layer 230 disposed on the substrate 202, a plurality of gate structures RS1 (first gate structures) disposed in the interlayer dielectric layer 230, and a plurality of resistor structures RS2 disposed directly above the gate structures RS 1. In some embodiments, the island structures 206 may include a rectangular shape in plan view and are arranged in an array along the first direction D1 and the second direction D2. The island structures 206 are separated from the substrate 202 by the isolation structures 208 and do not make direct contact. In some embodiments, the semiconductor structure 200a may include an etch stop layer 232 on the ild layer 230 and covering the gate structure RS 1.
As shown in fig. 6B and 7B, the region B includes the substrate 202, another isolation structure 208 surrounded by the substrate 202, an active region 210 surrounded by the isolation structure 208, an interlayer dielectric layer 230 on the substrate 202, a gate structure G (second gate structure) disposed in the interlayer dielectric layer 230 and on the active region 210, and source/drain regions S/D in the active region 210 at two sides of the gate structure G. In some embodiments, the gate structure G extends (e.g., along the first direction D1) across the active region 110. In some embodiments, the etch stop layer 232 extends to the interlayer dielectric layer 230 in the region B and covers the gate structure G.
It should be noted that, in a plan view, the shapes of the isolation structures 208 in the region a and the region B and the edges thereof completely surrounded by the substrate 202 are illustrated in fig. 6A and 6B for illustrative purposes, and the invention is not limited thereto. In other embodiments, the isolation structure 208 may have a different top-down shape and be surrounded only partially by the substrate 202.
The isolation structures 208, island structures 206, and active regions 210 of the regions a and B are formed simultaneously on the substrate 202 by the same fabrication process. For example, a photolithography and etching process may be performed using a substrate pattern photomask including the substrate pattern 102, the isolation region pattern 108 and the dummy pattern 106 of the region a of fig. 1A and the substrate pattern 102, the isolation region pattern 108 and the active region pattern 107 of the region B of fig. 1B, the pattern of the photomask may be transferred into the substrate 202 to form an insulation trench, the island-like structure 206 and the active region 210 may be defined, an insulation material layer (e.g., silicon oxide) may be deposited on the substrate 202 to fill the insulation trench, and a Chemical Mechanical Polishing (CMP) process may be performed to remove excess insulation material outside the insulation trench, so as to obtain the isolation structure 208 shown in fig. 7A and 7B.
A gate structure RS1 (first gate structure) and a gate structure G (second gate structure) are located in the interlayer dielectric layer 230 in the region a and the region B, respectively. The gate structures RS1 are located primarily on the isolation structures 208 and between the island structures 206. The gate structure G is mainly located on the active region 210, and extends across the active region 210 and partially located on the isolation structure 208. The gate structures RS1 and G each include a gate body 212 and spacers 213 disposed on two sides of the gate body 212. Preferably, the gate structure RS1 and the gate structure G have substantially the same height, and the top surfaces thereof are flush with each other.
In some embodiments, the gate structure RS1 and the resistor structure RS2 may be embedded resistors of the semiconductor structure 200a, respectively. In other embodiments, the gate structure RS1 may be a dummy structure that is electrically floating (floating), and is not electrically connected to other components.
The gate structure RS1 and the gate structure G can be formed on the substrate 202 simultaneously by the same manufacturing process. For example, a photolithography and etching process may be performed using a gate pattern photomask including the gate pattern 110 of fig. 1A and the gate pattern 111 of fig. 1B, the pattern of the photomask is transferred to a gate material layer on the substrate 202, the gate body 212 of the gate structure RS1 and the gate body 212 of the gate structure G are formed at the same time, a dielectric material layer is deposited on the substrate 202 to cover each gate body 212, and an anisotropic etching process is performed to remove a portion of the dielectric material layer, so that the remaining dielectric material layer is self-aligned on the sidewall of each gate body 212, thereby forming the spacer 213.
In some embodiments, the gate body 212 may comprise a semiconductor material, such as, but not limited to, polysilicon. The spacers 213 may comprise a single layer or a multi-layer structure, and the material may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or a combination thereof, but is not limited thereto. In some embodiments, the top of the gate body 212 may include a cap layer (e.g., a silicon nitride cap layer, not shown).
An interlayer dielectric layer 230 is disposed on the substrate 202 and covers the isolation structures 208, the island-shaped structures 206, and the active regions 210 in the regions a and B. After the gate structure RS1 and the gate structure G are completed, an interlayer dielectric layer 230 may be formed on the substrate 202 by chemical vapor deposition or other suitable manufacturing process. The interlayer dielectric layer 230 may comprise a dielectric material, which may comprise, for example, silicon oxide (SiO)2) For example, but not limited to, Undoped Silicon Glass (USG), or low dielectric constant (low-k) dielectric materials such as Fluorinated Silicon Glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, or organic polymer dielectric materials. In some embodiments, the layer interfaceThe electrical layer 230 comprises silicon oxide (SiO)2). The ild layer 230 may be subjected to a Chemical Mechanical Polishing (CMP) process to planarize the ild layer 230. As shown in fig. 7A and 7B, the top of the gate body 212 of the gate structure RS1 and the gate structure G can be exposed from the surface of the interlayer dielectric layer 230.
An etch stop layer 232 is disposed on the interlayer dielectric layer 230 and covers the exposed top portions of the gate structures RS1 and G. An etch stop layer 232 may be formed on the planarized interlayer dielectric layer 230 by chemical vapor deposition or other suitable fabrication processes. The etch stop layer 232 may comprise a dielectric material, such as silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN), but is not limited thereto. In some embodiments, the etch stop layer 232 comprises silicon oxide (SiO)2)。
The resistance structure RS2 is located on the etch stop layer 232 and is aligned in a vertical direction (e.g., the third direction D3) with the gate structure RS 1. The resistor structure RS2 may include a resistor layer 234a and a hard mask layer 234b on the resistor layer 234 a. A resistive material layer and a hard mask material layer may be deposited on the etch stop layer 232 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable semiconductor manufacturing process, and then a photolithography and etching process is performed using a resistive pattern photomask including the resistive pattern 112 of fig. 1A, the pattern of the photomask is transferred into the resistive material layer and the hard mask material layer, and the redundant resistive material layer and the hard mask material layer are removed, so as to obtain the resistive layer 234a and the hard mask layer 234b of the resistive structure RS 2.
According to some embodiments of the invention, the material of the resistive layer 234a may include an alloy (alloy) or a metal compound (metal compound), such as a metal silicide, a metal oxide, a metal nitride, or a combination of the foregoing, but is not limited thereto. According to an embodiment of the present invention, the material of the resistive layer 234a includes titanium nitride (TiN). The hard mask layer 234b is preferably selected to have an etching selectivity with respect to the etch stop layer 232. For example, when the etch stop layer 232 comprises silicon oxide, the hard mask layer 234b may comprise silicon nitride.
It is noted that during the fabrication of the semiconductor structure 200a, especially during the Chemical Mechanical Polishing (CMP) process of the isolation structure 208, the top surface of the isolation structure 208 with a large area (or with a too low pattern density) is usually recessed (deforming), so that the height of the gate material layer on the recessed portion is lower than that of the gate material layer in other areas, which affects the depth of focus, and is liable to cause patterning abnormality, resulting in deformation or wire breakage of the gate body 212, or gate material layer residue. In addition, the height of the interlayer dielectric layer 230 on the recess is also lower than the height of the interlayer dielectric layer 230 in other regions, which causes uneven heights of the resistor material layer and the hard mask material layer, and increases the difficulty of patterning the resistor structure RS 2.
The pattern density of the isolation structure 208 is adjusted by forming the island-shaped structures 206 in the isolation structure 208, and the percentage of the total area of the island-shaped structures 206 in a plan view to the area of the isolation structure 208 is preferably more than 0% and less than 50%, so that the polishing uniformity of a Chemical Mechanical Polishing (CMP) manufacturing process can be improved, the situation that the top surface of the isolation structure 208 is recessed is reduced, the problem of uneven heights of a gate material layer, a resistance material layer and a hard mask material layer is further reduced, the patterning manufacturing process of the gate structures RS1 and G and the resistance structure RS2 can have a better patterning result, and the manufacturing process margin of a semiconductor structure is improved.
Please refer to fig. 8A and 8B. FIG. 8A is a cross-sectional view of a region A along a line I-I 'of a semiconductor structure 200B according to another embodiment of the present invention, and FIG. 8B is a cross-sectional view of a region B along a line II-II'. The gate structures RS1 'and G' of the semiconductor structure 200B of fig. 8A and 8B may include metal gates.
The gate structure RS1 'and the gate structure G' can be formed by a replacement metal gate (replacement metal gate) fabrication process. In some embodiments, the replacement metal gate process step includes exposing the top portions of the gate bodies 212 of the gate structures RS1 and G from the surface of the interlayer dielectric layer 230, and then removing the gate bodies 212 by using a selective etching process (e.g., a wet etching process) to form a plurality of gate trenches. Then, a high-k dielectric layer (not shown), a work function metal layer 214, and a low-resistance metal layer 215 are sequentially deposited in the gate trench to fill up the gate trench, and a Chemical Mechanical Polishing (CMP) process is performed to remove the excess high-k dielectric layer, the work function metal layer 214, and the low-resistance metal layer 215 outside the gate trench, so as to obtain the gate structure RS1 'of fig. 8A and the gate structure G' of fig. 8B. In some embodiments, the gate structure RS1' and the resistor structure RS2 may be embedded resistors of the semiconductor structure 200a, respectively. In other embodiments, the gate structure RS1' may be an electrically floating dummy structure, not electrically connected to other components.
It is noted that in the replacement metal gate process, if the top surface of the isolation structure 208 is recessed, the height of the gate structure RS1 in the recessed portion is lower than the height of the gate structure in other areas (e.g., the gate structure G), so that the top of the gate body 212 of the gate structure RS1 is not exposed from the interlayer dielectric layer 230 and cannot be removed, thereby causing a metal gate replacement anomaly. In addition, the interlayer dielectric layer 230 on the recess is low, so that the gate metal layer thereon is not easily removed by polishing, resulting in a metal layer residue problem.
The pattern density of the isolation structure 208 is adjusted by forming the island-shaped structure 206 in the isolation structure 208, so that the top surface of the isolation structure 208 is prevented from being recessed, the gate structure RS1 and the gate structure (such as the gate structure G) in other regions have relatively consistent heights, the interlayer dielectric layer 230 has relatively consistent height as a whole, the situation of abnormal metal gate replacement or metal residue can be reduced, and the margin of the manufacturing process of the semiconductor structure is improved.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (20)

1. A semiconductor layout comprising
A base pattern surrounding the isolation region pattern;
a plurality of dummy patterns in the isolation region pattern;
a plurality of gate patterns in the isolation region patterns and passing between the plurality of dummy patterns; and
and a plurality of resistance patterns in the isolation region pattern and overlapping the plurality of gate patterns.
2. The semiconductor layout of claim 1 wherein a percentage of a total area of the plurality of dummy patterns to an area of the isolation region pattern is greater than 0% and less than 50%.
3. The semiconductor layout of claim 1 wherein the plurality of gate patterns extend along a first direction and are arranged in parallel along a second direction.
4. The semiconductor layout of claim 3, wherein the plurality of dummy patterns comprise rectangular shapes and are aligned along the first direction and the second direction.
5. The semiconductor layout of claim 3, wherein the plurality of dummy patterns comprise rectangular shapes and are aligned along the first direction and staggered along the second direction.
6. The semiconductor layout of claim 3, wherein the plurality of dummy patterns extend along the first direction and are staggered from the plurality of gate patterns along the second direction.
7. The semiconductor layout of claim 1 wherein edges of the plurality of gate patterns partially overlap edges of the plurality of dummy patterns.
8. The semiconductor layout of claim 1, wherein the plurality of gate patterns and the plurality of dummy patterns do not overlap at all.
9. The semiconductor layout of claim 1 wherein the plurality of dummy patterns do not overlap at all with edges of the isolation region pattern.
10. The semiconductor layout of claim 1 wherein an extent of the isolation region pattern overlaps an extent of the resistive mark region.
11. A semiconductor structure, comprising:
a substrate including an isolation structure surrounding a plurality of island-like structures;
an interlayer dielectric layer on the substrate;
a plurality of first gate structures in the interlayer dielectric layer and on the isolation structures; and
a plurality of resistor structures located on the interlayer dielectric layer and aligned with the first gate structures.
12. The semiconductor structure of claim 11, wherein said plurality of first gate structures comprise polysilicon and said plurality of resistive structures comprise titanium nitride (TiN).
13. The semiconductor structure of claim 11, wherein said plurality of first gate structures comprise a low-resistance metal and said plurality of resistive structures comprise titanium nitride (TiN).
14. The semiconductor structure of claim 11, wherein said plurality of first gate structures are electrically floating.
15. The semiconductor structure of claim 11, further comprising a second gate structure in said interlayer dielectric layer and on said active region, wherein said second gate structure is flush with said plurality of first gate structures.
16. The semiconductor structure of claim 15, wherein the plurality of first gate structures and the second gate structure comprise polysilicon and the resistive structure comprises titanium nitride (TiN).
17. The semiconductor structure of claim 15, wherein said plurality of first gate structures comprise polysilicon, said second gate structure comprises a low-resistance metal, and said resistive structure comprises titanium nitride (TiN).
18. The semiconductor structure of claim 15, wherein the plurality of first gate structures and the second gate structure comprise a low-resistance metal, the resistive structure comprising titanium nitride (TiN).
19. The semiconductor structure of claim 11, wherein the plurality of first gate structures do not overlap the plurality of island structures.
20. The semiconductor structure of claim 11, further comprising an etch stop layer between said plurality of first gate structures and said resistive structure.
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US20060163665A1 (en) * 2005-01-21 2006-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy patterns in integrated circuit fabrication
US20180211952A1 (en) * 2017-01-26 2018-07-26 Samsung Electronics Co., Ltd. Semiconductor device including resistor structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060163665A1 (en) * 2005-01-21 2006-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy patterns in integrated circuit fabrication
US20180211952A1 (en) * 2017-01-26 2018-07-26 Samsung Electronics Co., Ltd. Semiconductor device including resistor structure

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