CN113611608A

CN113611608A - Preparation method of silicon carbide planar gate MOSFET

Info

Publication number: CN113611608A
Application number: CN202110666132.8A
Authority: CN
Inventors: 杜蕾; 喻双柏; 孙军; 和巍巍; 张振中; 汪之涵
Original assignee: Basic Semiconductor Ltd
Current assignee: Basic Semiconductor Ltd
Priority date: 2021-06-16
Filing date: 2021-06-16
Publication date: 2021-11-05

Abstract

The embodiment of the invention provides a preparation method of a silicon carbide planar gate MOSFET, which comprises the following steps: forming self-aligned JFET regions and well regions in a silicon carbide substrate; forming a self-aligned source region and a channel region in the well region; forming a contact region in the well region; forming a gate dielectric layer and a gate electrode which is self-aligned to the source region, wherein the gate dielectric layer covers the source region, the channel region and the JFET region, and the gate electrode is positioned on the gate dielectric layer; and forming a source electrode and a drain electrode, wherein the source electrode is connected with the source region and the contact region, and the drain electrode is formed on the surface of the silicon carbide substrate, which is far away from the source electrode.

Description

Preparation method of silicon carbide planar gate MOSFET

Technical Field

The invention relates to the technical Field of semiconductors, in particular to a preparation method of a silicon carbide planar gate Metal-Oxide-Semiconductor Field Effect transistor (MOSFET).

Background

Silicon Carbide (SiC) material is an excellent material for preparing core power devices in the power electronic field due to its forbidden bandwidth three times that of Silicon, high critical breakdown electric field, high thermal conductivity and carrier saturation drift velocity. In a power device family, the MOSFET is used as a full-control power metal oxide field effect transistor and has the characteristics of high switching speed, high input impedance, relatively simple driving and the like. However, compared with the silicon-based MOSFET, the silicon carbide MOSFET has a lower channel mobility and a higher channel resistance Rch due to the poor channel interface state. The most direct way to reduce the channel resistance Rch is to shorten the channel length, but the manufacture of the short channel MOSFET has higher requirements on the precision of the alignment and etching. The on-resistance Ron of a MOSFET is defined as the total resistance that results from current flowing from the drain to the source when the device is on in the forward direction. For the planar gate MOSFET on-resistance Ron, it at least includes a source region resistance Rn +, a channel resistance Rch, a Junction FET (JFET) region resistance RJFET. In the traditional process, Rn +, Rch and RJFET are all related to photoetching alignment accuracy. In the traditional process, a JFET area, a well area, a channel area, a source area and a polysilicon grid electrode alignment area are all manufactured through photoetching, in order to achieve the stability of the process, an alignment allowance of 0.5-1.0 mu m is reserved in the areas, the allowance can increase the size of a corresponding area, and further the resistance of the corresponding area can be passively increased.

In the fabrication of a silicon-based planar gate MOSFET, also called a Vertical Double-diffused MOSFET (VDMOSFET), a polysilicon gate is commonly used as an ion implantation mask for a well region (e.g., PW) and an N + type source region, and the diffusion time and diffusion temperature after ion implantation are changed to control the ion diffusion range after implantation, thereby controlling the width of a channel, and the polysilicon gate is retained to be used as a gate of the VDMOSFET, which is generally called a self-aligned process. However, the ion diffusion coefficient in silicon carbide is very low, and no diffused junction exists, so that the silicon-based self-aligned process is not suitable for manufacturing silicon carbide MOSFETs.

Therefore, in view of the unique properties of silicon carbide materials, it is necessary to develop a preparation method suitable for manufacturing silicon carbide MOSFETs to reduce the on-resistance thereof.

Disclosure of Invention

The embodiment of the invention provides a preparation method of a silicon carbide planar gate MOSFET, which comprises the following steps:

forming self-aligned JFET regions and well regions in a silicon carbide substrate;

forming a self-aligned source region and a channel region in the well region;

forming a contact region in the well region;

forming a gate dielectric layer and a gate electrode which is self-aligned to the source region, wherein the gate dielectric layer covers the source region, the channel region and the JFET region, and the gate electrode is positioned on the gate dielectric layer; and

and forming a source electrode and a drain electrode, wherein the source electrode is connected with the source region and the contact region, and the drain electrode is formed on the surface of the silicon carbide substrate, which is far away from the source electrode.

The preparation method of the silicon carbide planar gate MOSFET can realize that the overlay areas of the JFET area, the channel area, the source area and the grid electrode are formed in a self-alignment mode, and no overlay allowance is required to be reserved, so that the optimized physical sizes of the JFET area, the channel area and the source area are realized, the source area resistance Rn +, the channel resistance Rch and the JFET area resistance RJFET are reduced, and the purpose of reducing the on-resistance Ron of the whole silicon carbide MOSFET is further realized.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a silicon carbide planar gate MOSFET according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of the JFET region formed in a silicon carbide substrate in the method of manufacturing shown in fig. 1.

Fig. 3 is a schematic diagram of a first polysilicon layer formed in the structure shown in fig. 2.

Fig. 4 is a schematic view of the structure shown in fig. 3 after planarization.

Fig. 5 is a schematic diagram of the structure shown in fig. 4, which is implanted with ions to form a well region.

Fig. 6 is a schematic diagram of the structure shown in fig. 5, with a silicon dioxide layer and a second polysilicon layer formed.

Fig. 7 is a schematic diagram of etching the second polysilicon layer in fig. 6 to form a sidewall.

Fig. 8 is a schematic view of the structure shown in fig. 7, which is implanted with ions to form a source region and a channel region.

Fig. 9 is a schematic view of the structure shown in fig. 8, which is subjected to ion implantation to form a contact region.

Fig. 10 is a schematic diagram of forming a shielding layer in the structure shown in fig. 9.

Fig. 11 is a schematic view of the structure shown in fig. 10 after planarization processing.

Fig. 12 is a schematic view of the structure shown in fig. 11 after a thermal oxidation process.

Fig. 13 is a schematic view of the silicon dioxide of fig. 12 after wet etching.

Fig. 14 is a schematic view of the structure shown in fig. 13 after a third polysilicon layer is formed and is subjected to a thermal oxidation process.

Fig. 15 is a schematic view of the structure shown in fig. 14 after planarization processing.

Fig. 16 is a schematic diagram of removing the shielding layer in fig. 15 to obtain a gate dielectric layer and a gate electrode.

Fig. 17 is a schematic view of the structure of fig. 16 with source and drain regions formed to obtain a silicon carbide planar gate MOSFET.

Description of the main elements

Silicon carbide planar gate MOSFET 100

Silicon carbide substrate 10

Silicon carbide substrate 11

Epitaxial layer 12

JFET region 122

Well region 124

Source region 1242

Channel region 1244

Contact area 1246

Side wall 13

Gate dielectric layer 14

Grid 15

Interlayer dielectric layer 16

Through hole 162

Source electrode 17

Drain electrode 18

JFET region mask layer 21

First polysilicon layer 22

Silicon dioxide layer 23

Second polysilicon layer 24

A photoresist layer 25

Shielding layer 26

Third polysilicon layer 27

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.

Fig. 1 is a schematic flow chart of a method for manufacturing a silicon carbide planar gate MOSFET according to an embodiment of the present invention. As shown in fig. 1, the method for manufacturing the silicon carbide planar gate MOSFET includes the following steps.

Step S1: self-aligned JFET and well regions are formed in a silicon carbide substrate.

Step S2: and forming a self-aligned source region and a channel region in the well region.

Step S3: and forming a contact region in the well region.

Step S4: and forming a gate dielectric layer and a gate self-aligned to the source region.

Step S5: and forming a source electrode and a drain electrode.

Specifically, the silicon carbide substrate is heavily doped with a first doping type. The JFET region is lightly doped with a first doping type. The well region is lightly doped with a second doping type. The source region is heavily doped with the first doping type. The contact region is heavily doped with the second doping type. In one embodiment, the first doping type is N-type, and the second doping type is P-type. In another embodiment, the first doping type is P-type and the second doping type is N-type. The following will specifically describe the method for manufacturing the silicon carbide planar gate MOSFET by taking the first doping type as an N-type and the second doping type as a P-type as an example, with reference to fig. 2 to 17.

As shown in fig. 2, a JFET region mask layer 21 is formed on a silicon carbide Substrate (SiC)10, and the silicon carbide substrate 10 is ion-implanted to form a JFET region 122.

In one embodiment, silicon carbide substrate 10 includes a silicon carbide substrate 11 (shown in fig. 17) and an epitaxial layer 12 (shown in fig. 17) formed on silicon carbide substrate 11. The silicon carbide substrate 10 is heavily N-doped (N +) and the epitaxial layer 12 is lightly N-doped (N-).

In one embodiment, the material of the JFET region mask layer 21 is silicon dioxide (SiO)₂). The step of forming the JFET region mask layer 21 includes depositing silicon dioxide (e.g., 1.0 μm thick) on the silicon carbide substrate 10 and then performing a patterned transfer of the JFET region 122 through photolithography and etching processing steps. That is, the deposited silicon dioxide is patterned to remove portions of the silicon carbide substrate 10 where JFET regions 122 are to be formed. Then, N-type impurities such as nitrogen or phosphorus are implanted into the area of the silicon carbide substrate 10 not covered by the JFET region mask layer 21 to form a JFET region 122.

As shown in fig. 3, a first polysilicon layer (Poly)22 is formed on the surface of the JFET region 122 and the JFET region mask layer 21. The portion of the first polysilicon layer 22 above the JFET region 122 is recessed toward the silicon carbide substrate 10 compared to the portion of the first polysilicon layer above the JFET region mask layer 21.

In one embodiment, the polysilicon layer may be formed by a thin film deposition technique such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., and has a thickness of 1.3 μm, for example.

As shown in fig. 4, the JFET region mask layer 21 and the first polysilicon layer 22 are planarized to make the surface thereof away from the silicon carbide substrate 10 flush.

In one embodiment, the structure shown in fig. 3 may be polished by a Chemical Mechanical Polishing (CMP) process to planarize the surface of the JFET region mask layer 21 and the first polysilicon layer 22 away from the silicon carbide substrate 10. The surface of the JFET region mask layer 21 is slightly polished away, and after polishing, the thickness of the JFET region mask layer 21 is approximately equal to the thickness of the first polysilicon layer 22, and is about 0.75 μm.

As shown in fig. 5, the JFET region mask layer 21 is removed, and the silicon carbide substrate 10 is ion implanted with the first polysilicon layer 22 as a mask layer for ion implantation of the well region 124 to form a P-type well region (PW) 124.

In an embodiment, the JFET region mask layer 21 is silicon dioxide, and the silicon dioxide is wet-etched by using a Buffered Oxide Etch (BOE) solution to remove the JFET region mask layer 21. The BOE etching solution has a low etching rate to the polysilicon, so that the pattern of the first polysilicon layer 22 is retained, and then PW implantation is performed using the retained first polysilicon layer 22 as a self-aligned mask layer for implantation in the well region 124.

In an embodiment, step S2 includes forming a sidewall spacer covering the sidewall of the first polysilicon layer; and performing ion implantation on the well region by taking the side wall as a mask layer for the ion implantation of the source region to form the source region and the channel region.

Step S2 is described below with reference to fig. 6 to 8.

As shown in fig. 6, a silicon dioxide layer 23 and a second polysilicon layer 24 are sequentially formed on the well region 124 and the first polysilicon layer 22 to prepare for the subsequent sidewall spacers 13.

The silicon dioxide layer 23 is, for example, 0.1 μm thick and the second polysilicon layer 24 is, for example, 0.4 μm thick. The silicon dioxide layer 23 covers the well region 124 and the surface of the first polysilicon layer 22, and the second polysilicon layer 24 covers the surface of the silicon dioxide layer 23.

As shown in fig. 7, the second polysilicon layer 24 is etched by using the silicon dioxide layer 23 as an etch stop layer to form the sidewall 13, and the sidewall 13 includes the second polysilicon layer 24 and the silicon dioxide layer 23.

Specifically, the second polysilicon layer 24 is etched by a dry etching method, an end point detection method is used to generate an etching stop signal, and the etched profile is as shown in fig. 7, so as to form a 0.5 μm-wide sidewall (also called spacer)13 composed of a silicon dioxide layer 23 and the + second polysilicon layer 24. This way, compared to other sidewall spacers formed by a single dielectric, the silicon carbide substrate 10 is protected. Since the etching of the sidewall 13 can be stopped when the thin silicon dioxide layer 23 is etched, the silicon carbide substrate 10 is not damaged. And the side wall formed by other single media is etched by taking the silicon carbide substrate as an etching stop, and the dry etching gas can damage the silicon carbide substrate to form more interface traps.

As shown in fig. 8, the sidewall 13 is used as a mask layer for ion implantation of the source region 1242, and ion implantation is performed on the well region 124 to form an N + source region 1242 and a channel region 1244.

Specifically, the implantation of the N + source region 1242 is performed directly through the sidewall 13 without a mask layer of the N + source region 1242. The source regions 1242 formed in this way may be left-right symmetric on the MOSFET structure. The region of the PW well region 124 that includes the N + source region 1242 is blocked by the composite sidewall 13 structure formed by silicon dioxide + Poly and is not implanted with N +, which is equivalent to forming the N + source region 1242 by self-alignment, and the size of the region of the PW well region 124 that includes the source region 1242 is the channel length Lch of the MOSFET. Compared with the structure of the traditional sidewall-free process, the channel length Lch of the structure is determined by the size of the composite sidewall formed by silicon dioxide and Poly, and the minimum Lch required by theory can be directly designed without considering the registration deviation between the PW well region and the N + source region. In one embodiment, the target Lch size is 0.5 μm.

Step S3: and forming a contact region in the well region.

As shown in fig. 9, a portion of the source region 1242 and the silicon dioxide layer 23 are removed to expose the well region 124; and performing ion implantation on the exposed portion of the well 124 to form a P + contact region 1246.

Specifically, a Photoresist layer (Photoresist)25 is formed on the basis of the structure shown in fig. 8. In fig. 9, the regions of the source regions 1242 and the silicon dioxide layer 23 not covered by the photoresist layer 25 are etched away. Then, ion implantation is performed on the exposed portion of the well region 124. The implantation conditions may be 50-200 Kev energy and 1E 14-1E 16 dose to implant boron ions to form P + contact 1246.

Step S3 is described below with reference to fig. 10 to 16.

As shown in fig. 10, a shield layer 26 is formed covering the contact region 1246, the silicon dioxide layer 23 and the second polysilicon layer 24, wherein the lowest position of the shield layer 26 away from the surface of the silicon carbide substrate 10 exceeds the highest position of the first polysilicon layer 22 away from the surface of the silicon carbide substrate 10.

Specifically, the photoresist layer 25 shown in fig. 9 is removed, and then a mask layer 26 is deposited. Wherein the material of the shielding layer 26 is, for example, SiN, and the thickness is, for example, 1.0 μm, so that the lowest point of the shielding layer 26 is higher than the highest point of the first polysilicon layer 22, thereby facilitating the subsequent processing.

As shown in fig. 11, the planarization process is performed to make the surfaces of the mask layer 26, the second polysilicon layer 24, the silicon dioxide layer 23, and the first polysilicon layer 22, which are far from the silicon carbide substrate 10, flush.

Specifically, the planarization process may be performed using CMP. The thickness of the processed first polysilicon layer 22 is about 0.6 μm.

As shown in fig. 12, a thermal oxidation process is performed to oxidize the second polysilicon layer 24 and the first polysilicon layer 22 into silicon dioxide.

Specifically, the thermal oxidation treatment is performed under the conditions that the temperature is 900 ℃ to 1100 ℃, and oxygen or water vapor is introduced into the second polysilicon layer 24 and the first polysilicon layer 22 to oxidize the second polysilicon layer and the first polysilicon layer into silicon dioxide, so as to obtain the structure shown in fig. 12.

As shown in fig. 13, the mask layer 26 is used as a mask to perform a wet etching process on the silicon dioxide to expose the JFET region 122 and the channel region 1244.

Specifically, in the BOE mixed solution, wet etching of silicon dioxide is performed to expose the JFET region 122 and the channel region 1244 of the silicon carbide substrate 10, and at this time, only the SiN shield layer and a small amount of silicon dioxide are present on the silicon carbide substrate 10, and no polysilicon (Poly) is present, so that the high-temperature activation process can be performed.

As shown in fig. 14, a thermal oxidation process is performed on the exposed surfaces of the JFET region 122 and the channel region 1244 to form the gate dielectric layer 14. Then, a third polysilicon layer 27 is formed on the surface of the shielding layer 26 and the surface of the gate dielectric layer 14. Wherein the lowest position of the third polysilicon layer 27 away from the surface of the silicon carbide substrate 10 exceeds the highest position of the shield layer 26 away from the surface of the silicon carbide substrate 10.

Specifically, in the structure shown in fig. 13, the high-temperature gate oxidation is continued, and the gate oxidation thickness may have different thicknesses, such as 0.02 μm to 0.2 μm, according to different product requirements. The conditions for the gate oxidation may be oxidized in a nitrogen containing atmosphere such as NO or N2O. The thickness of the third polysilicon layer 27 may be 0.65 μm so that the lowest position of the third polysilicon layer 27 is higher than the upper portion of the SiN shield layer 26, as shown in fig. 14.

As shown in fig. 15, the planarization process is performed to make the surfaces of the shield layer 26 and the third polysilicon layer 27 away from the silicon carbide substrate 10 flush.

Specifically, the planarization process may be performed using CMP. The composite dielectric layer with the total thickness of 0.5 μm is obtained after the treatment, wherein the thickness of the gate oxide silicon dioxide is about 0.1 μm, and the thickness of the third polysilicon layer 27 is about 0.4 μm.

As shown in fig. 15 and 16, the shield layer 26 is removed, resulting in the gate electrode 15.

The gate 15 comprises a third polysilicon layer 27 in fig. 15. The gate dielectric layer 14 covers the source region 1242, the channel region 1244 and the JFET region 122, and the gate 15 is located on the gate dielectric layer 14.

Specifically, the shielding layer 26 on the surface can be removed by hot phosphoric acid treatment at 70 ℃, and the target structure of fig. 16 is obtained. The physical relative sizes of the source region 1242 and the gate 15 are formed by self-alignment in the previous step, and the source region 1242 and the gate 15 may not need additional overlay (overlay), so that a smaller length of the source region 1242 may be obtained, and the resistance value of the source region 1242 may be reduced.

Step S5: and forming a source electrode and a drain electrode.

As shown in fig. 17, source 17 is in contact with and connected to source regions 1242 and contact regions 1246 through via 162. The drain 18 is formed on the surface of the silicon carbide substrate 10 facing away from the source 17.

Step S5 includes, for example, interlayer dielectric (ILD) deposition, contact lithography/etching, and metallization steps.

Specifically, forming the source 17 may include forming an interlayer dielectric layer 16 overlying the contact region 1246, the gate dielectric layer 14, and the gate 15; forming a via 162 exposing the source region 1242 and the contact region 1246 on the interlayer dielectric layer 16; and forming a metal layer in the via 162 and on the interlayer dielectric layer 16. Finally, the silicon carbide-based planar gate MOSFET structure shown in fig. 17 is formed. The JFET region 122, the channel region 1244, and the N + source region 1242 are all formed by a self-aligned process, so that the optimal on-resistance Ron can be obtained by directly adopting an optimal size design without considering the alignment precision of photolithography.

As shown in fig. 17, the on-resistance Ron of the planar gate MOSFET is generally expressed by the formula: ron ═ Rcs + Rn + + Rch + Ra + rjjfet + Rd + Rsub + Rcd. In the formula, Rcs is a source metal-semiconductor contact resistor, Rn + is an N + source Region resistor, Rch is an inversion layer channel resistor, Ra is a JFET Region accumulation layer resistor below a gate oxide, RJFET is a JFET Region resistor, Rd is a Drift Region (Drift Region) resistor, Rsub is a substrate resistor, and Rcd is a drain metal-semiconductor contact resistor. Wherein, Rcs, Rd, Rsub and Rcd are all related to the requirements of material contact work function or voltage-resistant grade. The Rn +, Rch, Ra and RJFET are related to the requirements of device parameters and the photoetching alignment precision in the traditional process, because the JFET region, the PW region, the channel region, the N + and the polysilicon (Poly) grid alignment region in the traditional process are all manufactured in a photoetching mode, and for the stability of the process, the alignment allowance of 0.5-1.0 mu m is reserved in the regions, and the allowance can increase the size of the corresponding region, so that the resistance of the corresponding region can be passively increased.

According to the preparation method of the silicon carbide-based planar gate MOSFET, disclosed by the embodiment of the invention, the manufacturing process of the silicon carbide-based planar gate MOSFET is redesigned by utilizing a Chemical Mechanical Polishing (CMP) process, so that a full-process self-alignment process comprising junction region self-alignment, channel region self-alignment and N + source region self-alignment can be realized, the side wall structure is optimized, the silicon carbide substrate is prevented from being etched and damaged during dry etching, and the surface defects of a device are reduced. The Rn +, the Rch and the Rjfet resistances are reduced, and the purpose of reducing the whole silicon carbide MOSFET on-resistance Ron is finally achieved.

Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.

Claims

1. A preparation method of a silicon carbide planar gate MOSFET is characterized by comprising the following steps:

forming a self-aligned source region and a channel region in the well region;

forming a contact region in the well region;

2. The method of claim 1, wherein forming the self-aligned JFET and well regions in the silicon carbide substrate comprises:

forming a JFET area mask layer on the silicon carbide substrate, and performing ion implantation on the silicon carbide substrate to form the JFET area;

forming a first polycrystalline silicon layer on the surface of the JFET area and the surface of the JFET area mask layer;

flattening treatment is carried out, so that the JFET area mask layer and the surface, far away from the silicon carbide substrate, of the first polycrystalline silicon layer are flush;

and removing the mask layer of the JFET area, taking the first polycrystalline silicon layer as a mask layer for ion implantation of the well region, and performing ion implantation on the silicon carbide substrate to form the well region.

3. The method of claim 2, wherein the JFET region mask layer is made of silicon dioxide, and the step of removing the JFET region mask layer is wet etching the JFET region mask layer.

4. The method of claim 2, wherein forming the self-aligned source region and the channel region in the well region comprises:

forming a side wall covering the side wall of the first polycrystalline silicon layer; and

and performing ion implantation on the well region by taking the side wall as a mask layer of the ion implantation of the source region to form the source region and the channel region.

5. The method of manufacturing a silicon carbide planar gate MOSFET of claim 4, wherein forming the sidewall spacers comprises:

sequentially forming a silicon dioxide layer and a second polysilicon layer on the well region and the first polysilicon layer; and etching the second polysilicon layer by taking the silicon dioxide layer as an etching stop layer to form the side wall, wherein the side wall comprises the second polysilicon layer and the silicon dioxide layer.

6. The method of fabricating a silicon carbide planar gate MOSFET of claim 5 wherein forming the contact region comprises:

removing part of the source region and the silicon dioxide layer to expose the well region; and

and performing ion implantation on the exposed part of the well region to form the contact region.

7. The method of claim 6, wherein forming the gate dielectric layer and the gate electrode comprises:

forming a shielding layer covering the contact region, the silicon dioxide layer and the second polysilicon layer, wherein the lowest position of the shielding layer away from the surface of the silicon carbide substrate exceeds the highest position of the first polysilicon layer away from the surface of the silicon carbide substrate;

flattening treatment is carried out so that the surfaces of the shielding layer, the second polycrystalline silicon layer, the silicon dioxide layer and the first polycrystalline silicon layer far away from the silicon carbide substrate are flush;

performing thermal oxidation treatment to oxidize the second polysilicon layer and the first polysilicon layer into silicon dioxide;

taking the shielding layer as a mask, and carrying out wet etching on the silicon dioxide to expose the JFET area and the channel area;

performing thermal oxidation treatment on the exposed surfaces of the JFET region and the channel region to form the gate dielectric layer, and forming a third polycrystalline silicon layer on the surface of the shielding layer and the surface of the gate dielectric layer, wherein the lowest position of the third polycrystalline silicon layer far away from the surface of the silicon carbide substrate exceeds the highest position of the shielding layer far away from the surface of the silicon carbide substrate;

flattening treatment is carried out, so that the surfaces of the shielding layer and the third polycrystalline silicon layer far away from the silicon carbide substrate are flush;

and removing the shielding layer to obtain the grid electrode, wherein the grid dielectric layer comprises the silicon dioxide layer, and the grid electrode comprises the third polycrystalline silicon layer.

8. The method of fabricating a silicon carbide planar gate MOSFET of claim 7 wherein forming the source comprises:

forming an interlayer dielectric layer covering the contact region, the gate dielectric layer and the gate;

forming a through hole exposing the source region and the contact region on the interlayer dielectric layer; and

and forming a metal layer in the through hole and on the interlayer dielectric layer to obtain the source electrode.

9. The method of manufacturing a silicon carbide planar gate MOSFET as claimed in any one of claims 1 to 8,

the silicon carbide substrate is heavily doped with a first doping type;

the JFET region is lightly doped with a first doping type;

the well region is lightly doped with a second doping type;

the source region is heavily doped with a first doping type;

the contact region is heavily doped with the second doping type.

10. The method of claim 9, wherein the first doping type is N-type and the second doping type is P-type; or, the first doping type is P-type, and the second doping type is N-type.