CN113594249A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN113594249A
CN113594249A CN202010368145.2A CN202010368145A CN113594249A CN 113594249 A CN113594249 A CN 113594249A CN 202010368145 A CN202010368145 A CN 202010368145A CN 113594249 A CN113594249 A CN 113594249A
Authority
CN
China
Prior art keywords
region
drift region
drift
dielectric layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010368145.2A
Other languages
Chinese (zh)
Other versions
CN113594249B (en
Inventor
蔡巧明
张云香
金美晨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010368145.2A priority Critical patent/CN113594249B/en
Publication of CN113594249A publication Critical patent/CN113594249A/en
Application granted granted Critical
Publication of CN113594249B publication Critical patent/CN113594249B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: the substrate is positioned in the well region in the substrate; the first drift region, the second drift region and the third drift region are positioned in the well region, the third drift region comprises an annular region and a bridging region, the annular region surrounds the first drift region and the second drift region, and the bridging region extends inwards from the annular region to the channel region; the gate structure is positioned on the substrate, crosses the first drift region and the second drift region, and comprises a gate dielectric layer, a gate electrode positioned on the gate dielectric layer and side walls positioned on the two sides of the gate dielectric layer and the gate electrode; and a source region and a drain region respectively located in the first drift region and the second drift region at two sides of the gate structure, wherein the channel region is located between the source region and the drain region and below the gate dielectric layer. The semiconductor structure and the forming method thereof improve the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Lateral Diffusion Metal Oxide Semiconductor (LDMOS) devices are widely used because they have significant advantages in terms of gain, linearity, and heat dissipation performance, and are compatible with Complementary Metal Oxide Semiconductor (CMOS) processes. For LDMOS devices with higher operating voltages (e.g., 32V), the thickness of the gate dielectric layer grown over the channel region is not uniform due to the manufacturing process. Particularly, the gate dielectric layer is thinner at the edge, which causes the edge of the channel region of the LDMOS device to be turned on in advance when the edge of the channel region does not reach the threshold voltage, thereby causing unnecessary current loss (Leakage) and further increasing the power consumption of the LDMOS device.
Accordingly, there is a need for improved LDMOS devices and methods of forming the same to improve their performance.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present application to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.
One aspect of the present application provides a semiconductor structure, comprising: a substrate; a well region located in the substrate; a first drift region, a second drift region, and a third drift region in the well region, the third drift region including a ring region surrounding the first drift region and the second drift region, and a bridge region extending inward from the ring region to a channel region; the grid structure is positioned on the substrate, spans the first drift region and the second drift region, and comprises a grid dielectric layer, a grid electrode positioned on the grid dielectric layer and side walls positioned on the grid dielectric layer and two sides of the grid electrode; and a source region and a drain region respectively located in the first drift region and the second drift region at two sides of the gate structure, wherein the channel region is located between the source region and the drain region and below the gate dielectric layer.
Optionally, the well region and the third drift region have a first conductivity type, the first drift region and the second drift region have a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
Optionally, the length of the source region and the length of the drain region are equal to the width of the channel region.
Optionally, the bridge regions extend from two opposing inner edges of the annular region to two opposing side edges of the channel region, respectively.
Optionally, the width of the bridging region is 0.1 μm to 0.8 μm.
Optionally, the doping concentration of the third drift region is 1012cm-3To 1014cm-3And the depth of the third drift region is 0.05 μm to 0.8 μm.
Another aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a substrate, and forming a well region in the substrate; forming a first drift region, a second drift region and a third drift region in the well region, the third drift region including a ring region surrounding the first drift region and the second drift region and a bridge region extending inwardly from the ring region to a channel region; forming a gate structure on the substrate, wherein the gate structure crosses over the first drift region and the second drift region and comprises a gate dielectric layer, a gate electrode positioned on the gate dielectric layer and side walls positioned on two sides of the gate dielectric layer and the gate electrode; and forming a source region and a drain region in the first drift region and the second drift region on two sides of the gate structure respectively, wherein the channel region is positioned between the source region and the drain region and below the gate dielectric layer.
Optionally, the annular region and the bridge region are formed in the same process.
Optionally, the bridge regions extend from two opposing inner edges of the annular region to two opposing side edges of the channel region, respectively.
Optionally, the width of the bridging region is 0.1 μm to 0.8 μm.
The technical scheme of this application has following beneficial effect:
the bridging region which extends inwards from the annular region to the channel region is arranged in the third drift region, so that the doping concentration at the edge of the channel region is higher than that of the well region, inversion is more difficult, namely, the threshold voltage at the position is improved, the reduction of the threshold voltage caused by the thinning of the gate dielectric layer above the channel region at the position is compensated, the device is effectively prevented from being started in advance, electric leakage of the device in an unopened state is avoided, and the power consumption of the device is reduced.
Secondly, since the bridge region is a part of the third drift region, that is, both can be formed in the same process, no additional process flow is added in the technical scheme of the present application.
Furthermore, since the length of the source region and the length of the drain region are equal to the width of the channel region, the technical solution of the present application can ensure the saturation current (I) of the channel regiondsat) Is maximized.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1A is a schematic plan view (top view) of a semiconductor structure;
FIG. 1B is a cross-sectional view taken along line AA' of FIG. 1A;
FIG. 2A is a schematic plan view (top view) of another semiconductor structure;
FIG. 2B is a cross-sectional view taken along line BB' of FIG. 2A;
FIG. 3 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present application;
FIG. 4A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 4B is a cross-sectional view taken along line CC' of FIG. 4A;
FIG. 5A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 5B is a cross-sectional view taken along line CC' of FIG. 5A;
FIG. 6A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 6B is a cross-sectional view taken along line CC' of FIG. 6A;
FIG. 7A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 7B is a cross-sectional view taken along line CC' of FIG. 7A;
FIG. 7C is a cross-sectional view taken along line DD' of FIG. 7A;
FIG. 8A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 8B is a cross-sectional view taken along line CC' of FIG. 8A;
FIG. 8C is a cross-sectional view taken along line DD' of FIG. 8A;
fig. 9A is a schematic plan view (top view) of a semiconductor structure according to an embodiment of the present application;
FIG. 9B is a cross-sectional view taken along line CC' of FIG. 9A;
fig. 9C is a sectional view taken along line DD' of fig. 9A.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.
As shown in fig. 1A and 1B, a semiconductor structure includes: a substrate 110; a well region 120 located in the substrate 110; a first drift region 141, a second drift region 142 and a third drift region 130 in the well region 120; fourth drift regions 160 located at both sides of the channel region 180; a gate structure 170 on the substrate 120; a source region 151 and a drain region 152 in the first drift region 141 and the second drift region 142 at both sides of the gate structure 170, respectively. More specifically, the gate structure 170 spans the first drift region 141 and the second drift region 142 and includes a gate dielectric layer 171, a gate electrode 172 on the gate dielectric layer 171, and spacers 173 on both sides of the gate dielectric layer 171 and the gate electrode 172. Channel region 180 is located between source region 151 and drain region 152 and below gate dielectric layer 171.
The existence of the fourth drift region 160 having the same doping type as the well region 120 enables the channel region 180 to have a higher doping concentration at the edge, so that inversion is more difficult, thereby compensating for the reduction of threshold voltage caused by the thinning of the gate dielectric layer 171 above the channel region 180 at the edge, effectively preventing the early turn-on of the device, and avoiding electric leakage.
However, the formation of the fourth drift region 160 requires additional processes (e.g., ion implantation) and materials (e.g., masks), which increases manufacturing time and manufacturing costs.
As shown in fig. 2A and 2B, a semiconductor structure includes: a substrate 210; a well region 220 located in the substrate 210; a first drift region 241, a second drift region 242, and a third drift region 230 in the well region 220; a gate structure 270 on the substrate 220; a source region 251 and a drain region 252 in the first drift region 241 and the second drift region 242 on both sides of the gate structure 270, respectively. More specifically, the gate structure 270 spans the first drift region 241 and the second drift region 242 and includes a gate dielectric layer 271, a gate electrode 272 on the gate dielectric layer 271, and side walls 273 on both sides of the gate dielectric layer 271 and the gate electrode 272. The channel region 280 is located between the source region 251 and the drain region 252 and below the gate dielectric layer 271. Both sides of the channel region 280 are in contact with the third drift region 230.
By contacting the third drift region 230 with the channel region 280, after the annealing process, part of the doped ions of the third drift region 230 will diffuse into the channel region 280, so as to improve the doping concentration at the edge of the channel region 280, and make inversion more difficult, thereby compensating for the reduction of the threshold voltage caused by the thinning of the gate dielectric layer 271 above the channel region 280 at the edge, effectively preventing the device from being turned on in advance, and avoiding electric leakage.
However, due to the spacing between the first and second drift regions 241, 242 and the third drift region 230, the length of the channel region 280 in contact with the third drift region 230 is necessarily greater than the length of the source and drain regions 251, 252, which is detrimental to the maximization of the saturation current of the channel region 280, since the magnitude of the saturation current is limited by the shortest length of the source and drain regions 251, 252, 280.
In order to solve the above problem, embodiments of the present application provide a semiconductor structure and a method for forming the same, as shown in fig. 2, the method for forming the semiconductor structure includes the following steps:
step S11: providing a substrate;
step S12: forming a well region in the substrate;
step S13: forming a first drift region, a second drift region and a third drift region in the well region, the third drift region including a ring region surrounding the first drift region and the second drift region and a bridge region extending inwardly from the ring region to a channel region;
step S14: forming a gate structure on the substrate, wherein the gate structure crosses over the first drift region and the second drift region and comprises a gate dielectric layer, a gate electrode positioned on the gate dielectric layer and side walls positioned on two sides of the gate dielectric layer and the gate electrode;
step S15: and forming a source region and a drain region in the first drift region and the second drift region on two sides of the gate structure respectively, wherein the channel region is positioned between the source region and the drain region and below the gate dielectric layer.
The above steps will be described in detail with reference to fig. 4A to 9C. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.
As shown in fig. 4A and 4B, a substrate 310 is provided.
The material of the substrate 310 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other semiconductor materials, such as a III-V compound like gallium arsenide (GaAs). The material of the substrate 100 may be polysilicon. The substrate 310 may also be a silicon-on-insulator structure or a silicon-on-epitaxial layer structure. A first active region 381, a second active region 382, a third active region 383, and a fourth active region 384 are defined in the substrate 100, corresponding to a source region, a drain region, a channel region, and a body region, respectively. In the present embodiment, the first and second active regions 381 and 382 each extend in a first direction (e.g., Y direction), and the third active region 383 extends in a second direction (e.g., X direction), the first direction being perpendicular to the second direction. In the present application, a direction that coincides with the extending direction of a structure or a region may also be referred to as a longitudinal direction, and a direction perpendicular to the extending direction of the structure or the region may also be referred to as a width direction.
As shown in fig. 5A and 5B, a well region 320 is formed in a substrate 310.
Well region 320 may be formed for doping in substrate 310. In this embodiment, the well region 320 may be a P-type well region, which may be formed by P-type doping in the substrate 310. The impurity ions used for P-type doping can be one or more of boron ions, indium ions and gallium ions. In other embodiments, the well region 320 may be an N-type well region, which may be formed by N-type doping in the substrate 310. The N-type impurity ions can be one or more of phosphorus ions, arsenic ions and antimony ions.
As shown in fig. 6A and 6B, a first drift region 341 and a second drift region 342 are formed in the well region 320.
The first drift region 341 may be formed by doping in the well region 320. The doping type of the first drift region 341 is opposite to the doping type of the well region 320. In the present embodiment, the doping type of the first drift region 341 is N type. The doping concentration of the first drift region 341 is higher than that of the well region 320.
The second drift region 342 may be formed for doping in the well region 320. The doping type of the first drift region 341 is opposite to the doping type of the well region 320. In the present embodiment, the doping type of the second drift region 342 is N-type. The second drift region 342 has a doping concentration higher than that of the well region 320.
In subsequent processes, a source region and a drain region may be formed in the first drift region 341 and the second drift region 342, respectively, and the doping concentration of the source region and the drain region may be higher than that of the first drift region 341 and the second drift region 342. The presence of the first drift region 341 and the second drift region 342 can avoid the problem that the doping concentration of the source region and the drain region is too different from that of the well region 320 to generate a strong electric field, thereby affecting the device performance.
As shown in fig. 7A to 7C, a third drift region 330 is formed in the well region 320.
The third drift region 330 may be formed for doping in the well region 320. The doping type of the third drift region 330 is the same as the doping type of the well region 320. In this embodiment, the doping type of the third drift region 330 is P-type, the ion implantation energy of the ion implantation process used in the third drift region is 40KeV to 160 KeV, and the doping concentration of the third drift region is 1012cm-3To 1014cm-3And the depth of the third drift region is 0.05 μm to 0.8 μm. The third drift region 330 may include a ring region 361 and a bridge region 362. An annular region 361 is formed in the fourth active region 384 and surrounds the first and second drift regions 341 and 342. The bridge region 362 extends inward from the annular region 361 to the third active region 383, i.e., the channel region. More specifically, the bridge regions 362 extend from two opposite inner edges of the annular region 361 to two opposite side edges of the third active region 383, respectively. In the present embodiment, the width of the bridge region 363 is 0.1 μm to 0.8 μm, for example, 0.2 μm to 0.6 μm.
As shown in fig. 8A-8C, a gate structure 370 is formed on the substrate 310.
The gate structure 370 spans the first drift region 341 and the second drift region 342 and includes a gate dielectric 371, a gate electrode 372 on the gate dielectric 371, and side walls 373 on both sides of the gate dielectric 371 and the gate electrode 372. Gate dielectric 371 may comprise an oxide of silicon, hafnium oxide, or other high-K material. The gate electrode 372 may include a polysilicon material or a metal material. The sidewall 373 may include silicon oxide or silicon nitride.
As shown in fig. 9A to 9C, a source region 351 and a drain region 361 are formed in the first drift region 341 and the second drift region 342 at both sides of the gate structure 370, respectively.
The source region 351 and the drain region 361 are formed in the first active region 381 and the second active region 382, respectively. The channel region is located between the source region 351 and the drain region 361 and below the gate dielectric 371. In the present embodiment, the doping types of the source region 351 and the drain region 361 are both N-type. The source and drain regions 351 and 361 each extend in the first direction, and the third active region 383 extends in the second direction. In the present embodiment, the length of the source region 351 and the length of the drain region 361 are equal to the width of the third active region 383.
By arranging the bridging region 362 extending from the annular region 361 to the channel region in the third drift region 330, the doping concentration at the edge of the channel region is higher than that of the well region 320, and inversion is more difficult, that is, the threshold voltage at the edge is increased, so that the decrease of the threshold voltage caused by the thinning of the gate dielectric layer 371 above the channel region is compensated, the device is effectively prevented from being turned on in advance, electric leakage of the device in an unopened state is avoided, and the power consumption of the device is improved.
In addition, since the bridge region 362 and the third drift region 330 are formed in the same process, the technical solution of the present application does not result in an additional process flow.
In addition, according to the present invention, the length of the source region 351 and the length of the drain region 361 can be made equal to the width of the channel region, thereby maximizing the saturation current passing through the channel region.
Embodiments of the present application also provide a semiconductor structure, comprising: the substrate 310 is located in the well region 320 of the substrate 310; a first drift region 341, a second drift region 342, and a third drift region 330 in the well region 320, the third drift region 330 including a ring region 361 and a bridge region 362, the ring region 361 surrounding the first drift region 341 and the second drift region 342, the bridge region 362 extending inward from the ring region 361 to the channel region; a gate structure 370 located on the substrate 310, the gate structure 370 spanning the first drift region 341 and the second drift region 342 and including a gate dielectric 371, a gate electrode 372 located on the gate dielectric 371, and side walls 373 located on both sides of the gate dielectric 371 and the gate electrode 372; and a source region 351 and a drain region 361 in the first drift region 341 and the second drift region 342 respectively located at two sides of the gate structure 370, the channel region being located between the source region 351 and the drain region 361 and below the gate dielectric layer 371.
The material of the substrate 310 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other semiconductor materials, such as a III-V compound like gallium arsenide (GaAs). The material of the substrate 100 may be polysilicon. The substrate 100 may also be a silicon-on-insulator structure or a silicon-on-epitaxial layer structure.
Well region 320 may be formed for doping in substrate 310. In this embodiment, the well region 320 may be a P-type well region, which may be formed by P-type doping in the substrate 310. The impurity ions used for P-type doping can be one or more of boron ions, indium ions and gallium ions. Well region 320 may also be an N-type well region, which may be formed by N-type doping in substrate 310. The N-type impurity ions can be one or more of phosphorus ions, arsenic ions and antimony ions.
The first drift region 341 may be formed by doping in the well region 320. The doping type of the first drift region 341 is opposite to the doping type of the well region 320. In the present embodiment, the doping type of the first drift region 341 is N type. The doping concentration of the first drift region 341 is higher than that of the well region 320.
The second drift region 342 may be formed for doping in the well region 320. The doping type of the first drift region 341 is opposite to the doping type of the well region 320. In the present embodiment, the doping type of the second drift region 342 is N-type. The second drift region 342 has a doping concentration higher than that of the well region 320.
The third drift region 330 may be formed for doping in the well region 320. The doping type of the third drift region 330 is the same as the doping type of the well region 320. In the present embodiment, the doping type of the third drift region 330 is P-type.
Gate dielectric 371 may comprise an oxide of silicon, hafnium oxide, or other high-K material.
The gate electrode 372 may include a polysilicon material or a metal material.
The sidewall 373 may include silicon oxide or silicon nitride.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a substrate;
a well region located in the substrate;
a first drift region, a second drift region, and a third drift region in the well region, the third drift region including a ring region surrounding the first drift region and the second drift region, and a bridge region extending inward from the ring region to a channel region;
the grid structure is positioned on the substrate, spans the first drift region and the second drift region, and comprises a grid dielectric layer, a grid electrode positioned on the grid dielectric layer and side walls positioned on the grid dielectric layer and two sides of the grid electrode; and
and the channel region is positioned between the source region and the drain region and below the gate dielectric layer.
2. The semiconductor structure of claim 1, wherein the well region and the third drift region have a first conductivity type, wherein the first drift region and the second drift region have a second conductivity type, and wherein the first conductivity type is opposite the second conductivity type.
3. The semiconductor structure of claim 1, wherein a length of the source region and a length of the drain region are equal to a width of the channel region.
4. The semiconductor structure of claim 1, wherein the bridge regions extend from two opposing inner edges of the ring region to two opposing side edges of the channel region, respectively.
5. The semiconductor structure of claim 1, wherein the bridge region has a width of 0.1 μm to 0.8 μm.
6. The semiconductor structure of claim 1, wherein the third drift region has a doping concentration of 1012cm-3To 1014cm-3And the depth of the third drift region is 0.05 μm to 0.8 μm.
7. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a well region in the substrate;
forming a first drift region, a second drift region and a third drift region in the well region, the third drift region including a ring region surrounding the first drift region and the second drift region and a bridge region extending inwardly from the ring region to a channel region;
forming a gate structure on the substrate, wherein the gate structure crosses over the first drift region and the second drift region and comprises a gate dielectric layer, a gate electrode positioned on the gate dielectric layer and side walls positioned on two sides of the gate dielectric layer and the gate electrode; and
and forming a source region and a drain region in the first drift region and the second drift region on two sides of the gate structure respectively, wherein the channel region is positioned between the source region and the drain region and below the gate dielectric layer.
8. The method of claim 7, wherein the annular region and the bridge region are formed in the same process.
9. The method of claim 7, wherein the bridge regions extend from two opposing inner edges of the annular region to two opposing side edges of the channel region, respectively.
10. The method of claim 7, wherein the width of the bridging region is 0.1 μm to 0.8 μm.
CN202010368145.2A 2020-04-30 2020-04-30 Semiconductor structure and forming method thereof Active CN113594249B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010368145.2A CN113594249B (en) 2020-04-30 2020-04-30 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010368145.2A CN113594249B (en) 2020-04-30 2020-04-30 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN113594249A true CN113594249A (en) 2021-11-02
CN113594249B CN113594249B (en) 2023-07-04

Family

ID=78236925

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010368145.2A Active CN113594249B (en) 2020-04-30 2020-04-30 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN113594249B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115881824A (en) * 2023-02-09 2023-03-31 广州粤芯半导体技术有限公司 MOS transistor
CN118039638A (en) * 2024-04-11 2024-05-14 合肥晶合集成电路股份有限公司 Semiconductor device layout structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097475A (en) * 2009-11-27 2011-06-15 美格纳半导体有限公司 Semiconductor device and method for fabricating semiconductor device
US20120193709A1 (en) * 2011-01-27 2012-08-02 Fujitsu Semiconductor Limited Mos transistor and fabrication method of semiconductor integrated circuit device
CN103681855A (en) * 2012-08-31 2014-03-26 爱思开海力士有限公司 Semiconductor device
CN108695386A (en) * 2017-04-11 2018-10-23 世界先进积体电路股份有限公司 High voltage semiconductor device and its manufacturing method
CN110957349A (en) * 2018-09-27 2020-04-03 世界先进积体电路股份有限公司 Semiconductor device and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097475A (en) * 2009-11-27 2011-06-15 美格纳半导体有限公司 Semiconductor device and method for fabricating semiconductor device
US20120193709A1 (en) * 2011-01-27 2012-08-02 Fujitsu Semiconductor Limited Mos transistor and fabrication method of semiconductor integrated circuit device
CN103681855A (en) * 2012-08-31 2014-03-26 爱思开海力士有限公司 Semiconductor device
CN108695386A (en) * 2017-04-11 2018-10-23 世界先进积体电路股份有限公司 High voltage semiconductor device and its manufacturing method
CN110957349A (en) * 2018-09-27 2020-04-03 世界先进积体电路股份有限公司 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115881824A (en) * 2023-02-09 2023-03-31 广州粤芯半导体技术有限公司 MOS transistor
CN118039638A (en) * 2024-04-11 2024-05-14 合肥晶合集成电路股份有限公司 Semiconductor device layout structure

Also Published As

Publication number Publication date
CN113594249B (en) 2023-07-04

Similar Documents

Publication Publication Date Title
US9780184B2 (en) Electronic device with asymmetric gate strain
US7525150B2 (en) High voltage double diffused drain MOS transistor with medium operation voltage
US9224862B2 (en) High voltage semiconductor device and method for fabricating the same
US9054075B2 (en) Strip-shaped gate tunneling field effect transistor with double-diffusion and a preparation method thereof
KR100840667B1 (en) Lateral dmos device and fabrication method therefor
US20150123199A1 (en) Lateral diffused semiconductor device
US20060033155A1 (en) Method of making and structure for LDMOS transistor
US7709311B1 (en) JFET device with improved off-state leakage current and method of fabrication
JP2005516389A (en) Field effect transistor having a source and / or drain forming a Schottky or Schottky contact using a strained semiconductor substrate
JP2701762B2 (en) Semiconductor device and manufacturing method thereof
US8981421B2 (en) Strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof
JP6175411B2 (en) Semiconductor device
TWI455318B (en) High voltage semiconductor device and method for manufacturing the same
CN117153888B (en) Semiconductor device and method for manufacturing the same
CN113594249B (en) Semiconductor structure and forming method thereof
CN109980010B (en) Method for manufacturing semiconductor device and integrated semiconductor device
TWI798825B (en) Manufacturing method of semiconductor device
KR102456758B1 (en) High voltage semiconductor device and manufacturing method thereof
US20240222455A1 (en) High-voltage transistor, level-up shifting circuit, and semiconductor device
US20230420560A1 (en) Semiconductor device and method for forming the same
US20220140116A1 (en) Junction field effect transistor on silicon-on-insulator substrate
KR20050104163A (en) High voltage transistor and method of fabricating the same
KR100405450B1 (en) Dmos transistor having structure of pocket type junction layer and manufacturing method thereof
JPH09121053A (en) Vertical field-effect transistor and fabrication thereof
CN114242777A (en) LDMOSFET, preparation method, chip and circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant