CN113567761A - CMOS full-integrated electromagnetic detection radio frequency front-end sensor - Google Patents
CMOS full-integrated electromagnetic detection radio frequency front-end sensor Download PDFInfo
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Abstract
The invention discloses a radio frequency front end sensor for CMOS (complementary metal oxide semiconductor) fully-integrated electromagnetic detection, which comprises a Hall sensor, a rotating current circuit, an instrument operational amplifier, a low-pass filter and a clock processing circuit, wherein the rotating current circuit is used for eliminating the electromagnetic induction offset of the Hall sensor; the instrument operational amplifier is used for improving the load capacity of the circuit; the low-pass filter is used for realizing RC low-pass filtering of the circuit; the clock processing circuit is used for outputting high-level non-overlapping waveform clocks and preventing the influence caused by simultaneous conduction of switches in the rotating current circuit. The invention adopts CMOS process, realizes full integration of electromagnetic sensing, can insert the sensor into the channel without influencing the radio frequency performance, does not increase the chip area, saves the cost, and realizes the detection of the electromagnetic intensity between the radio frequency front-end circuits.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a radio frequency front-end sensor for CMOS fully integrated electromagnetic detection.
Background
In radio frequency front-end systems, system stability is a matter of concern for designers. In practical use, inter-channel interference caused by chip signal leakage is an important factor influencing the indexes of the radio frequency system. Leakage of the transmit signal from the power amplifier can interfere with the receive signal, degrading the channel isolation of the rf receiver system. This problem affects the performance of the chip during its use. In the conventional radio frequency chip test, the use of a probe station for needle insertion is too complicated, and the cost is high. The invention mainly aims to solve the problem of complex isolation detection in the traditional radio frequency system, and designs an integrated electromagnetic sensor circuit by utilizing a CMOS (complementary metal oxide semiconductor) process, so that the current detection is converted into the electromagnetic detection, the power consumption and the area can be reduced, and the cost is reduced.
The Bipolar process is adopted to design the integrated circuit, so that the integrated circuit has the advantages of low noise and low offset voltage, but when the offset voltage caused by mismatching of transistors is eliminated, the structure of an external signal processing circuit of the Bipolar sensor is not simple, the area of a chip is increased, the production cost is low, and the Bipolar process usually has a logic function which is difficult to realize. The CMOS process has the advantages of high integration level and low power consumption, so that the functions of the CMOS sensor can be increased, and the integrated circuit design process using the CMOS process is compatible with the market development requirements, but the CMOS process has significant disadvantages, for example, offset voltage and noise of the CMOS hall sensor are relatively serious, and effective hall signals are easily affected by the offset voltage and noise, so that the performance of the hall sensor is seriously affected, and the sensitivity of the hall sensor based on the CMOS process is significantly lower than that of the hall sensor manufactured by the bipolar process, and the sensitivity is an important parameter for measuring the performance of the hall sensor.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a CMOS fully-integrated electromagnetic detection radio-frequency front-end sensor.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a CMOS fully integrated electromagnetic detection radio frequency front end sensor comprises a Hall sensor, a rotating current circuit, an instrument operational amplifier, a low pass filter and a clock processing circuit, wherein,
the rotating current circuit is used for eliminating the electromagnetic induction offset of the Hall sensor;
the instrument operational amplifier is used for improving the load capacity of the circuit;
the low-pass filter is used for realizing RC low-pass filtering of the circuit;
the clock processing circuit is used for outputting high-level non-overlapping waveform clocks and preventing the influence caused by simultaneous conduction of switches in the rotating current circuit.
The scheme has the advantages that the detection of the isolation between the radio frequency channels is converted into the detection of the electromagnetic field strength of the leakage signal, the isolation between the radio frequency channels can be indirectly measured, the high-precision magnetic field detection is realized, and the method is suitable for the radio frequency front-end circuit with strict requirements on power consumption.
Further, the hall sensor is of a four-electrode symmetrical structure and comprises symmetrical electrodes H1 and H3, H2 and H4, and when the hall sensor is in a working state, the symmetrical electrodes H1 and H3, and H2 and H4 which are in symmetrical positions are respectively used as an input end bias electrode and an output end detection electrode.
The beneficial effect of the further scheme is that the four electrodes are symmetrical in height in pairs, so that the device can still keep high symmetry and consistency after the bias electrodes and the detection electrodes are exchanged in pairs, and disorder is reduced.
Further, the rotating current circuit comprises a two-phase rotating current circuit which comprises a first clock complementary signal control switch S1 and a second clock complementary signal control switch S2, and in the working state, when S1 is closed and S2 is opened, current flows from the electrode H1 end of the Hall sensor to the electrode H3 end, and high-frequency voltage signals are output at the electrode H2 end and the electrode H4 end; when S1 is disconnected and S2 is closed, current flows from the end of the electrode H2 to the end of the electrode H4, offset low-frequency voltage signals are output at the end of the electrode H1 and the end of the electrode H3, and the output of the rotating current circuit is divided into two paths which are respectively connected with the input of the operational amplifier of the instrument.
The further scheme has the beneficial effect that the offset of the Hall element is eliminated by utilizing the rotating current circuit.
Further, when S1 is closed and S2 is opened, the control clock period is CLK, and the output induced voltage is represented as:
when S1 is open and S2 is closed, the output induced voltage is expressed as:
wherein, VOFor the output induced voltage, VH1～VH4The induced potential is output from the terminal of electrode H1 to the terminal of electrode H4,
and
voltage output by electrodes containing low frequency offset, Δ R is resistance between diagonal electrodes, VΔRIs a low frequency offset voltage signal, VHThe output induction voltage without offset.
The further proposal has the advantages that the induced voltage is chopped into VHThe period is a periodic signal of the input clock signal, and the offset is a low-frequency signal.
Further, the instrument operational amplifier comprises a pre-amplifier circuit, a demodulator and a unity gain operational amplifier circuit, wherein the output of the rotating current circuit is output to the low-pass filter circuit sequentially through the pre-amplifier circuit, the demodulator and the unity gain operational amplifier circuit.
The further scheme has the advantages that after the signal output by the operational amplifier is amplified by the instrument operational amplifier, the signal is changed into a low-frequency signal through a demodulator between the operational amplifier and the unit gain, and noise, CMOS (complementary metal oxide semiconductor) elements and operational amplifier detuning are modulated to high frequency.
Further, the pre-amplifier circuit comprises a first operational amplifier a1, a second operational amplifier a2, and input feedback resistors R1, R2, and R3, wherein the non-inverting terminal of the first operational amplifier a1 is connected to one input of the rotation selection circuit, and the inverting terminal is connected to the non-inverting terminal of the second operational amplifier a2 through the input feedback resistor R1 and connected to the demodulator through the input feedback resistor R2; the inverting end of the second operational amplifier A2 is connected with the other output of the rotating current circuit, and the non-inverting end is connected with the demodulator through an input feedback resistor R3; the outputs of the first and second operational amplifiers a1 and a2 are both connected to the demodulator.
The beneficial effect of the above further scheme is that a signal with high common mode rejection ratio, low noise and low detuning is provided for the demodulator.
Further, the demodulator includes switches S1B and S2B, and the demodulation operation state is:
when switch S1B is open, the inputs:
Vinp-Vinn＝A(VH-VΔR+VOS)；
the output is:
Voutp-Voutn＝A(VH-VΔR+VOS)＝AVH-A(VΔR-VOS)
when switch S2B is open, the inputs are:
Vinp-Vinn＝A(-VH-VΔR+VOS)；
the output is:
Voutp-Voutn＝A(VH+VΔR-VOS)＝AVH+A(VΔR-VOS)；
where A is the gain of the front-end amplifier of the demodulator, VinnAnd VinpIs the input signal of the demodulator, VoutnAnd VoutpIs the output signal of the demodulator, VHFor output of offset-free induced voltage, VOSIs a noise signal.
The beneficial effect of the above further scheme is that after amplification by a1 and a2, the demodulator modulates the high-frequency signal output by the rotating current circuit into low frequency and simultaneously modulates the detuning into high frequency.
Further, the unity gain amplifier comprises a third operational amplifier a3, output feedback resistors R6, R7, R8 and R9, wherein the input terminals of the third operational amplifier are respectively connected to the output terminals of the demodulator, and the output terminals are output to the low pass filter through a resistor R9.
The beneficial effect of the above further scheme is that the load capacity of the circuit is improved.
Further, the low-pass filter is an RC low-pass filter and includes a resistor R10 and a capacitor C1, wherein one end of the resistor R10 is connected to the output end of the unity gain amplifier, and the other end of the resistor R10 is used as the output end of the radio frequency front end sensor for CMOS fully integrated electromagnetic detection and is grounded through the capacitor C1.
The beneficial effect of the above further scheme is that the output is passed through a low pass filter, and the obtained signal is an induction signal with little offset.
Drawings
Fig. 1 is a schematic structural diagram of a CMOS fully integrated electromagnetic detection rf front end sensor according to the present invention.
FIG. 2 is a schematic diagram of a CMOS fully integrated electromagnetic detection RF front end sensor circuit according to the present invention.
FIG. 3 is a schematic diagram of the CMOS linear Hall sensor device of the present invention.
FIG. 4 is a schematic diagram of a clock processing circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
A CMOS fully integrated electromagnetic detection RF front end sensor, as shown in FIG. 1, comprises a Hall sensor, a rotating current circuit, an instrumentation operational amplifier, a low pass filter and a clock processing circuit, wherein,
the rotating current circuit is used for eliminating the electromagnetic induction offset of the Hall sensor;
the instrument operational amplifier is used for improving the load capacity of the circuit;
the low-pass filter is used for realizing RC low-pass filtering of the circuit;
the clock processing circuit is used for outputting high-level non-overlapping waveform clocks and preventing the influence caused by simultaneous conduction of switches in the rotating current circuit.
The invention aims to detect the isolation of a radio frequency front-end chip, convert the detection of the isolation between radio frequency channels into the detection of the strength of an electromagnetic field of a leakage signal, and indirectly measure the isolation between the radio frequency channels, wherein a linear Hall electromagnetic sensor is adopted for electromagnetic sensing, and a low-noise instrument amplifier is designed as a post-stage processing circuit.
As shown in fig. 3, the hall sensor has a four-electrode symmetrical structure, and includes symmetrical electrodes H1 and H3, H2 and H4, and when in an operating state, the symmetrical electrodes H1 and H3, and H2 and H4 in symmetrical positions are respectively used as an input bias electrode and an output detection electrode.
The four electrodes are symmetrical in height in pairs, so that the device can still keep high symmetry and consistency after the bias electrodes and the detection electrodes are exchanged in pairs, and disorder is reduced. In operation, the H1-H3 electrodes serve as bias electrodes and are input terminals, the H2-H4 electrodes serve as detection electrodes and are output terminals, and the bias electrodes and the H2-H4 electrodes are used for detecting magnetic fields perpendicular to the surface of the device or vice versa. The thickness direction of the active region of the horizontal Hall device is parallel to the direction of the magnetic field, and the Hall voltage formula shows that the Hall voltage and current related sensitivity of the device are improved along with the reduction of the thickness in the direction. Heavily doped N-Well is used as an active region of the device, and highly doped N + is used as four electrodes of the device. A layer of P-type doped region is used for covering the active region of the device, so that flicker noise and surface loss are reduced. Because the CMOS sensor is compatible with the CMOS process, the Hall electromagnetic sensor and the signal conditioning circuit can be integrated on one chip to form a system on chip, so that the area is reduced, and the cost is saved.
As shown in fig. 2, the circuit principle of the present invention is that the rotating current circuit alternately supplies current to the electromagnetic induction device, so that the output signal is also alternately output as a high frequency signal. However, the direct current offset of the device is unrelated to the bias current, so the output offset is a low-frequency signal, after the low-frequency signal is amplified by A1 and A2, the demodulator modulates the high-frequency signal output by the rotating current circuit into low frequency, the offset is modulated into high frequency, A3 is single-bit gain operational amplifier, the load capacity of the circuit is improved, and the A1, A2 and A3 jointly form an instrument amplifier. The output is passed through a low pass filter, and the resulting signal is an induced signal with little detuning, specifically,
the rotating current circuit comprises a two-phase rotating current circuit which comprises a first clock complementary signal control switch S1 and a second clock complementary signal control switch S2, and in the working state, when S1 is closed and S2 is opened, current flows from an electrode H1 end of the Hall sensor to an electrode H3 end, and high-frequency voltage signals are output from an electrode H2 end and an electrode H4 end; when S1 is disconnected and S2 is closed, current flows from the end of the electrode H2 to the end of the electrode H4, offset low-frequency voltage signals are output at the end of the electrode H1 and the end of the electrode H3, and the output of the rotating current circuit is divided into two paths which are respectively connected with the input of the operational amplifier of the instrument.
The two-phase rotating current selected by the invention, S2 and S1 are switches controlled by clock complementary signals, and the control clock is given by figure 4. The operation mode is that when S2 is turned off, the current flows from the end H1 to the end H3 in FIG. 3, and if the device has no offset, the induced voltage V will be output at the ends H2 and H4H：
VH＝VH2-VH4＝0 (5)
However, a certain deviation often exists, and the output is not zero when no magnetic field passes through actually. Assuming that the magnetic field passes vertically inward through the device, S2 is turned off, the potential at the point H2 is greater than that at the point H3526 due to the presence of the resistance Δ R at the ends H2 and H4
When the magnetic field passes through the plane, current flows from H1 to the end H3, and under the action of Lorentz force, induced voltage is generated:
therefore, when S1 is closed, VOIs a VH-VΔRWhen S2 is closed, VOis-VH-VΔR. So that the Hall induced voltage is chopped into a magnitude of VHThe period is a periodic signal of CLK, and the offset is a low-frequency signal.
When S1 is turned off, current flows from the end H2 to the end H4, and an induced potential is generated under the action of a magnetic field:
so V when S2 is openedOIs a VH-VΔRS1 opening time VOis-VH-VΔR. The induced voltage is thus chopped into a magnitude VHThe period is a periodic signal of the input clock signal, and the offset is a low-frequency signal.
The instrument operational amplifier comprises a pre-amplifier circuit, a demodulator and a unit gain operational amplifier circuit, wherein the output of the rotating current circuit is output to the low-pass filter circuit through the pre-amplifier circuit, the demodulator and the unit gain operational amplifier circuit in sequence, specifically,
the pre-stage amplifying circuit comprises a first operational amplifier A1, a second operational amplifier A2 and input feedback resistors R1, R2 and R3, wherein the in-phase end of the first operational amplifier A1 is connected with one input of the rotation selection circuit, and the reverse-phase end of the first operational amplifier A1 is connected with the in-phase end of the second operational amplifier A2 through an input feedback resistor R1 and is connected with the demodulator through an input feedback resistor R2; the inverting end of the second operational amplifier A2 is connected with the other output of the rotating current circuit, and the non-inverting end is connected with the demodulator through an input feedback resistor R3; the outputs of the first and second operational amplifiers a1 and a2 are both connected to the demodulator.
The demodulator comprises switches S1B and S2B, and after the Hall signal output by the operational amplifier is amplified by Av times, the Hall signal is changed into a low-frequency signal by the demodulator as shown in figure 2, and the noise, the Hall element and the operational amplifier are modulated to a high frequency. The working principle is that when the switch S1B is opened, the following are input:
Vinp-Vinn＝A(VH-VΔR+VOS)；
the output is:
Voutp-Voutn＝A(VH-VΔR+VOS)＝AVH-A(VΔR-VOS)
when switch S2B is open, the inputs are:
Vinp-Vinn＝A(-VH-VΔR+VOS)；
the output is:
Voutp-Voutn＝A(VH+VΔR-VOS)＝AVH+A(VΔR-VOS)；
therefore, when the switch S1B and the switch S2B are turned on alternately, the demodulated Hall signal is restored to be a low-frequency signal with the amplitude AVHThe offset of the Hall element and the operational amplifier is chopped into a high-frequency signal related to the clock with amplitude A (V)ΔR-VOS). Where A is the gain of the front-end amplifier of the demodulator, VinnAnd VinpFor the input signal of the demodulator, VoutnAnd VoutpIs the output signal of the demodulator. VHThe output induction voltage without offset. VOSIs a noise signal, wherein the switching control frequency is the same as the rotating current control circuit frequency.
The unity gain amplifier comprises a third operational amplifier A3, an output feedback resistor R6, R7, R8 and R9, wherein the input end of the third operational amplifier is respectively connected to the output end of the demodulator, and the output end of the third operational amplifier is output to the low-pass filter through a resistor R9.
Compared with the current mode and current feedback type instrument operational amplifier, the three operational amplifier structure has the advantages of simpler structure, high common mode rejection ratio and low noise. The structure circuit of the invention aims at CMOS devices, and requires lower noise and offset while requiring high common mode rejection ratio, so the invention adopts a three-operational amplifier structure. The feedback resistance of the output stage operational amplifier is always equal to the input stage feedback resistances R2 and R3 during design, namely the output gain is 1, so the closed loop gain A of the circuitdComprises the following steps:
in this design, R2 and R3 resistances are set equal, usually for simplicity and to allow for matching, so that the gain of the instrument op-amp can be controlled by adjusting R1 and R2 and R3. Under ideal conditions, the input stages are completely matched by the same operational amplifier, and if the operational amplifiers in the graph are all ideal operational amplifiers, the common-mode gain A can be calculatedcComprises the following steps:
as shown in fig. 4, the clock circuit structure of the present invention is schematically illustrated, an internal clock signal is generated by a ring oscillator, and the internal clock signal passes through a non-overlapping clock circuit, and a high-level non-overlapping waveform clock is output by using a delay between gate-level circuits, thereby preventing unnecessary influence caused by simultaneous conduction of switches.
Wherein, as shown in fig. 4, the ring oscillator comprises 5 delay units (inverters), and the output of the last stage is fed back to the input of the first stage to form positive feedback. To achieve sustained oscillation, the oscillation loop must provide a phase shift of 2 π and the loop gain must be greater than 1. The phase shift is divided equally between each delay cell. The oscillation frequency is determined by the propagation delay of the cell and the number of delay stages. The inherent delay of the inverter is determined by designRetardation τpdIn which τ ispIs the average of the low-to-high and high-to-low transition times of the inverter levels of each stage, and haspd＝2×NτpWhere N is the order of the ring oscillator. Then for a 5 th order ring oscillator, the oscillation frequency is given by:
fOSC＝1/τpd＝1/(2×5τp)
the clock buffer has two functions: 1) enhancing the driving capability of the oscillating signal to drive a large capacitive load, 2) generating two-phase non-overlapping clock signals to prevent the switches from being turned on simultaneously. The schematic diagram of the clock buffer is shown in the right half part of fig. 4, an oscillation signal is input into an inverter INV1 and then divided into two paths, one path directly enters a flip-flop composed of a nor gate, and the other path is firstly inverted by an inverter INV12 and then enters a flip-flop circuit. The output enhances the driving capability of the oscillation signal through the buffer. The whole circuit consists of eight logic gates including two nor gates and six inverters, and the working state of the clock buffer is shown in table 1.
TABLE 1
The ring oscillator generates internal clock signals, and outputs high-level non-overlapping waveform clocks by using delay among gate-level circuits through a non-overlapping clock circuit, thereby preventing unnecessary influence caused by simultaneous conduction of switches.
Wherein the ring oscillator adopts a 5-order ring oscillator, and the current flowing through each branch of the ring oscillator
The capacitor is thus discharged (t)PHL) The time is as follows:
when the input is changed from high to low, the NMOS is closed, the PMOS is in a saturation state, and the capacitor is charged. Due to the existence of the tail current mirror, the NMOS discharges by using the same capacitor to charge, and the voltage difference is the same, so the level of each level of inverter is equal from low to high and from high to low: t is tPLH＝tPHLThus, the total propagation delay of the ring oscillator is:
therefore, the output frequency f of the ring oscillatorOSCAs shown in formula (4), the frequency range (KHz to MHz) of the desired output can be realized by only modifying the load capacitor by controlling other variables in the design in relation to the order of the ring oscillator, the power supply voltage, the load capacitor, and the current mirror ratio.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and as described above, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention, and it is to be understood that the scope of the invention is not to be limited to such specific statements and embodiments. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (10)
1. A CMOS fully integrated electromagnetic detection radio frequency front end sensor is characterized by comprising a Hall sensor, a rotating current circuit, an instrument operational amplifier, a low-pass filter and a clock processing circuit, wherein,
the rotating current circuit is used for eliminating the electromagnetic induction offset of the Hall sensor;
the instrument operational amplifier is used for improving the load capacity of the circuit;
the low-pass filter is used for realizing RC low-pass filtering of the circuit;
the clock processing circuit is used for outputting high-level non-overlapping waveform clocks and preventing the influence caused by simultaneous conduction of switches in the rotating current circuit.
2. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 1, wherein the Hall sensor is a four-electrode symmetrical structure, and comprises symmetrical electrodes H1 and H3, H2 and H4, and when in a working state, the symmetrical electrodes H1 and H3, H2 and H4 in the symmetrical positions are respectively used as an input bias electrode and an output detection electrode.
3. The CMOS fully integrated electromagnetic detection radio frequency front end sensor according to claim 2, wherein the rotating current circuit comprises a two-phase rotating current circuit comprising a first clock complementary signal control switch S1 and a second clock complementary signal control switch S2, in an operation state, when S1 is closed and S2 is opened, current flows from an electrode H1 end of the Hall sensor to an electrode H3 end, and high frequency voltage signals are output at an electrode H2 end and an electrode H4 end; when S1 is disconnected and S2 is closed, current flows from the end of the electrode H2 to the end of the electrode H4, offset low-frequency voltage signals are output at the end of the electrode H1 and the end of the electrode H3, and the output of the rotating current circuit is divided into two paths which are respectively connected with the input of the operational amplifier of the instrument.
4. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 3, wherein when S1 is closed and S2 is opened, the control clock period is CLK, and the output induced voltage is represented as:
when S1 is open and S2 is closed, the output induced voltage is expressed as:
wherein, VOFor the output induced voltage, VH1～VH4The induced potential is output from the terminal of electrode H1 to the terminal of electrode H4,
and
voltage output for electrodes including low frequency offset, Δ R is resistance between diagonal electrodes, VΔRIs a low frequency offset voltage signal, VHThe output induction voltage without offset.
5. The CMOS fully integrated electromagnetic detection radio frequency front end sensor according to claim 4, wherein the instrumentation operational amplifier comprises a pre-amplifier circuit, a demodulator and a unity gain operational amplifier circuit, wherein the output of the rotating current circuit is output to the low pass filter circuit sequentially through the pre-amplifier circuit, the demodulator and the unity gain operational amplifier circuit.
6. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 5, wherein said pre-amplifier circuit comprises a first operational amplifier A1, a second operational amplifier A2 and input feedback resistors R1, R2 and R3, wherein the non-inverting terminal of said first operational amplifier A1 is connected to one input of said rotation selection circuit, and the inverting terminal is connected to the non-inverting terminal of said second operational amplifier A2 through an input feedback resistor R1 and to said demodulator through an input feedback resistor R2; the inverting end of the second operational amplifier A2 is connected with the other output of the rotating current circuit, and the non-inverting end is connected with the demodulator through an input feedback resistor R3; the outputs of the first and second operational amplifiers a1 and a2 are both connected to the demodulator.
7. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 6, wherein said demodulator comprises switches S1B and S2B, which demodulate the operating status as:
when switch S1B is open, the inputs:
Vinp-Vinn＝A(VH-VΔR+WOS)；
the output is:
Voutp-Voutn＝A(VH-VΔR+VOS)＝AVH-A(VΔR-VOS)
when switch S2B is open, the inputs are:
Vinp-Vinn＝A(-VH-VΔR+VOS)；
the output is:
Voutp-Voutn＝A(VH+VΔR-VOS)＝AVH+A(VΔR-VOS)；
where A is the gain of the front-end amplifier of the demodulator, VinnAnd VinpIs the input signal of the demodulator, VoutnAnd VoutpIs the output signal of the demodulator, VHFor output of offset-free induced voltage, VOSIs a noise signal.
8. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 7, wherein said unity gain amplifier comprises a third operational amplifier A3, output feedback resistors R6, R7, R8 and R9, wherein the input terminals of said third operational amplifier are respectively connected to the output terminals of said demodulator, and the output terminals are output to said low pass filter through a resistor R9.
9. The CMOS fully integrated electromagnetic sensing radio frequency front end sensor according to claim 8, wherein said low pass filter is an RC low pass filter, comprising a resistor R10 and a capacitor C1, wherein one end of the resistor R10 is connected to the output terminal of said unity gain amplifier, and the other end is used as the output terminal of said CMOS fully integrated electromagnetic sensing radio frequency front end sensor and is grounded through a capacitor C1.
10. The CMOS fully integrated electromagnetic detection rf front-end sensor according to claim 9, wherein the clock processing circuit comprises a 5-stage ring oscillator and a clock buffer, wherein the ring oscillator comprises a plurality of stages of delay units, an output oscillation signal of a last stage of delay unit is fed back to the clock buffer and the first stage of input to form a positive feedback, and an oscillation frequency of the oscillation signal is:
fOSC＝1/τpd＝1/(2×Nτp)，
wherein f isOSCTo the oscillation frequency, τpdFor inherent delay of inverters,. taupThe average value of the conversion time of the level of each level of inverter from low to high and from high to low;
the clock buffer comprises inverters INV1, INV2, INV3 and INV4, a flip-flop, a buffer1 and a buffer2, wherein one path of oscillation signals output by the ring oscillator passes through the inverter INV1 and is directly output to the flip-flop, the other path of oscillation signals is output to the flip-flop through the inverter INV2, two paths of outputs passing through the flip-flop are respectively divided into two paths of outputs after passing through the buffers buffer1 and 2, one path of output passing through the buffer1 is output to the switch S1B through the inverter INV3, and the other path of output is directly output to the switch S1; one output path of the output from the buffer2 passes through the inverter INV4 and is output to the switch S2B, and the other output path is directly output to the switch S1.
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