CN113556122A - High-speed high-linearity voltage-time converter applied to time domain analog-to-digital converter - Google Patents
High-speed high-linearity voltage-time converter applied to time domain analog-to-digital converter Download PDFInfo
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Abstract
Compared with the traditional voltage-time converter, the high-speed high-linearity voltage-time converter applied to the time domain analog-to-digital converter provided by the invention can allow the common-mode voltage of the input signal to be at a lower value, and is more suitable for the second-stage time domain analog-to-digital converter of the mixed-architecture analog-to-digital converter. Most of the traditional voltage-time converters improve the linearity by raising the input common-mode voltage, but the invention uses an auxiliary current branch circuit to conduct M4 in the reset stage so that the source end voltage of M4 is changed into the common-mode voltage value VCMCompared with the structure that the drain terminal voltage of the M2 is close to VDD in the reset phase of the traditional voltage-time converter, the linearity of the current source is influenced, and the current source with the structure can realize high linearity under the condition of lower input common-mode voltage.
Description
Technical Field
The invention belongs to the technical field of digital-to-analog converters, and particularly relates to a high-speed high-linearity voltage-to-time converter applied to a time domain analog-to-digital converter.
Background
With the development of CMOS process, hybrid architecture analog-to-digital converters (ADCs) are gaining attention. Referring to fig. 1, the analog-to-digital converter of the hybrid architecture is formed by mixing a voltage domain analog-to-digital converter and a time domain analog-to-digital converter. Since the output common-mode Voltage generated by the first stage in the hybrid architecture is relatively low, this means that the common-mode Voltage of the input signal of the Voltage Time Converter (VTC) of the second stage Time domain analog-to-digital converter is relatively low.
Referring to fig. 2, in the conventional VTC, an NOMS current source is used to discharge an input signal to a set threshold, and the input signal needs a higher input common-mode voltage, so that the range of the common-mode voltage is limited, the swing of the input signal is limited, and the universality of a quantization signal of an analog-to-digital converter is reduced. In addition, the VTC with the conventional structure usually uses a method of raising the input common-mode voltage or folding the common-mode voltage to improve the linearity, the former may not only affect the linearity of the preceding stage ADC, but also easily cause problems such as overvoltage and the like at a higher common-mode voltage, and the latter may bring extra consumption and introduce common-mode mismatch. Aiming at the linearity of VTC, an auxiliary current branch circuit is added in the circuit, so that high linearity can be realized under a lower input common-mode voltage.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a high-speed high-linearity voltage-to-time converter applied to a time domain analog-to-digital converter. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a high-speed high-linearity voltage-time converter applied to a time domain analog-to-digital converter, which comprises: the first conversion circuit and the second conversion circuit have the same structure, and both the first conversion circuit and the second conversion circuit comprise: a current source circuit and a threshold voltage detection circuit,
the current source circuit includes: the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are arranged in such a way that the grid electrode of the first MOS transistor M1 and the grid electrode of the second MOS transistor M2 of each current source circuit are connected with a first bias voltage VBOf 1 atThe source electrode of a MOS tube M1 is connected with a power supply voltage, the drain electrode of a first MOS tube M1 is connected with the source electrode of a second MOS tube M2, the drain electrode of the second MOS tube M2 is respectively connected with the source electrode of a third MOS tube M3 and the source electrode of a fourth MOS tube M4, the drain electrode of the third MOS tube M3 is connected with an input signal and the input of a threshold voltage detection circuit, and the gate electrode of the third MOS tube M3 is connected with a first clock signal phiSThe grid of the fourth MOS tube M4 is connected with the second clock signal
The drain electrode of the fourth MOS transistor M4 is connected with the common-mode voltage V of the input signalCMThe input signal comprises: first input signal VRESPAnd a second input signal VRESNThe current source circuit of the first conversion circuit is different from the input signal connected to the current source circuit of the second conversion circuit, and the first input signal V is different from the second input signal VRESPAnd a second input signal VRESNIs lower than one-half of the supply voltage.
The current source circuit is used for charging the voltage of the input signal of the current source circuit, and when the voltage value of the input signal reaches the threshold voltage value V of the threshold voltage detection circuitDETAt this time, the threshold voltage detection circuit changes the output signal outputted from itself to a high level.
Optionally, the drain of the third MOS transistor M3 in the first conversion circuit is connected to the first input signal VRESPThe drain of the third MOS transistor M3 in the second conversion circuit is connected to the second input signal VRESN。
Optionally, the output signal includes a first output signal SP and a second output signal SN, the output signal of the first conversion circuit is the first output signal SP, and the output signal of the second conversion circuit is the first output signal SN.
Optionally, the threshold voltage detection circuit includes:
a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16,
the grid of the fifth MOS transistor M5 is connectedThe drain of the third MOS transistor M3 is connected, the source of the fifth MOS transistor M5 is connected to the source of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9, the drain of the fifth MOS transistor M5 is connected to the gate and the drain of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8, and the gate of the sixth MOS transistor M6 is connected to the threshold voltage VDETThe drain of the sixth MOS transistor M6 is connected to the drain of the eighth MOS transistor M8, the drain of the sixteenth MOS transistor M16, the gate of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12, the source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are connected to the supply voltage, and the gate of the ninth MOS transistor M9 is connected to the second clock signal
The source of the ninth MOS transistor M9 is connected to the drain of the tenth MOS transistor M10, and the gate of the tenth MOS transistor M10 is connected to the second bias voltage VBCThe source of the tenth MOS transistor M10 is connected to the power ground, the source of the eleventh MOS transistor M11 and the source of the thirteenth MOS transistor M13 are connected to the power voltage, the drain of the eleventh MOS transistor M11 is connected to the drain of the twelfth MOS transistor M12 and the gate of the fourteenth MOS transistor M14, respectively, the source of the twelfth MOS transistor M12, the source of the fifteenth MOS transistor M15 and the source of the sixteenth MOS transistor M16 are connected to the power ground, and the gate of the thirteenth MOS transistor M13 and the gate of the fifteenth MOS transistor M15 are connected to the third clock signal ΦDThe drain of the thirteenth MOS transistor M13 is connected to the source of the fourteenth MOS transistor M14, the drain of the fourteenth MOS transistor M14 is connected to the drain of the fifteenth MOS transistor M15 and outputs a signal, and the gate of the sixteenth MOS transistor M16 is connected to the first clock signal ΦS。
Compared with the traditional VTC, the high-speed high-linearity voltage-time converter applied to the time domain analog-to-digital converter provided by the invention can allow the common-mode voltage of the input signal to be at a lower value, and is more suitable for the second-stage time domain analog-to-digital converter of the mixed-architecture analog-to-digital converter. In addition, the auxiliary current branch is used for conducting M4 in the reset stage, so that the source end voltage of M4 is changed into a common-mode voltage value VCMThe drain terminal voltage of the M2 in the reset stage of the traditional voltage-time converter can be prevented from approaching VDD, so that the linearity of the current source is improvedHigh linearity is achieved at common mode voltages.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is an overall block diagram of a hybrid architecture analog-to-digital converter;
FIG. 2 is a schematic diagram of a conventional VTC;
FIG. 3 is a block diagram of a high-speed high-linearity voltage-to-time converter applied to a time domain analog-to-digital converter according to an embodiment of the present invention;
fig. 4 is a timing diagram illustrating the operation of the high-speed high-linearity voltage-to-time converter according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
As shown in fig. 3, the present invention provides a high-speed high-linearity voltage-to-time converter applied to a time domain analog-to-digital converter, which includes: the first conversion circuit and the second conversion circuit with the same structure both comprise: a current source circuit and a threshold voltage detection circuit,
the current source circuit includes: the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are arranged in such a way that the grid electrode of the first MOS transistor M1 and the grid electrode of the second MOS transistor M2 of each current source circuit are connected with a first bias voltage VBThe source of the first MOS transistor M1 is connected to a power supply voltage, the drain of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, the drain of the second MOS transistor M2 is connected to the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4, respectively, the drain of the third MOS transistor M3 is connected to an input signal and the input of a threshold voltage detection circuit, and the gate of the third MOS transistor M3 is connected to the first clock signal ΦSThe grid of the fourth MOS tube M4 is connected with the second clock signal
The drain electrode of the fourth MOS transistor M4 is connected with the common-mode voltage V of the input signalCM. The input signal includes: first input signal VRESPAnd a second input signal VRESNThe current source circuit of the first conversion circuit is different from the input signal connected to the current source circuit of the second conversion circuit, and the first input signal V is different from the second input signal VRESPAnd a second input signal VRESNIs lower than half the supply voltage, i.e., VDD/2.
The current source circuit is used for charging the voltage of the input signal of the current source circuit, and when the voltage value of the input signal reaches the threshold voltage value V of the threshold voltage detection circuitDETAt this time, the threshold voltage detection circuit changes the output signal outputted from itself to a high level.
Wherein, the drain of the third MOS transistor M3 in the first conversion circuit is connected with the first input signal VRESPThe drain of the third MOS transistor M3 in the second conversion circuit is connected to the second input signal VRESN. The output signals include a first output signal SP and a second output signal SN, the output signal of the first conversion circuit is the first output signal SP, and the output signal of the second conversion circuit is the first output signal SN.
It will be appreciated that the common mode voltage is lower than VDD/2, meaning that the common mode voltage of the first input signal and the second input signal is a low input common mode.
Referring to fig. 3, the threshold voltage detection circuit includes:
a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16,
the grid of the fifth MOS tube M5 is connected with the drain of the third MOS tube M3, the source of the fifth MOS tube M5 is respectively connected with the source of the sixth MOS tube M6 and the drain of the ninth MOS tube M9, the drain of the fifth MOS tube M5 is respectively connected with the grid and the drain of the seventh MOS tube M7 and the grid of the eighth MOS tube M8, and the grid of the sixth MOS tube M6 is connected with the threshold voltage value VDETThe drain of the sixth MOS transistor M6 is connected to the drain of the eighth MOS transistor M8, the drain of the sixteenth MOS transistor M16, the gate of the eleventh MOS transistor M11, the gate of the twelfth MOS transistor M12, and the source of the seventh MOS transistor M7The source of the eighth MOS tube M8 and the pole are connected with the power supply voltage, and the gate of the ninth MOS tube M9 is connected with the second clock signal
The source of the ninth MOS transistor M9 is connected to the drain of the tenth MOS transistor M10, and the gate of the tenth MOS transistor M10 is connected to the second bias voltage VBCThe source of the tenth MOS transistor M10 is connected to the power ground, the source of the eleventh MOS transistor M11 and the source of the thirteenth MOS transistor M13 are connected to the power voltage, the drain of the eleventh MOS transistor M11 is connected to the drain of the twelfth MOS transistor M12 and the gate of the fourteenth MOS transistor M14, respectively, the source of the twelfth MOS transistor M12, the source of the fifteenth MOS transistor M15 and the source of the sixteenth MOS transistor M16 are connected to the power ground, and the gate of the thirteenth MOS transistor M13 and the gate of the fifteenth MOS transistor M15 are connected to the third clock signal ΦDThe drain of the thirteenth MOS transistor M13 is connected to the source of the fourteenth MOS transistor M14, the drain of the fourteenth MOS transistor M14 is connected to the drain of the fifteenth MOS transistor M15 and outputs a signal, and the gate of the sixteenth MOS transistor M16 is connected to the first clock signal ΦS。
The working principle of the high-speed high-linearity voltage-time converter applied to the time domain analog-to-digital converter provided by the invention is as follows:
the gate voltage of the constant current source composed of M1 and M2 is controlled by a bias voltage VBProviding, clock signal phiSThe gate of M3 is connected to control the on and off of the current source branch, the clock signal
The grid voltage of M10 is controlled by a bias voltage V by connecting the grids of M4 and M9BCProviding that the gate of M5 is connected to a given threshold voltage VDETThe gates of M13 and M15 are connected to a clock signal phiD。
Referring to FIG. 4, when the circuit is in the reset phase, the clock signal ΦSAt high, turn off M3 and turn on M16, stop charging and reset the output; clock signal
Is a low level conductorLeading the source end voltage of M4 to be equal to the input common-mode voltage V by M4CMWhile M9 is off; clock signal phiDAt clock signal phiSAfter a certain delay, the signal goes high, turning off M13 and turning on M15, and resetting the output SP/SN to low.
When the circuit is in the working phase, the clock signal
Going high turns on M9 and off M4; clock signal phiDAnd phiSAt the same time, it goes low, turning off M15 and M16 and turning on M13 and M3, the current source starts the signal V to the input terminalRESP/VRESNCharging, when charging to an input signal level greater than a given threshold voltage VDETThe time output signal SP/SN jumps high.
Due to the input signal VRESP/VRESNDifferent in size, and charged to the threshold voltage VDETIs equal to the time difference deltat between the two rising edges of the SP and SN signals, thereby completing the conversion of the voltage domain signal to the time domain signal.
In the conventional structure when phiSAt high level, the source voltage of M3, i.e. the drain voltage of M2, is close to VDD, resulting in a voltage value when phi isSWhen the voltage is low, the pseudo current mirror gm formed by the M1 and M2 tubes is reduced, mismatch is caused, and the linearity is adversely affected; in the improved structure of the invention, M4 is added when phi isSAt high level, the drain voltage of M2 is equal to VCMSo that can be at phiSThe saturation of the current source is maintained when M3 is turned on at low level, and the pseudo current mirror consisting of M1 and M2 is ensured to be in saturation region current pair VRESP/VRESNThe input voltage of the point is charged, and the linearity is improved.
Compared with the traditional VTC, the high-speed high-linearity voltage-time converter applied to the time domain analog-to-digital converter provided by the invention can allow the common-mode voltage of the input signal to be at a lower value, and is more suitable for the second-stage time domain analog-to-digital converter of the mixed-architecture analog-to-digital converter. And the present invention employs an auxiliary current branch,in the reset stage, M4 is turned on to change the source end voltage of M4 to a common mode voltage value VCMCompared with the structure that the drain terminal voltage of the M2 is close to VDD in the reset phase of the traditional voltage-time converter, the linearity of the current source is influenced, and the current source with the structure can realize high linearity under the condition of lower input common-mode voltage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (4)
1. A high speed, high linearity voltage-to-time converter for use in a time domain analog-to-digital converter, comprising: the first conversion circuit and the second conversion circuit have the same structure, and both the first conversion circuit and the second conversion circuit comprise: a current source circuit and a threshold voltage detection circuit,
the current source circuit includes: a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3) and a fourth MOS transistor (M4), wherein for each current source circuit, the grid electrode of the first MOS transistor (M1) and the grid electrode of the second MOS transistor (M2) are connected with a first bias voltage (V)B) The source electrode of the first MOS tube (M1) is connected with a power supply voltage, the drain electrode of the first MOS tube (M1) is connected with the source electrode of the second MOS tube (M2), the drain electrode of the second MOS tube (M2) is respectively connected with the source electrode of the third MOS tube (M3) and the source electrode of the fourth MOS tube (M4), the drain electrode of the third MOS tube (M3) is connected with an input signal and the input of the threshold voltage detection circuit, and the gate electrode of the third MOS tube (M3) is connected with a first clock signal (phi)S) The gate of the fourth MOS tube (M4) is connected with a second clock signal
The drain electrode of the fourth MOS tube (M4) is connected with an input signal common-mode voltage (V)CM) The input signal comprises: a first input signal (V)RESP) And a second input signal (V)RESN) The current source circuit of the first conversion circuit is different from the input signal connected to the current source circuit of the second conversion circuit, and the first input signal (V) is different from the second input signal (V)RESP) And a second input signal (V)RESN) Is lower than one-half of the supply voltage.
The current source circuit is used for charging the voltage of the input signal of the current source circuit, and when the voltage value of the input signal reaches the threshold voltage value (V) of the threshold voltage detection circuitDET) When the threshold voltage detection circuit is used, the output signal output by the threshold voltage detection circuit jumps to a high level.
2. The high-speed high-linearity voltage-to-time converter according to claim 1, wherein the drain of the third MOS transistor (M3) in the first conversion circuit is connected to the first input signal (V)RESP) The drain of the third MOS transistor (M3) in the second conversion circuit is connected with the second input signal (V)RESN)。
3. A high speed high linearity voltage to time converter according to claim 2, wherein the output signal comprises a first output Signal (SP) and a second output Signal (SN), the output signal of the first converting circuit being the first output Signal (SP) and the output signal of the second converting circuit being the first output Signal (SN).
4. The high speed high linearity voltage to time converter of claim 1, wherein the threshold voltage detection circuit comprises:
a fifth MOS transistor (M5), a sixth MOS transistor (M6), a seventh MOS transistor (M7), an eighth MOS transistor (M8), a ninth MOS transistor (M9), a tenth MOS transistor (M10), an eleventh MOS transistor (M11), a twelfth MOS transistor (M12), a thirteenth MOS transistor (M13), a fourteenth MOS transistor (M14), a fifteenth MOS transistor (M15) and a sixteenth MOS transistor (M16),
the grid electrode of the fifth MOS tube (M5) is connected with the drain electrode of the third MOS tube (M3), the source electrode of the fifth MOS tube (M5) is respectively connected with the source electrode of the sixth MOS tube (M6) and the drain electrode of the ninth MOS tube (M9), and the fifth MOS tube (M5)Is respectively connected with the grid electrode and the drain electrode of the seventh MOS tube (M7) and the grid electrode of the eighth MOS tube (M8), and the grid electrode of the sixth MOS tube (M6) is connected with the threshold voltage value (V)DET) The drain of the sixth MOS transistor (M6) is connected with the drain of the eighth MOS transistor (M8), the drain of the sixteenth MOS transistor (M16), the gate of the eleventh MOS transistor (M11) and the gate of the twelfth MOS transistor (M12), the source of the seventh MOS transistor (M7) and the source of the eighth MOS transistor (M8) are connected with a power supply voltage, and the gate of the ninth MOS transistor (M9) is connected with the second clock signal
The source electrode of the ninth MOS tube (M9) is connected with the drain electrode of the tenth MOS tube (M10), and the gate electrode of the tenth MOS tube (M10) is connected with the second bias voltage (V)BC) The source of the tenth MOS transistor (M10) is connected with a power ground, the source of the eleventh MOS transistor (M11) and the source of the thirteenth MOS transistor (M13) are connected with a power voltage, the drain of the eleventh MOS transistor (M11) is respectively connected with the drain of the twelfth MOS transistor (M12) and the gate of the fourteenth MOS transistor (M14), the source of the twelfth MOS transistor (M12), the source of the fifteenth MOS transistor (M15) and the source of the sixteenth MOS transistor (M16) are respectively connected with the power ground, and the gate of the thirteenth MOS transistor (M13) and the gate of the fifteenth MOS transistor (M15) are connected with a third clock signal (phi)D) The drain of the thirteenth MOS transistor (M13) is connected with the source of the fourteenth MOS transistor (M14), the drain of the fourteenth MOS transistor (M14) is connected with the drain of the fifteenth MOS transistor (M15) and outputs a signal, and the gate of the sixteenth MOS transistor (M16) is connected with the first clock signal (phi)S)。
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