CN113540104B

CN113540104B - Memory device

Info

Publication number: CN113540104B
Application number: CN202110375096.XA
Authority: CN
Inventors: 孙文堂; 许家荣; 陈学威
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2020-04-13
Filing date: 2021-04-08
Publication date: 2023-06-30
Anticipated expiration: 2041-04-08
Also published as: TW202139434A; CN113540104A; TWI757145B

Abstract

The invention discloses a memory device which comprises a first well, a second well, a third well, a floating gate layer, a first doping region, a second doping region, a third doping region, a groove isolation layer and a word line contact. The second well is located on the first well and comprises a first portion and a second portion. The third well includes a first portion and a second portion on the first portion and the second portion of the second well, respectively. The first doped region, the second doped region, and the third doped region are located in the first portion of the third well. The trench isolation layer is used to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well. The word line contact is disposed on the second portion of the third well region for receiving a word line voltage.

Description

Memory device

Technical Field

The present invention relates to memory devices, and more particularly to memory devices that include multiple wells created using the same mask.

Background

As electronic products continue to advance, the importance of memory also continues to increase. Regarding the characteristics of a memory device, there is a general demand for reducing the area occupied by the memory, improving the access speed, and reducing the power consumption.

However, it is not easy to achieve the above object. The conventional memory device in the prior art usually includes at least two transistors and needs to be matched with an additional erasing gate to operate normally, so that the device area is difficult to reduce. In order to manufacture the above structure, two or more masks are additionally used compared with the standard device, which results in difficulty in reducing the manufacturing cost.

Therefore, there is still a lack of suitable solutions in the art to achieve the effects of saving area, increasing access speed, reducing process cost and saving power consumption.

Disclosure of Invention

A memory device comprising a first well; a second well on the first well, including a first portion, and a second portion; a third well comprising a first portion and a second portion, the first portion being located on the first portion of the second well, the second portion being located on the second portion of the second well; a floating gate layer over the third well; a first doped region located in the first portion of the third well; a second doped region located in the first portion of the third well; a third doped region located in the first portion of the third well and adjacent to the first doped region; a trench isolation layer to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well; and a word line contact disposed on the second portion of the third well region for receiving a word line voltage.

Drawings

FIG. 1 is a top view of a memory device in an embodiment.

FIG. 2 is a cross-sectional view of the memory device of FIG. 1 along line 2-2'.

Fig. 3 to 7 are waveform diagrams showing the word line voltage rising from the first voltage to the second voltage when performing the write operation in the different embodiments.

FIG. 8 is a flow chart of a method of manufacturing a memory device according to an embodiment.

Wherein reference numerals are as follows:

100. memory device

110. First well

120. Second well

1201,1301 first part

1202,1302 second part

130. Third well

140. Fourth well

155. Floating gate layer

161. First doped region

162. Second doped region

163. Third doped region

170. Trench isolation layer

191. A first oxide layer

192. A second oxide layer

2-2' tangent

800. Method of manufacture

810 to 840 steps

A first overlapping area

B second overlap area

BL bit line contact

L channel length

SL source line contact

Time period T1, T2, T3, T4, T5, T91, T92, T93, T11, T12

TP, TP1, TP2, TP3, TP4, TP5 pause sections

VA, VB, VC, VD, VE Voltage

VBL bit line voltage

VH second voltage

VL first voltage

VSL source line voltage

VW1 first well voltage

VW2 second well voltage

VWL word line voltage

W1 first well contact

W2 second well contact

WL word line contact

Detailed Description

In order to solve the above problems, the embodiments provide a memory device and an operating method thereof, so as to achieve the effects of saving area, improving access speed, reducing manufacturing cost and saving power. FIG. 1 is a top view of a memory device 100 in an embodiment. FIG. 2 is a cross-sectional view of the memory device 100 of FIG. 1 along the line 2-2'. Fig. 1 and 2 are simplified schematic diagrams illustrating embodiments, not the detailed construction of the display and restriction device.

The memory device 100 includes a first well 110, a second well 120, a third well 130, a floating gate layer 155, a first doped region 161, a second doped region 162, a third doped region 163, and a trench isolation layer 170. The second well 120 is located on the first well 110 and includes a first portion 1201 and a second portion 1202. The third well 130 includes a first portion 1301 and a second portion 1302, wherein the first portion 1301 is located on the first portion 1201 of the second well 120 and the second portion 1302 is located on the second portion 1202 of the second well 120. Floating gate layer 155 is located over third well 130. The first doped region 161, the second doped region 162 and the third doped region 163 are located at the first portion 1301 of the third well 130, and the third doped region 163 is adjacent to the first doped region 161. The trench isolation layer 170 is used to isolate the first portion 1201 and the second portion 1202 of the second well 120, and isolate the first portion 1301 and the second portion 1302 of the third well 130. The trench isolation layer 170 may be a shallow trench isolation layer.

According to an embodiment, the first well 110 may be a p-type well, and the second well 120 and the third well 130 may be n-type wells. The memory device 100 may be a non-volatile memory.

As shown in fig. 2, according to an embodiment, the memory device 100 may optionally further include a fourth well 140 located under the first well 110 and having a doping type different from that of the first well; for example, the fourth well 140 may be a deep n-type well. The fourth well 140 may be used when circuits other than memories are fabricated.

According to an embodiment, as shown in fig. 2, the memory device 100 further includes a first oxide layer 191 and a second oxide layer 192. The first oxide layer 191 is located between the first portion 1301 of the third well 130 and the floating gate layer 155, and the second oxide layer 192 is located between the second portion 1302 of the third well 130 and the floating gate layer 155.

As shown in fig. 1 and 2, the first portion 1301 of the floating gate layer 155 and the third well 130 has a first overlap area a, and the second portion 1302 of the floating gate layer 155 and the third well 130 has a second overlap area B; and the first overlapping area a is smaller than the second overlapping area B. For example, the ratio of the first overlapping area a to the second overlapping area B may be approximately 1 to 5, or 1 to 10. According to an embodiment, the second overlap area B corresponds to the second oxide layer 192, and the second oxide layer 192 may be a coupling gate layer, also referred to as a control gate layer, of the memory device 100.

As shown in fig. 2, the memory device 100 may further include a source line contact (contact) SL, a bit line contact BL, and a word line contact WL. The source line contact SL is disposed on a contact surface between the first doped region 161 and the third doped region 163, coupled to the source line, and configured to receive the source line voltage VSL. The bit line contact BL is disposed on the second doped region 162, coupled to the bit line, and configured to receive the bit line voltage VBL. The word line contact WL is disposed on the second portion 1302 of the third well 130, coupled to the word line, and is configured to receive the word line voltage VWL.

The memory device 100 may optionally further include a first well contact W1 coupled to the first well 110 and configured to receive the first well voltage VW1. The memory device 100 may optionally further comprise a second well contact W2 coupled to the first portion 1201 of the second well 120 and configured to receive the second well voltage VW2.

Since the second overlap area B is sufficient to form a good plate-type (planar-type) capacitor, in the embodiment, when performing the write operation, the word line voltage VWL may use a ramp voltage (ramp voltage) to increase the write speed and reduce the write current, thereby achieving both the acceleration of access and the saving of power consumption. The waveform of the ramp-up voltage will be described later.

For example, the first doped region 161 and the second doped region 162 may be p-type doped regions (may be denoted as p+), and the third doped region 163 may be an n-type doped region (may be denoted as n+).

In fig. 2, the first doped region 161, the second doped region 162, and the channel between the first doped region 161 and the second doped region 162 may form a transistor structure (e.g., a PNP transistor). As shown in FIG. 2, each memory cell in the memory device 100 may include only one transistor, and thus may be referred to as a 1T structure. The memory device 100 of the embodiment may thus be of smaller size than conventional memory cells, which often have to include at least two transistors (hence the term 2T structure). In addition, by using the first well 110, the second well 120, and the third well 130, the channel length L between the first doped region 161 and the second doped region 162 can be shorter than that of the standard cell, so that the area of the memory device 100 can be further reduced.

Table 1 shows the operating voltages shown in FIGS. 2 and 3. As shown in table 1, the memory device 100 may be operated as follows.

When performing a write operation, the word line voltage VWL may be adjusted from a first voltage (ramp) to a second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted to the reference voltage VF.

When performing a read operation, the source line voltage VSL may be adjusted to the read voltage Vrd, the bit line voltage VBL may be adjusted to a low voltage (e.g., 0.4 volts), the word line voltage VWL may be adjusted to a fixed voltage, and the first well voltage VW1 may be adjusted to the reference voltage VF.

When performing an erase operation, the source line voltage VSL may be adjusted to the erase voltage Vee, the bit line voltage may be adjusted to the floating voltage VFL, and the word line voltage VWL and the first well voltage VW1 may be adjusted to the reference voltage VF.

(Table 1, voltage values in parentheses are examples only)

In tables 2 and 1, the write operation, the erase operation and the read operation are not performed simultaneously. According to an embodiment, the low voltage described in table 1 may be lower than the read voltage Vrd, the read voltage Vrd may be lower than the write voltage Vpp, and the write voltage Vpp may be lower than the erase voltage Vee. The thicker the oxide layers (e.g., the first oxide layer 191 and the second oxide layer 192), the higher the erase voltage Vee and the write voltage Vpp.

Table 2 shows another embodiment of the operating voltages shown in FIG. 2. As shown in table 2, the memory device 100 may be operated as follows.

When performing a write operation, the word line voltage VWL is adjusted from the first voltage to the second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted to the reference voltage VF.

When performing an erase operation, the source line voltage VSL is adjusted to the erase voltage Vee, the bit line voltage VBL is adjusted to the reference voltage VF, and the word line voltage VWL and the first well voltage VW1 are adjusted to a fixed voltage (e.g., between +1 volts and-2 volts).

When performing a read operation, the source line voltage VSL is adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage (e.g., 0.4 volts), the word line voltage VWL is adjusted to a fixed voltage (e.g., between 0 volts and 5 volts), and the first well voltage VW1 is adjusted to the reference voltage VF.

(Table 2, voltage values in parentheses are examples only)

In fig. 2 and table 2, the write operation, the erase operation, and the read operation are not performed simultaneously, and the erase operation is a Channel Hot Hole (CHH) erase operation. According to an embodiment, the low voltage described in Table 2 may be lower than the read voltage Vrd, the write voltage Vpp may be close to the erase voltage Vee, and the fixed voltage may be between positive and negative voltages (e.g., +1 and-2 volts).

Table 3 shows the operating voltages of FIG. 2 in another embodiment. As shown in table 3, the memory device 100 may be operated as follows.

When performing a write operation, the word line voltage VWL is adjusted from the first voltage to the second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, the bit line voltage VBL and the first well voltage VW1 are adjusted to the reference voltage VF, and the second well voltage VW2 (e.g., the same as the write voltage Vpp) is adjusted.

When performing an erase operation, the source line voltage VSL is adjusted to an erase voltage Vee, the bit line voltage VBL (e.g., the same as the erase voltage Vee) is adjusted, the word line voltage VWL is adjusted to a fixed voltage, the first well voltage VW1 is adjusted to a fixed voltage, and the second well voltage VW2 is adjusted to a reference voltage VF.

When performing a read operation, the source line voltage VSL is adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage, the word line voltage VWL is adjusted to a fixed voltage, the first well voltage VW1 is adjusted to the reference voltage VF, and the second well voltage VW2 (e.g., the same as the read voltage Vrd) is adjusted.

(Table 3, voltage values in parentheses are examples only)

In tables 2 and 3, the write operation, the erase operation, and the read operation are not performed simultaneously, and the erase operation may be a band-to-band hot hole (BBHH) erase operation. According to an embodiment, the low voltage described in table 3 may be less than the read voltage Vrd, and the read voltage Vrd may be less than the write voltage Vpp. In an erase operation, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL, and the first well voltage VW1 may be negative voltages. According to an embodiment, when performing a write operation and performing a read operation, the source line voltage VSL may be substantially equal to the second well voltage VW2.

According to the embodiment, the reference voltage VF in table 1, table 2 and table 3 may be zero voltage or ground voltage. In tables 1, 2 and 3, the voltage values in brackets are merely examples to help understand the principles of the embodiments, and not to limit the scope of the embodiments; the voltage value used can be adjusted according to the requirements, the manufacturing process and the statistical result. Each of the write voltage Vpp, the erase voltage Vee, and the read voltage Vrd described above may be different in the cases of table 1, table 2, and table 3.

Fig. 3 to 7 are waveform diagrams showing the word line voltage VWL rising from the first voltage (ramp) to the second voltage when performing the write operation in tables 1, 2 and 3 according to various embodiments. According to an embodiment, when performing a write operation, the waveform of the word line voltage VWL rising from the first voltage VL to the second voltage VH may include a line rising waveform, a ladder waveform, and/or an arc waveform. The first voltage VL and the second voltage VH of fig. 3 to 7 may correspond to the first voltage and the second voltage of table 1 to table 3.

In fig. 3 to 7, the first voltage VL may be a start voltage at which the word line voltage VWL starts to rise, and according to an embodiment, the first voltage VL may be set to be lower than the source line voltage VSL by a predetermined value when performing a write operation; the predetermined value may be, for example, 0.5 volts to 2 volts.

When the word line voltage VWL rises faster, the write operation can be accelerated, however, the probability of a stuck-at fault also increases, so that the waveform slope of the rising word line voltage VWL can be adjusted according to the actual situation to achieve both the operation speed and the accuracy.

As shown in fig. 3 and 5, the waveform in which the word line voltage VWL rises may include a straight line waveform. As shown in fig. 4 and 6, the waveform of the rising word line voltage VWL may include an arc waveform. As shown in fig. 7, the waveform in which the word line voltage VWL rises may include a staircase waveform.

According to an embodiment, the waveform of the word line voltage VWL rising from the first voltage to the second voltage may include at least one pause period when performing the write operation, as shown in fig. 5, 6 and 7. The method of operating the memory device 100 further includes verifying whether the potential of the word line reaches a predetermined potential during the pause interval.

For example, in fig. 5 and 6, it can be verified whether the potential of the word line reaches the predetermined potential in the pause interval TP. For example, in fig. 7, the word line voltage VWL may be stepped up from the first voltage VL to the voltage VA in the period T1, and it is verified whether the word line voltage reaches the predetermined voltage in the pause period TP 1. If not, the word line voltage VWL may be raised to the voltage VB in the subsequent period T2, and it may be verified whether the word line voltage reaches the predetermined voltage in the pause period TP 2. Similarly, the word line voltage VWL may be raised to the voltage VC during the period T3, the word line potential may be verified during the pause period TP3, the word line voltage VWL may be raised to the voltage VD during the period T4, the word line potential may be verified during the pause period TP4, the word line voltage VWL may be raised to the voltage VE during the period T5, and the word line potential may be verified during the pause period TP 5. In fig. 7, in the pause period TP5, it is verified that the word line voltage VWL is not increased any more when the word line voltage reaches the predetermined voltage, i.e., the second voltage VH.

In fig. 5 to 7, the time for each voltage application is adjustable. For example, the lengths of the periods T91, T92, and T93 of fig. 6 may be the same or different; the lengths of the periods T11 and T12 of fig. 7 may be the same or different.

FIG. 8 is a flow chart of a method 800 for manufacturing the memory device 100 in accordance with an embodiment. The method 800 of manufacturing may include at least the steps of:

step 810: performing an oxidation process to generate a first oxide layer 191 and a second oxide layer 192;

step 820: generating at least one trench isolation layer;

step 830: performing a planarization process; a kind of electronic device with high-pressure air-conditioning system

Step 840: plural ion implants are performed using the same mask to create the first well 110, the second well 120, and the third well 130, respectively.

According to an embodiment, the same mask may be used for ion implantation after performing an oxidation process, creating a trench isolation layer (e.g., trench isolation layer 170), and performing a planarization process (e.g., chemical mechanical planarization process, CMP) to create the first well 110, the second well 120, and the third well 130. Compared to the fabrication of standard devices, the masks used to create the first well 110, the second well 120, and the third well 130 are additional masks, and according to the embodiments, only one additional mask is used to form the first well 110, the second well 120, and the third well 130, so that the process can be simplified. After the first well 110, the second well 120, and the third well 130 are created, ion implantation may be performed to create the wells required for the logic device. Ion implantation may be performed in addition to create the fourth well 140, according to an embodiment.

According to an embodiment, a Thinning down (Thinning down) process may be further performed to reduce the thickness of the first oxide layer 191 and the second oxide layer 192, thereby reducing the source line voltage VSL required when performing the writing operation and the erasing operation.

Taking table 1 above as an example, if the thicknesses of the first oxide layer 191 and the second oxide layer 192 are reduced during the manufacturing process, the write voltage Vpp may be reduced, for example, less than 5.5 volts, and the erase voltage Vee may be reduced, for example, less than 13 volts. After the thickness of the first oxide 191 and the second oxide 192 of the memory device 100 is reduced, the thickness of the first oxide is greater than the thickness of the oxide of the core (core) device and less than the thickness of the oxide of the input/output (I/O) device.

In summary, the memory device 100 provided in the embodiments can reduce the size of the memory cell by using the first well 110, the second well 120, and the third well 130, so that the memory cell includes only a single transistor and the channel length of the transistor can be reduced. Since the write current can be reduced, power consumption can be effectively reduced. Since the coupling gate of the memory device 100 has a good plate capacitance, the word line voltage VWL can use a rising waveform, so that the write operation can be accelerated. By using the first well 110, the second well 120, and the third well 130, a breakdown problem can be effectively prevented, so that reliability can be improved. The first well 110, the second well 120 and the third well 130 can be formed by using the same mask, so that the cost and complexity of the process can be effectively reduced. According to the experiment, the operation current and voltage of the memory device 100 are not significantly reduced after 10000 accesses, so the endurance is excellent. By the operation method provided by the embodiment, the potential of the word line can be verified in real time when the word line voltage VWL is regulated, so that the operation and verification are facilitated. The memory device 100 supports a variety of operating principles and is therefore highly flexible in operation. Accordingly, the memory device and method of manufacture provided by the embodiments are beneficial in reducing many of the long-term challenges in the art.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, the memory device comprising:

a first well;

a second well on the first well, including a first portion, and a second portion;

a third well comprising a first portion and a second portion, the first portion being located on the first portion of the second well, the second portion being located on the second portion of the second well;

a floating gate layer over the third well;

a first doped region located in the first portion of the third well;

a second doped region located in the first portion of the third well;

a third doped region located in the first portion of the third well and adjacent to the first doped region; a trench isolation layer to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well; a kind of electronic device with high-pressure air-conditioning system

And a word line contact disposed on the second portion of the third well region for receiving a word line voltage.

2. The memory device of claim 1, wherein the first well is a p-type well and the second well and the third well are n-type wells.

3. The memory device of claim 1, further comprising:

and a fourth well, which is positioned below the first well and has a doping type different from that of the first well.

4. The memory device of claim 1, wherein the first portion of the floating gate layer and the third well has a first overlap area; the floating gate layer and the second portion of the third well have a second overlap area; and the first overlapping area is smaller than the second overlapping area.

5. The memory device of claim 1, further comprising:

a first oxide layer between the first portion of the third well and the floating gate layer; a kind of electronic device with high-pressure air-conditioning system

A second oxide layer between the second portion of the third well and the floating gate layer.

6. The memory device of claim 5, further comprising:

and the source line contact is arranged on the contact surface between the first doped region and the third doped region and is used for receiving source line voltage.

7. The memory device of claim 6, further comprising:

and the bit line contact is arranged on the second doped region and is used for receiving bit line voltage.

8. The memory device of claim 7, further comprising:

the first trap contact is arranged on the first trap to receive a first trap voltage.

9. The memory device of claim 8, further comprising:

and a second well contact disposed at the first portion of the second well to receive a second well voltage.

10. The memory device of claim 1, wherein the first doped region and the second doped region are p-type doped regions and the third doped region is an n-type doped region.