CN113539833A - Manufacturing method of split gate power MOSFET device - Google Patents

Manufacturing method of split gate power MOSFET device Download PDF

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CN113539833A
CN113539833A CN202110834666.7A CN202110834666A CN113539833A CN 113539833 A CN113539833 A CN 113539833A CN 202110834666 A CN202110834666 A CN 202110834666A CN 113539833 A CN113539833 A CN 113539833A
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oxide layer
groove
etching
gate
silicon nitride
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CN113539833B (en
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乔明
王正康
马涛
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The invention provides a manufacturing method of a split gate power MOSFET device, wherein the preparation of a control gate comprises the following steps: after a dielectric layer between the control gate and the separation gate is formed, thermally growing sacrificial oxygen and depositing silicon nitride, wherein the silicon nitride is separated from the silicon layer by the sacrificial oxygen; depositing an oxide layer and etching back to a position lower than the upper surface of the silicon nitride in the MESA region, and etching the oxide layer and the silicon nitride by using MASK (MASK etching), wherein silicon nitride with a certain vertical height is reserved in the groove; depositing an oxide layer, removing part of the oxide layer by adopting a mode of combining CMP and wet etching until an interface of the oxide layer keeps a certain distance from an upper interface of the separation gate, and etching the residual silicon nitride; and depositing polycrystal and etching back to form a control gate. According to the method, the silicon nitride layer is adopted to shield the etching of the oxide layer, the control gate with a narrower lower part is formed, the control gate process is easy to realize, and meanwhile, the overlapping of the control gate and the separation gate is reduced, so that the gate-source capacitance is reduced. The larger cross-sectional area of the upper part of the separation gate reduces the gate-source capacitance and the gate charge and ensures that the gate resistance is not basically degraded.

Description

Manufacturing method of split gate power MOSFET device
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a split gate power MOSFET device.
Background
The power MOSFET device has the advantages of high switching speed, high input impedance, good thermal stability and the like, is concerned about intelligent power integrated circuits such as power management and motor drive, and the requirements of rapid development in new energy vehicles, Internet of things, artificial intelligence and other emerging fields on the power consumption and efficiency of the power MOSFET device are also stricter nowadays, so that the advantages of the split-gate power MOSFET device in the middle and low voltage field are gradually reflected. The device structure utilizes the capacitance coupling effect between the separated gate electrode and the shielding control gate electrode and the epitaxial layer to reduce the gate-drain parasitic capacitance Cgd, and simultaneously the separated gate electrode plays a role of an in-vivo field plate and is used for assisting in depletion of carriers in a drift region, so that the electric field distribution of the drift region is optimized, and the device structure has the advantages of low specific on resistance and low gate charge. However, split-gate power MOSFET devices introduce parasitic capacitance associated with the split-gate electrode: the capacitance between the drain and the split gate electrode Cds and the capacitance between the gate and the split gate electrode Cgs, the added parasitic capacitance, to some extent, offsets the advantage of the split gate MOSFET device in reducing the gate-drain capacitance Cgd. Cgs and Cds disadvantageously increase the input and output capacitance of the device, which may affect the operating efficiency of the whole system to some extent, and especially in the high-frequency and high-efficiency operating state, it is increasingly important to reduce the parasitic capacitance from the drain and the gate to the split gate electrode.
Therefore, in response to the above problems, it is desirable to reduce the parasitic capacitance associated with split gate electrodes in conventional split gate power MOSFET devices, and embodiments of the present invention are presented in this context.
Disclosure of Invention
The invention provides a manufacturing method of a split gate power MOSFET device, wherein the preparation process of a control gate electrode comprises the following steps: after a dielectric layer between the control gate and the separation gate is formed, depositing or thermally growing a sacrificial oxide layer, depositing a thin silicon nitride layer to cover the whole active region and the terminal region, wherein the sacrificial oxide layer is used as an isolation layer between the silicon nitride and a silicon layer of the MESA region; after depositing an oxide layer, etching back to the position slightly lower than the upper surface of the silicon nitride layer in the MESA area, and etching the oxide layer and the silicon nitride by using a mask plate to ensure that only the silicon nitride of a vertical part is reserved in the groove; after depositing an oxide layer, etching the oxide layer with a certain thickness by adopting a mode of combining chemical mechanical polishing and wet etching, and then etching away the residual silicon nitride; and depositing polysilicon and etching back to form a control gate electrode. The manufacturing method is based on the preparation improvement of the traditional separated gate power MOSFET device provided by B.J.Balia, the lower half part of a control gate is formed in a mode of etching a thin silicon nitride shielding oxide layer, the shape of the control gate is easy to realize in process, and meanwhile, the overlapping area of the control gate and a separated gate electrode can be reduced, so that the gate source parasitic capacitance Cgs is reduced. The upper half part of the separation gate electrode keeps a larger cross-sectional area similar to that of a traditional separation gate structure, so that the gate-source capacitance Cgs and the gate charge Qg are reduced to a certain extent, and the resistance value of the gate is basically not degraded. The desired goal of combining high switching speed with low switching losses is achieved.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a manufacturing method of a split gate power MOSFET device comprises the following steps:
1) forming a series of groove structures on the epitaxial layer by using a first mask, wherein the groove structures comprise a control gate groove of an active area and a separation gate groove of a terminal area, the control gate groove and a first terminal area groove structure vertical to the control gate groove are separated by an MESA area, and then forming a first dielectric layer on the inner wall of the groove structure;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2) by using a second mask, forming a separation gate electrode at the lower half part of a control gate groove of the active region, and forming a complete separation gate electrode in a separation gate groove of the terminal region;
4) depositing a dielectric layer to fill all the groove structures, back-etching by using a third mask, and forming a second dielectric layer in the groove of the active area and on the upper part of the separation gate as a dielectric layer between the control gate and the separation gate electrode;
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing silicon nitride in the groove structure to cover the active region and the terminal region;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be lower than the upper surface of the silicon nitride layer in the MESA region;
7) etching the oxide layer in the groove of the active region by using a fourth mask by a wet method, and then etching the silicon nitride deposited in the step 5) by a dry method, so that the silicon nitride of a vertical part with a certain height is reserved in the groove, and the upper surface of the silicon nitride is lower than that of the silicon layer in the MESA region;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; etching the residual silicon nitride in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method;
9) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric layer covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
10) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
11) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region by using a fifth mask;
12) depositing an oxide layer, and etching a contact hole in a source region and a separation gate lead-out region by using a sixth mask;
13) and depositing metal, and forming source metal in part of the active region and gate metal in part of the active region by using a seventh mask.
Preferably, in the step 1), the trench structure of the active region and the first termination region trench structure perpendicular thereto are connected in the process of forming the trench structure on the epitaxial layer by using the first mask.
Preferably, the first dielectric layer formed in step 1) is made of a low-k material with k less than 3.9.
Preferably, the second dielectric layer formed in step 4) is made of a low-k material with a k less than 3.9.
Preferably, step 5) is performed without thermally growing or depositing a sacrificial oxide layer, and the silicon nitride is deposited directly in the trench structure to cover the active region and the termination region.
Preferably, step 5) to step 8) use polysilicon instead of silicon nitride as follows:
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing a polycrystalline silicon covering active region and a terminal region in the groove structure;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be slightly lower than the upper surface of the MESA region polycrystalline silicon layer;
7) etching the oxide layer in the groove of the active area by using a fourth mask by a wet method, and then etching the polycrystalline silicon deposited in the step 5) by a dry method, so that the vertical part of the polycrystalline silicon with a certain height is reserved in the groove, and the upper surface of the polycrystalline silicon is lower than that of the silicon layer in the MESA area;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; and etching the residual polysilicon in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method.
Preferably, the thickness of the deposited silicon nitride layer in the step 5) is controlled to finally obtain the width of the vertical part of the control gate electrode meeting the requirement, and the thickness of the silicon nitride layer is at least 20-30 nm.
Preferably, the etching thickness of the silicon nitride is controlled in the step 7), and the wet etching thickness of the oxide layer is controlled in the step 8), so that the upper surface of the oxide layer after etching is lower than the upper surface of the silicon nitride reserved in the groove.
As a preferable mode, after the fourth mask is used for etching the oxide layer and the silicon nitride in the groove of the active region in the step 7), the active region is ensured to be connected with the silicon nitride layer of the terminal region, and the risk of silicon nitride layer drifting in the subsequent etching process is reduced.
The invention has the beneficial effects that: in the preparation process of the control gate electrode, in the steps 5) to 8), after depositing a thin silicon nitride layer in the groove, back etching is carried out, so that only the vertical part of the silicon nitride layer is reserved, after depositing the oxide layer, an oxide layer with a certain thickness is etched in a mode of combining chemical mechanical polishing and wet etching, after etching the silicon nitride layer on the vertical part in the groove and sacrificing oxygen, polysilicon is deposited and back etched, the lower half part of the formed control gate electrode is narrower, the overlapping area of the control gate electrode and the separated gate electrode is smaller, and the gate source capacitance Cgs can be greatly reduced. Meanwhile, the upper half part of the control gate electrode is obviously wider, so that the cross-sectional area for flowing of gate current is increased to a certain extent, and the gate resistance is effectively reduced. The manufacturing method is easy to implement in process, and meanwhile, a separation gate device structure with low gate charge and low gate resistance characteristics can be obtained.
Drawings
Fig. 1 is a schematic structural diagram of a conventional split-gate power MOSFET device.
Fig. 2 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method of embodiment 1 according to the present invention.
Fig. 3 is a flowchart of a method for manufacturing a split-gate power MOSFET device according to embodiment 1 of the present invention, which is sequentially from left to right and from top to bottom.
Fig. 4 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method of embodiment 2 according to the present invention.
FIG. 5 is a partial step diagram of a manufacturing method proposed in embodiment 3 of the present invention, which is used to replace the processes (e) to (l) in FIG. 3; the differences from the manufacturing method described in example 1 of the present invention are: and 5) directly depositing a thin silicon nitride covering active area and a terminal area in the groove structure.
Fig. 6 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method according to embodiment 4 of the present invention.
Fig. 7 is a schematic structural diagram of a split-gate power MOSFET device obtained by the manufacturing method according to embodiment 5 of the present invention.
The active region trench structure includes a substrate 10 of a first conductivity type, an epitaxial layer 11 of the first conductivity type, an active region trench structure 121, a first terminal region trench structure 122, a first dielectric layer 131, a second dielectric layer 132, a gate dielectric layer 133, a third dielectric layer 134, and a sacrificial oxide layer 14; 15 is a shielding layer, which can be silicon nitride or polysilicon; 16 is a split gate electrode, 17 is a control gate electrode, 18 is a second conductivity type well region, 19 is a second conductivity type heavily doped region, 20 is a first conductivity type heavily doped source region, and 21 is a metal.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
As shown in fig. 3, a method for manufacturing a split gate power MOSFET device includes the steps of:
1) forming a series of groove structures on the epitaxial layer by using a first mask, wherein the groove structures comprise a control gate groove of an active area and a separation gate groove of a terminal area, the control gate groove and a first terminal area groove structure vertical to the control gate groove are separated by an MESA area, and then forming a first dielectric layer on the inner wall of the groove structure;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2) by using a second mask, forming a separation gate electrode at the lower half part of a control gate groove of the active region, and forming a complete separation gate electrode in a separation gate groove of the terminal region;
4) depositing a dielectric layer to fill all the groove structures, back-etching by using a third mask, and forming a second dielectric layer in the groove of the active area and on the upper part of the separation gate as a dielectric layer between the control gate and the separation gate electrode;
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing silicon nitride in the groove structure to cover the active region and the terminal region;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be lower than the upper surface of the silicon nitride layer in the MESA region;
7) etching the oxide layer in the groove of the active region by using a fourth mask by a wet method, and then etching the silicon nitride deposited in the step 5) by a dry method, so that the silicon nitride of a vertical part with a certain height is reserved in the groove, and the upper surface of the silicon nitride is lower than that of the silicon layer in the MESA region;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; etching the residual silicon nitride in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method;
9) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric layer covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
10) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
11) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region by using a fifth mask;
12) depositing an oxide layer, and etching a contact hole in a source region and a separation gate lead-out region by using a sixth mask;
13) and depositing metal, and forming source metal in part of the active region and gate metal in part of the active region by using a seventh mask.
Preferably, in the manufacturing method, the steps 5) to 8) may adopt polysilicon instead of silicon nitride:
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing a thin layer of polycrystalline silicon in the groove structure to cover the active region and the terminal region;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be slightly lower than the upper surface of the MESA region polycrystalline silicon layer;
7) etching the oxide layer in the groove of the active area by using a fourth mask by a wet method, and then etching the polycrystalline silicon deposited in the step 5) by a dry method, so that the vertical part of the polycrystalline silicon with a certain height is reserved in the groove, and the upper surface of the polycrystalline silicon is lower than that of the silicon layer in the MESA area;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; etching the residual polysilicon in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method;
preferably, step 5) of the manufacturing method can control the thickness of the deposited silicon nitride layer (the minimum thickness can be 20-30nm), and finally obtain the required width of the vertical part of the control gate electrode.
Preferably, in the manufacturing method, step 7) needs to control the etching thickness of the silicon nitride, and step 8) needs to accurately control the wet etching thickness of the oxide layer, so as to ensure that the upper surface of the oxide layer after etching is slightly lower than the upper surface of the silicon nitride remained in the groove.
Preferably, in step 7) of the manufacturing method, after the fourth mask is used for etching the oxide layer and the silicon nitride in the groove of the active region, the active region is ensured to be connected with the silicon nitride layer of the terminal region, and the risk of silicon nitride layer drifting in the subsequent etching process is reduced.
Example 2
As shown in fig. 4, the present embodiment is different from the manufacturing method described in embodiment 1 in that: in the step 1), the first mask is used to connect the trench structure of the active region and the first termination region trench structure 122 perpendicular thereto in the process of forming the trench structure on the epitaxial layer.
Example 3
As shown in fig. 5, a partial step diagram of a manufacturing method of a split gate power MOSFET device is used to replace the processes (e) - (j) in fig. 3, and the difference between this embodiment and the manufacturing method described in embodiment 1 is: and 5) directly depositing a thin silicon nitride covering active area and a terminal area in the groove structure without adopting a thermal growth or sacrificial oxide layer deposition mode.
Example 4
As shown in fig. 6, the present embodiment is different from the manufacturing method described in embodiment 1 in that: the first dielectric layer surrounding the separation gate electrode formed in the step 1) is made of a low-k material with k less than 3.9 instead of silicon dioxide, so that the source-drain capacitance can be further reduced.
Example 5
As shown in fig. 7, the present embodiment is different from the manufacturing method described in embodiment 1 in that: and 4) the second dielectric layer formed in the step 4) adopts a low-k material with k less than 3.9 to replace silicon dioxide, so that the gate-source capacitance can be further reduced.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A manufacturing method of a split gate power MOSFET device is characterized by comprising the following steps:
1) forming a series of groove structures on the epitaxial layer by using a first mask, wherein the groove structures comprise a control gate groove of an active area and a separation gate groove of a terminal area, the control gate groove and a first terminal area groove structure (122) vertical to the control gate groove are separated by an MESA area, and then forming a first dielectric layer on the inner wall of the groove structure;
2) depositing polycrystalline silicon in the groove structure to enable the polycrystalline silicon to fill the whole groove;
3) etching the polycrystalline silicon deposited in the step 2) by using a second mask, forming a separation gate electrode at the lower half part of a control gate groove of the active region, and forming a complete separation gate electrode in a separation gate groove of the terminal region;
4) depositing a dielectric layer to fill all the groove structures, back-etching by using a third mask, and forming a second dielectric layer in the groove of the active area and on the upper part of the separation gate as a dielectric layer between the control gate and the separation gate electrode;
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing silicon nitride in the groove structure to cover the active region and the terminal region;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be lower than the upper surface of the silicon nitride layer in the MESA region;
7) etching the oxide layer in the groove of the active region by using a fourth mask by a wet method, and then etching the silicon nitride deposited in the step 5) by a dry method, so that the silicon nitride of a vertical part with a certain height is reserved in the groove, and the upper surface of the silicon nitride is lower than that of the silicon layer in the MESA region;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; etching the residual silicon nitride in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method;
9) thermally growing the upper half part of the control gate groove in the active region to form a gate dielectric layer covering the side wall; then depositing polysilicon in the active region to fill the whole groove;
10) etching the polysilicon deposited in the step 9), and forming a control gate electrode on the upper half part in the control gate groove of the active region;
11) forming a second conductive type well region on the upper surface of the epitaxial layer, and forming a first conductive type source region in the second conductive type well region by using a fifth mask;
12) depositing an oxide layer, and etching a contact hole in a source region and a separation gate lead-out region by using a sixth mask;
13) and depositing metal, and forming source metal in part of the active region and gate metal in part of the active region by using a seventh mask.
2. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: in the process of forming the groove structure on the epitaxial layer by using the first mask in the step 1), the groove structure of the active area and a first terminal area groove structure (122) vertical to the groove structure are connected.
3. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: the first dielectric layer formed in the step 1) is made of a low-k material with k less than 3.9.
4. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: the second dielectric layer formed in the step 4) is made of a low-k material with k less than 3.9.
5. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 5) directly depositing silicon nitride in the groove structure to cover the active region and the terminal region without adopting a mode of thermal growth or sacrificial oxide layer deposition.
6. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 5) replacing silicon nitride with polysilicon in the steps 5) to 8), and the steps are as follows:
5) thermally growing or depositing a sacrificial oxide layer with a certain thickness, and then depositing a polycrystalline silicon covering active region and a terminal region in the groove structure;
6) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer by a wet method to enable the upper surface of the etched oxide layer to be slightly lower than the upper surface of the MESA region polycrystalline silicon layer;
7) etching the oxide layer in the groove of the active area by using a fourth mask by a wet method, and then etching the polycrystalline silicon deposited in the step 5) by a dry method, so that the vertical part of the polycrystalline silicon with a certain height is reserved in the groove, and the upper surface of the polycrystalline silicon is lower than that of the silicon layer in the MESA area;
8) depositing an oxide layer in the groove structure to enable the oxide layer to fill the whole groove, and then etching the oxide layer with a certain thickness by adopting a chemical mechanical polishing mode and a wet method until a certain distance is kept between the upper surface of the oxide layer and the upper surface of the polysilicon of the separation gate; and etching the residual polysilicon in the groove and the sacrificial oxide layer thermally grown or deposited in the step 7) by a wet method.
7. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 5) controlling the thickness of the deposited silicon nitride layer to finally obtain the width of the vertical part of the control gate electrode meeting the requirement, wherein the minimum thickness of the silicon nitride layer is 20-30 nm.
8. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 7) controlling the etching thickness of the silicon nitride, and controlling the wet etching thickness of the oxide layer in the step 8), so as to ensure that the upper surface of the etched oxide layer is lower than the upper surface of the silicon nitride reserved in the groove.
9. The method of claim 1, wherein the step of forming the split-gate power MOSFET comprises: and 7) after the fourth mask is used for etching the oxide layer and the silicon nitride in the groove of the active region, the active region is ensured to be connected with the silicon nitride layer of the terminal region, and the risk of silicon nitride layer drifting in the subsequent etching process is reduced.
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