CN113078066B - Manufacturing method of split gate power MOSFET device - Google Patents

Manufacturing method of split gate power MOSFET device Download PDF

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CN113078066B
CN113078066B CN202110342787.XA CN202110342787A CN113078066B CN 113078066 B CN113078066 B CN 113078066B CN 202110342787 A CN202110342787 A CN 202110342787A CN 113078066 B CN113078066 B CN 113078066B
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etching
gate
polysilicon
oxide layer
silicon nitride
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CN113078066A (en
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乔明
马涛
王正康
张波
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University of Electronic Science and Technology of China
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Abstract

The invention provides a manufacturing method of a split gate power MOSFET device, which comprises the following steps: after a dielectric layer between the control gate and the separation gate is formed, a sacrificial oxide layer is deposited or thermally grown, and deposited silicon nitride fills the whole groove structure, wherein the silicon nitride and the MESA region silicon layer are isolated by the sacrificial oxide; after etching silicon nitride, the silicon nitride remained in the groove is used as a shielding layer for the etching of the next oxide layer; etching the oxide layer until the interface is higher than the upper interface of the step-shaped separation gate, and then etching away the residual silicon nitride; polysilicon is deposited and etched back to form the control gate electrode. The device structure prepared by the invention has the advantages that the lower half part of the control gate is narrower, the gate-source capacitance Cgs can be greatly reduced, meanwhile, the cross section area of the gate current flow is increased by the upper half part of the control gate, the gate resistance is reduced on the premise of ensuring that the gate-source capacitance Cgs and the gate charge Qg are not degraded, and the targets of high switching speed and low switching loss are realized.

Description

Manufacturing method of split gate power MOSFET device
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of a split gate power MOSFET device.
Background
With the continuous development of new fields of electronic information industry, power semiconductor devices also come to be a new round of development peak, and simultaneously, higher requirements on the performance of power MOSFETs are put forward, and lower switching loss and higher working efficiency become the development trend of power devices. The advantages of the power VDMOS with high frequency and low power consumption are gradually reflected, and the power VDMOS is widely applied in the fields of power management and the like. And the split gate power MOSFET device structure developed based on the Trench MOSFET device utilizes the capacitive coupling between the split gate electrode shielding control gate electrode and the epitaxial layer to reduce the parasitic capacitance Cgd of the gate drain. Meanwhile, the separated gate electrode is used as an in-body field plate, and the drift region carrier is used for assisting in depletion, so that the doping concentration of the drift region of the device can be remarkably improved, and the specific on-resistance can be reduced. However, split gate power MOSFET devices introduce parasitic capacitance associated with the split gate electrode: the increased parasitic capacitance counteracts to some extent the advantage of the split gate MOSFET device in reducing the gate-drain capacitance Cgd, as well as the capacitance Cds between the drain and the split gate electrode and Cgs between the gate and the split gate electrode. The higher input-output capacitance adversely affects the operating efficiency of the system, and it is now becoming increasingly important to reduce the capacitance of the drain and gate to the split gate electrode in order to meet the requirements of higher operating frequencies.
Accordingly, in view of the above problems, there is a need for reducing parasitic capacitance associated with split gate electrodes in conventional split gate MOSFET devices, and a method of fabricating a split gate power MOSFET device in accordance with the present invention has been developed in this context.
Disclosure of Invention
The invention provides a manufacturing method of a split gate power MOSFET device, wherein the manufacturing process of a control gate electrode comprises the steps of depositing or thermally growing a sacrificial oxide layer after a dielectric layer between the control gate and the split gate is formed, depositing silicon nitride to fill the whole groove structure, wherein the sacrificial oxide layer is used as an isolation layer between the silicon nitride and a silicon layer of an MESA region; etching the silicon nitride so that the silicon nitride remained in the groove serves as a shielding layer for the etching of the next oxide layer; etching an oxide layer with a certain thickness, etching residual silicon nitride, depositing polysilicon and etching back to form a control gate electrode. Compared with the preparation of the traditional split gate power MOSFET device, the manufacturing method is easy to implement and does not need to increase a mask photoetching process, and the parasitic capacitance Cgs and gate charge Qg between the control gate and the split gate electrode in the traditional split gate power MOSFET device are obviously reduced by the obtained device structure while the manufacturing cost is not increased. Compared with the power MOSFET device with the separated gate enhancement structure, which is proposed in China patent No. 201910191166.9 and U.S. patent No. 16/536333 of Qiao Ming, wang Zhengkang and Zhang Bo, the lower half part of the control gate electrode of the structure is narrower, so that the gate-source capacitance Cgs of the device can be greatly reduced, the improvement of the switching speed and the reduction of the switching loss of the device are facilitated, and meanwhile, the cross-sectional area of the gate current flow can be increased to a certain extent by controlling the upper half part of the gate electrode, so that the gate resistance value is reduced on the premise that the gate-source capacitance Cgs and the gate charge Qg are not degraded, and the aims of high switching speed and low switching loss are fulfilled. The adoption of the step-shaped separation gate electrode structure can further lead the electric field distribution of the drift region of the device to be more uniform, and realize the improvement of breakdown voltage BV and specific on-resistance Ron.
In order to achieve the above object, the present invention has the following technical scheme:
a method of fabricating a split gate power MOSFET device comprising the steps of:
1) Forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of the groove structures;
2) Depositing polysilicon in the trench structure so that the polysilicon fills the entire trench;
3) Etching the polysilicon deposited in the step 2), and forming a lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) Wet etching the first dielectric layer, and then depositing polysilicon in the groove structure to enable the polysilicon to fill the whole groove;
5) Etching the polysilicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) Depositing and etching back the upper part of the step-shaped separation gate in the groove of the active region to form a second dielectric layer;
7) Thermally growing or depositing an oxide layer, and then depositing silicon nitride in the trench structure to fill the entire trench of the active region;
8) Wet etching the silicon nitride deposited in the step 7), so that the upper interface is lower than the upper surface of the silicon layer of the MESA region, and the silicon nitride remained in the groove is used as a shielding layer for the etching of the next oxide layer;
9) Etching the oxide layer by a wet method, and then etching the oxide layer by a dry method, so that the etched interface is higher than the upper interface of the stepped separation gate; then wet etching to remove the residual silicon nitride in the groove;
10 A gate dielectric covering the sidewalls is formed by thermal growth in the upper half of the control gate trench in the active region; polysilicon is deposited in the active region to fill the entire trench;
11 Etching the polysilicon deposited in step 9), forming a control gate electrode in the upper half of the control gate trench of the active region;
12 Forming a second conductivity type well region on the upper surface of the epitaxial layer, and forming a first conductivity type source region in the second conductivity type well region;
13 A dielectric layer is deposited, a source electrode contact hole is etched in the source region and the separation gate leading-out region, metal is injected, and potential is led out.
Preferably, the first dielectric layer formed in step 1) of the manufacturing method is a low-k material with k less than 3.9.
Preferably, the second dielectric layer formed in step 6) of the manufacturing method is a low-k material with k less than 3.9.
Preferably, step 7) in the manufacturing method is to finally obtain the width of the vertical portion of the control gate electrode meeting the requirement by controlling the thickness of the thermally grown or deposited oxide layer.
Preferably, after wet etching the oxide layer in step 9) of the manufacturing method, the interface of the oxide layer is controlled to be lower than the upper interface of the silicon nitride remained in the groove and higher than the lower interface of the silicon nitride, and then dry etching of the oxide layer is selected.
Preferably, step 9) of the manufacturing method is implemented as follows:
9) Dry etching the oxide layer, and controlling the etched interface to keep a distance from the upper interface of the step-shaped separation gate; the remaining silicon nitride in the trench is then wet etched away.
Preferably, steps 7) to 9) of the manufacturing method use polysilicon instead of silicon nitride:
7) Thermally growing or depositing an oxide layer, and then depositing polysilicon in the trench structure to fill the entire trench of the active region;
8) Etching the polysilicon deposited in the step 7) to enable the upper interface of the polysilicon to be lower than the upper surface of the silicon layer of the MESA region, wherein the polysilicon reserved in the groove is used as a shielding layer for etching the next oxide layer;
9) Wet etching the oxide layer, and then selecting dry etching the oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
The beneficial effects of the invention are as follows: in the preparation process of the control gate electrode, in the steps 7) to 9), silicon nitride or polysilicon is used as an etching shielding layer, polysilicon is deposited and etched back after the oxide layer is etched, the lower half part of the formed control gate electrode is narrower, the overlapping area with the step-shaped separation gate electrode is smaller, and the gate-source capacitance Cgs can be greatly reduced. Meanwhile, the upper half part of the control gate electrode is obviously wider, so that the cross section area of the gate current flow is increased to a certain extent, and the gate resistance is effectively reduced. The manufacturing method is easy to implement, does not need to add an extra mask photoetching process, and meanwhile, the obtained device structure has low gate charge characteristics and low gate resistance characteristics, and achieves the aims of high switching speed and low switching loss.
Drawings
Fig. 1 is a schematic diagram of a conventional split gate power MOSFET device.
Fig. 2 is a schematic diagram of a split gate power MOSFET device obtained by using the manufacturing method proposed in embodiment 1.
Fig. 3 is a flowchart of a method for manufacturing a split gate power MOSFET device according to embodiment 1 of the present invention, which is sequentially from left to right and from top to bottom.
FIG. 4 is a partial step chart of the manufacturing method according to embodiment 2 of the present invention, which is used to replace the processes (j) - (k) in FIG. 3; the differences from the manufacturing method described in example 1 of the present invention are: the implementation mode of the step 9) selects direct dry etching of the oxide layer.
Fig. 5 is a schematic diagram of a split gate power MOSFET device obtained by using the manufacturing method proposed in embodiment 3.
Fig. 6 is a schematic diagram of a split gate power MOSFET device obtained by using the manufacturing method proposed in embodiment 4.
10 is a first conductivity type substrate, 11 is a first conductivity type epitaxial layer, 12 is a trench structure, 131 is a first dielectric layer, 132 is a second dielectric layer, 133 is a gate dielectric layer, 134 is a third dielectric layer, 14 is a sacrificial oxide layer, 15 is a shielding layer (silicon nitride or polysilicon), 16 is a split gate electrode, 17 is a control gate electrode, 18 is a second conductivity type well region, 19 is a second conductivity type heavily doped region, 20 is a first conductivity type heavily doped source region, and 21 is a metal.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Example 1
As shown in fig. 3, a method for manufacturing a split gate power MOSFET device includes the steps of:
1) Forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of the groove structures;
2) Depositing polysilicon in the trench structure so that the polysilicon fills the entire trench;
3) Etching the polysilicon deposited in the step 2), and forming a lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) Wet etching the first dielectric layer, and then depositing polysilicon in the groove structure to enable the polysilicon to fill the whole groove;
5) Etching the polysilicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) Depositing and etching back the upper part of the step-shaped separation gate in the groove of the active region to form a second dielectric layer;
7) Thermally growing or depositing an oxide layer, and then depositing silicon nitride in the trench structure to fill the entire trench of the active region;
8) Wet etching the silicon nitride deposited in the step 7), so that the upper interface is lower than the upper surface of the silicon layer of the MESA region, and the silicon nitride remained in the groove is used as a shielding layer for the etching of the next oxide layer;
9) Etching the oxide layer by a wet method, and then etching the oxide layer by a dry method, so that the etched interface is higher than the upper interface of the stepped separation gate; then wet etching to remove the residual silicon nitride in the groove;
10 A gate dielectric covering the sidewalls is formed by thermal growth in the upper half of the control gate trench in the active region; polysilicon is deposited in the active region to fill the entire trench;
11 Etching the polysilicon deposited in step 9), forming a control gate electrode in the upper half of the control gate trench of the active region;
12 Forming a second conductivity type well region on the upper surface of the epitaxial layer, and forming a first conductivity type source region in the second conductivity type well region;
13 A dielectric layer is deposited, a source electrode contact hole is etched in the source region and the separation gate leading-out region, metal is injected, and potential is led out.
Preferably, step 7) of the manufacturing method can finally obtain the width of the vertical portion of the control gate electrode meeting the requirement by controlling the thickness of the thermally grown or deposited oxide layer.
Preferably, after wet etching the oxide layer in step 9) of the manufacturing method, the interface of the oxide layer is controlled to be lower than the upper interface of the silicon nitride remained in the groove and higher than the lower interface of the silicon nitride, and then the oxide layer with a certain thickness is etched by dry etching.
Preferably, steps 7) to 9) of the manufacturing method use polysilicon instead of silicon nitride:
7) Thermally growing or depositing an oxide layer, and then depositing polysilicon in the trench structure to fill the entire trench of the active region;
8) Etching the polysilicon deposited in the step 7) to enable the upper interface of the polysilicon to be lower than the upper surface of the silicon layer of the MESA region, wherein the polysilicon reserved in the groove is used as a shielding layer for etching the next oxide layer;
9) Wet etching the oxide layer, and then selecting dry etching the oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
Example 2
As shown in fig. 4, this embodiment provides a part of the steps of a manufacturing method of a split gate power MOSFET device, which is used to replace the (j) - (k) processes in fig. 3, and the difference between the manufacturing method of this embodiment and the manufacturing method of embodiment 1 is that the following implementation manner is adopted in step 9):
9) Dry etching the oxide layer, and controlling the etched interface to keep a certain distance from the upper interface of the step-shaped separation gate; then wet etching to remove the residual silicon nitride in the groove;
example 3
As shown in fig. 5, this embodiment is different from the manufacturing method described in embodiment 1 in that: the first dielectric layer formed in the step 1) surrounding the separation gate electrode adopts a low-k material with k less than 3.9 to replace silicon dioxide, so that the source-drain capacitance can be further reduced.
Example 4
As shown in fig. 6, this embodiment is different from the manufacturing method described in embodiment 1 in that: and the second dielectric layer formed in the step 6) is made of a low-k material with k less than 3.9 instead of silicon dioxide, so that the gate-source capacitance can be further reduced.
The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made thereto by those of ordinary skill in the art without departing from the spirit of the invention and the scope of the appended claims.

Claims (7)

1. A manufacturing method of a split gate power MOSFET device is characterized by comprising the following steps:
1) Forming a series of groove structures on the epitaxial layer, and forming a first dielectric layer on the inner wall of the groove structures;
2) Depositing polysilicon in the trench structure so that the polysilicon fills the entire trench;
3) Etching the polysilicon deposited in the step 2), and forming a lower half part of a stepped separation gate electrode in a control gate groove of the active region;
4) Wet etching the first dielectric layer, and then depositing polysilicon in the groove structure to enable the polysilicon to fill the whole groove;
5) Etching the polysilicon deposited in the step 4), and forming the upper half part of the stepped separation gate electrode in the control gate groove of the active region;
6) Depositing and etching back the upper part of the step-shaped separation gate in the groove of the active region to form a second dielectric layer;
7) Thermally growing or depositing an oxide layer, and then depositing silicon nitride in the trench structure to fill the entire trench of the active region;
8) Wet etching the silicon nitride deposited in the step 7), so that the upper interface is lower than the upper surface of the silicon layer of the MESA region, and the silicon nitride remained in the groove is used as a shielding layer for the etching of the next oxide layer;
9) Etching the oxide layer by a wet method, and then etching the oxide layer by a dry method, so that the etched interface is higher than the upper interface of the stepped separation gate; then wet etching to remove the residual silicon nitride in the groove;
10 A gate dielectric covering the sidewalls is formed by thermal growth in the upper half of the control gate trench in the active region; polysilicon is deposited in the active region to fill the entire trench;
11 Etching the polysilicon deposited in step 9), forming a control gate electrode in the upper half of the control gate trench of the active region;
12 Forming a second conductivity type well region on the upper surface of the epitaxial layer, and forming a first conductivity type source region in the second conductivity type well region;
13 A dielectric layer is deposited, a source electrode contact hole is etched in the source region and the separation gate leading-out region, metal is injected, and potential is led out.
2. The method of manufacturing a split gate power MOSFET device of claim 1, wherein: the first dielectric layer formed in step 1) is a low-k material with k less than 3.9.
3. The method of manufacturing a split gate power MOSFET device of claim 1, wherein: the second dielectric layer formed in step 6) is a low-k material having a k less than 3.9.
4. The method of manufacturing a split gate power MOSFET device of claim 1, wherein: and 7) finally obtaining the width of the vertical part of the control gate electrode meeting the requirement by controlling the thickness of the thermally grown or deposited oxide layer.
5. The method of manufacturing a split gate power MOSFET device of claim 1, wherein: and 9) after wet etching the oxide layer, controlling the interface of the oxide layer to be lower than the upper interface of the silicon nitride reserved in the groove and higher than the lower interface of the silicon nitride, and then selecting dry etching the oxide layer.
6. The method of manufacturing a split gate power MOSFET device according to claim 1, wherein step 9) is implemented as follows:
9) Dry etching the oxide layer, and controlling the etched interface to keep a distance from the upper interface of the step-shaped separation gate; the remaining silicon nitride in the trench is then wet etched away.
7. The method of manufacturing a split gate power MOSFET device according to claim 1, wherein polysilicon is used instead of silicon nitride in steps 7) through 9):
7) Thermally growing or depositing an oxide layer, and then depositing polysilicon in the trench structure to fill the entire trench of the active region;
8) Etching the polysilicon deposited in the step 7) to enable the upper interface of the polysilicon to be lower than the upper surface of the silicon layer of the MESA region, wherein the polysilicon reserved in the groove is used as a shielding layer for etching the next oxide layer;
9) Wet etching the oxide layer, and then selecting dry etching the oxide layer to enable the etched interface to be higher than the upper interface of the stepped separation gate; the remaining polysilicon in the trench is then etched away.
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