CN113505063A - FPGA logic test method and device - Google Patents

FPGA logic test method and device Download PDF

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CN113505063A
CN113505063A CN202110756274.3A CN202110756274A CN113505063A CN 113505063 A CN113505063 A CN 113505063A CN 202110756274 A CN202110756274 A CN 202110756274A CN 113505063 A CN113505063 A CN 113505063A
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CN113505063B (en
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贺莹
田莉蓉
王闯
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Avic Airborne System General Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
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    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract

The invention belongs to the technical field of integrated circuits, and particularly provides a method and a device for testing FPGA (field programmable gate array) logic. The method comprises the following steps: determining the required resource storage amount required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested; if the storage capacity of the required resources is less than the residual storage capacity of the FPGA on-chip memory, determining that the storage mode is on-chip storage, otherwise, determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage; and testing the logic source code to be tested based on the embedded logic analyzer kernel, and storing the sampling data generated by the test into a corresponding memory according to the determined storage mode. The method and the device can avoid the problem of low sampling depth caused by the internal storage space during FPGA test, thereby effectively improving the sampling depth during test.

Description

FPGA logic test method and device
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method and a device for testing FPGA (field programmable gate array) logic.
Background
An FPGA (Field programmable Gate Array) is a general-purpose device, and includes a large number of basic units such as a repeated programmable logic block (CLB), an input/output unit (IOB), and a Programmable Interconnect (PI). Particularly suitable for the development of new products of integrated circuits and the production of small-batch ASIC circuits, which have been widely used in many fields along with the rapid development of the integrated circuits. With the wide application of the FPGA, the requirement for the accuracy of the FPGA is higher and higher, so the FPGA needs to be reasonably verified through testing.
Currently, there are generally two methods for FPGA logic testing: one is a method using an external oscilloscope or a logic analyzer, and the other is a method using an embedded logic analyzer. The method of using the external oscilloscope or the logic analyzer needs to route the internal signal to be tested to the pin which is not used by the FPGA and then connect the pin to the external oscilloscope or the logic analyzer for observation.
The method for using the embedded logic analyzer is based on the kernel of the embedded logic analyzer of an FPGA manufacturer, acquires the internal resources of the FPGA to realize signal sampling and storage, and transmits the captured data to a PC (personal computer) for display through a JTAG (joint test action group) interface. The method is limited by storage resources inside the FPGA, so that the sampling depth (sampling data storage amount) of the signal is limited, and the requirement of a test scene with high requirement on the number of test samples cannot be met.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides an FPGA logic test method and device, electronic equipment and a medium, and aims to solve the problem that the signal sampling depth is limited when an embedded logic analyzer is used for FPGA logic test.
In a first aspect, the present invention provides a method for testing FPGA logic, including:
determining the required resource storage amount required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;
if the required resource storage amount is less than the residual storage amount of the FPGA on-chip memory, determining that the storage mode is on-chip storage, otherwise, determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage;
and testing the logic source code to be tested based on the embedded logic analyzer kernel, and storing the sampling data generated by testing into a corresponding memory according to the determined storage mode.
According to the technical scheme, the FPGA logic test method provided by the invention determines the storage mode according to the relation between the storage capacity of the required resources and the residual storage capacity in the chip, and selects the proper storage mode to store the data under the condition that the storage capacity of the required resources is greater than the residual storage capacity in the chip, so that the sampling depth can be effectively improved, the existing resources are fully utilized, and no additional design cost is brought.
Optionally, when the storage manner is off-chip storage, the storing the sample data generated by the test into the corresponding memory according to the determined storage manner includes:
writing sampling data generated by testing into the FPGA on-chip memory;
and when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into the external memory.
Optionally, the method further comprises:
recording the writing times of writing sampling data into the FPGA on-chip memory;
and if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested.
OptionallyThe data transfer threshold is
Figure BDA0003147639070000021
And Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.
Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the storing the sampled data in the FPGA on-chip memory into the external memory includes:
and sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to C, and storing the sampling data with the data width of C in the data writing buffer area into the external memory.
Optionally, the method further comprises:
selecting a partial space in the external memory according to the demand resource storage amount, and dividing the partial space into N data blocks,
Figure BDA0003147639070000022
x is the storage amount of the required resources, R is the data width of the FPGA on-chip memory, and L is the residual data depth of the FPGA on-chip memory;
the storing the sampling data in the FPGA on-chip memory into the external memory comprises:
and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.
Optionally, after the testing of the embedded logic analyzer is completed, the method further includes:
writing the data blocks storing the sampling data in the external memory into the FPGA on-chip memory in sequence;
and after each data block is read out, writing the next data block into the on-chip memory to realize the refreshing of the on-chip memory until the data block is read out completely.
Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, writing the data blocks stored in the external memory into the FPGA on-chip memory in sequence includes:
and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area to C, and storing the data blocks with the data width of C in the data reading buffer area into the FPGA chip memory.
Optionally, the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program into the FPGA, and at this time, the FPGA configuration chip is in an idle state.
In a second aspect, the present invention provides an FPGA logic testing apparatus, including:
the memory space determining module is used for determining the required resource memory space required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;
the storage mode determining module is used for determining that the storage mode is on-chip storage if the storage capacity of the required resources is less than the residual storage capacity of the FPGA on-chip storage, or determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage;
and the test storage module is used for testing the logic source code to be tested based on the embedded logic analyzer kernel and storing the sampling data generated by the test into the corresponding memory according to the determined storage mode.
Optionally, when the storage mode is off-chip storage, the test storage module is specifically configured to:
writing sampling data generated by testing into the FPGA on-chip memory;
and when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into the external memory.
Optionally, the apparatus further comprises a counting module:
recording the writing times of writing sampling data into the FPGA on-chip memory;
and if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested.
Optionally, in the counting module, the data transfer threshold is
Figure BDA0003147639070000031
And Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.
Optionally, when the data width C of the external memory is not equal to the data width R of the FPGA on-chip memory, the test storage module is specifically configured to:
and sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to C, and storing the sampling data with the data width of C in the data writing buffer area into the external memory.
Optionally, the apparatus further includes a space selection module, specifically configured to:
selecting a partial space in the external memory according to the demand resource storage amount, and dividing the partial space into N data blocks,
Figure BDA0003147639070000041
x is the storage amount of the required resources, R is the data width of the FPGA on-chip memory, and L is the residual data depth of the FPGA on-chip memory;
the test storage module is specifically further configured to:
and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.
Optionally, the apparatus further includes a data migration module, specifically configured to:
after the embedded logic analyzer is tested, writing the data blocks storing the sampling data in the external memory into the FPGA on-chip memory in sequence;
and after each data block is read out, writing the next data block into the on-chip memory to realize the refreshing of the on-chip memory until the data block is read out completely.
Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test storage module is further configured to:
and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area to C, and storing the data blocks with the data width of C in the data reading buffer area into the FPGA chip memory.
Optionally, the external memory to which the test module is specifically applied is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program into the FPGA, and at this time, the FPGA configuration chip is in an idle state.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of any one of the methods when executing the computer program.
In a fourth aspect, an embodiment of the invention provides a computer-readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the steps of any of the methods described above.
By adopting the technical scheme, the method has the following beneficial effects:
1) according to the FPGA logic testing method, the sampling signals are stored and converted from the internal RAM to the external memory, so that the problem of insufficient sampling depth caused by limited internal storage resources of the FPGA is solved, meanwhile, no extra storage space is added, and the sampling depth of the testing is improved. Meanwhile, the embedded logic analyzer is adopted, and the method is different from an external oscilloscope or an analyzer, and all signals to be tested do not need to be led out to the FPGA pins, so that the method is not limited by the number of the spare IO pins of the FPGA.
2) According to the FPGA logic test method, data exchange can be achieved between the on-chip memory and the external memory, so that the logic test is not limited by on-chip memory resources, and the sampling depth of the FPGA logic test is improved.
3) The external memory is used for storing the logic code to be tested, wherein the external memory can be a configuration chip, the sampling depth is improved, the external memory is not additionally added, and the cost is reduced.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
Fig. 1 is a schematic view illustrating an application scenario of an FPGA logic testing method according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for testing FPGA logic according to an embodiment of the present invention;
FIG. 3 illustrates a spatial map of on-chip memory and external memory provided by an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an FPGA logic testing apparatus according to an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of an electronic device provided in an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.
When an embedded logic analyzer is used for carrying out logic test on an FPGA, the situation that the sampling depth is not high due to the fact that the data volume of a logic source code to be tested is larger than the internal storage space mismatching often occurs. When such a problem is encountered, an external memory is often added for storing the logic source code to be tested. Therefore, extra external memory cost is brought to the testing process, the logic testing time is prolonged, and the testing efficiency is reduced.
Referring to fig. 1, fig. 1 is a schematic view of an application scenario of an FPGA logic testing method according to an embodiment of the present invention, where an embedded logic analyzer kernel is set, a signal to be tested is set as a sampling signal, and a logic code to be tested is sampled. Meanwhile, the sampling signal can be written into the internal RAM for storage, and the logic analyzer can send the signal to the display through the JTAG interface for display. When the depth requirement of the sampling signal is not satisfied by the internal RAM, the internal RAM can be connected with the external memory, the sampling signal is stored by the external memory, the method has a good effect when the required storage quantity is large, but when the required storage quantity is small, the test time can be prolonged by directly storing the sampling signal by the external memory, and the problem of low test efficiency is caused. Based on the above, the logic test method is provided, the judgment is carried out according to the demand of the sampling signal, when the FPGA on-chip memory is not enough for storing the sampling signal, the data migration from the FPGA on-chip memory to an external memory is realized through the FPGA logic test device, then the data is processed in blocks and is migrated to the FPGA on-chip memory one by one, and the display of the test signal is realized.
Based on the above technical problem, the following describes an FPGA logic testing method specifically related in the embodiment of the present application, with reference to fig. 2, including:
s101, determining the required resource storage amount required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested.
Specifically, the logic source code to be tested is mainly used for performing logic test on the FPGA, in order to arrange a storage space, a required resource storage amount of the logic source code to be tested is determined first, the required resource storage amount is determined by a to-be-tested signal bandwidth and a sampling depth of the source code, and a specific calculation method is as follows:
X＝K×S，
wherein, X is the required resource storage amount, K is the to-be-tested signal bandwidth of the to-be-tested logic source code, and S is the sampling depth, i.e. the number of samples. According to the calculation method, the required resource storage capacity of the logic source code to be tested can be obtained.
S102, if the storage amount of the required resources is less than the residual storage amount of the FPGA on-chip memory, determining that the storage mode is on-chip storage, and if not, determining that the storage mode is off-chip storage; the memory corresponding to the on-chip memory is an FPGA on-chip memory, and the memory corresponding to the off-chip memory is an external memory.
In the step, due to the fact that the required resource storage amount is different from the residual storage amount in the chip in size, the storage mode of the logic source code to be tested is determined under different conditions, and the logic source code to be tested is stored according to the determined storage mode. The on-chip storage refers to storing the sampling data generated in the test process into an FPGA on-chip memory, and the off-chip storage refers to storing the sampling data generated in the test process into the FPGA on-chip memory.
S103, testing the logic source code to be tested based on the embedded logic analyzer kernel, and storing the sampling data generated by the test into a corresponding memory according to the determined storage mode.
Before testing, the embedded logic analysis kernel is firstly set, and the specific setting method is as follows:
making the trigger width equal to the bandwidth K of the logic source code to be tested; the setting of the data depth includes two cases, specifically as follows:
Figure BDA0003147639070000061
wherein D is data depth, S is sampling depth, Y is residual resource storage in the chip, X is required resource storage, K is bandwidth of the logic source code to be tested,
Figure BDA0003147639070000071
to represent
Figure BDA0003147639070000072
Rounding down to multiples of 2, the remaining cores remain unchanged.
The embedded logic analyzer kernel is arranged, the logic code signal to be tested is set as the kernel sampling signal, and the signal to be tested can be tested. The method comprises the steps of determining a storage mode of a logic source code to be tested under different conditions due to the fact that the required resource storage capacity is inconsistent with the residual storage capacity in the chip, and storing the logic source code to be tested according to the determined storage mode.
By the FPGA logic test method, the function of automatically selecting a proper storage mode based on the conditions of the required resource storage capacity and the residual storage capacity in the chip is realized, and when the logic source code to be tested does not meet the storable capacity of the chip memory, the external memory is called for storage, and idle resources of the external memory are fully utilized, so that the storable data volume of the FPGA logic test is increased, and the sampling depth can be effectively increased; and when the logic source code to be tested can meet the condition of the storage capacity of the on-chip memory, the FPGA on-chip memory is selected to store the sampling data, so that the data storage and reading efficiency is ensured. The storage mode is judged according to the required storage data volume, and under the condition that the required storage data volume is less than the residual storage volume in the FPGA chip, the storage is directly carried out through the FPGA chip memory without transferring to an external memory for storage, so that the test time is shortened.
Specifically, for the condition that the logic source code to be tested can be stored by the on-chip memory of the FPGA, the logic source code to be tested is directly stored in the on-chip memory, that is, the selected storage mode is on-chip storage. Namely, the resource storage capacity responding to the demand is smaller than the residual storage capacity in the chip, and the test logic source code is stored through the FPGA chip memory.
When the FPGA on-chip memory does not satisfy the storage requirement, the selected storage mode is off-chip storage, and at this time, the step S103 stores the sampling data generated by the test to the corresponding memory according to the determined storage mode, including: writing the sampling data generated by the test into an FPGA on-chip memory; and when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into an external memory.
The preset condition may be that the data amount of the sampling data written into the FPGA on-chip memory reaches a preset value, the preset value may be determined according to the remaining memory amount of the FPGA on-chip memory obtained in step S102, and the preset value does not exceed the remaining memory amount of the FPGA on-chip memory. The method comprises the steps that sampling data generated by testing are stored in an FPGA chip memory, and when the data volume of the sampling data in the FPGA chip memory reaches a preset value, the sampling data in the FPGA chip memory are sequentially transferred to an external memory until the testing is finished.
The FPGA on-chip memory is used as a cache region of the sampled data, under the condition that the on-chip memory is enough to store the logic source code to be tested, the sampled data is cached in the FPGA on-chip memory, the internal storage space of the FPGA is fully utilized, and then the sampled data in the FPGA on-chip memory is sequentially transferred to an external memory, so that the data storage efficiency can be improved compared with the mode of directly storing the sampled data in the external memory. When the required storage data volume of the test data is smaller than the residual storage volume of the FPGA on-chip memory, the storage time can be effectively shortened by adopting the on-chip storage mode, and the data processing flow is simplified.
In one possible implementation, the data amount of the sampled data written into the on-chip memory of the FPGA can be counted by the following method: recording the writing times of writing sampling data into the FPGA on-chip memory; and if the writing times are not less than the data transfer threshold, determining that the data volume of the sampled data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold is determined based on the required resource memory and the bandwidth of the signal to be tested.
In specific implementation, before data sampling, a proper data transfer threshold value is set according to the storage capacity of required resources and the bandwidth of a signal to be tested, the condition that data is transferred into an external memory is determined, and the FPGA on-chip memory is ensured to sufficiently buffer sampled data; and designing a write counter, counting according to the trigger clock, recording the number of the current write RAM, and reading the number of the write counter to obtain the write-in times. After data sampling is started, writing sampling data into the FPGA chip memory, increasing the numerical value of a write counter by 1, setting an external write signal WR _ ex to be effective when the count value of the write counter is larger than or equal to a data transfer threshold value, writing the sampling data in the chip memory into the external memory, resetting the numerical value of the write counter, and repeating the operations until the sampling is finished.
In one possible embodiment, the data transfer threshold is
Figure BDA0003147639070000081
Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.
In the application, the data transfer threshold is a condition for transferring data from the on-chip memory of the FPGA to the external memory, and when the on-chip data storage reaches to 2, taking n as an example
Figure BDA0003147639070000082
And starting to transfer the data stored in the on-chip memory of the FPGA to the external memory. Wherein,
Figure BDA0003147639070000083
an example of a data transfer threshold that may be implemented by the present application is not a specific limitation of the present application.
Optionally, referring to fig. 3, when the data width C of the external memory is not equal to the data width R of the FPGA chip memory, the sampling data in the FPGA chip memory is stored in the external memory, which specifically includes the following steps: and sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area into C in order to match the data width, and storing the sampling data with the data width of C in the data writing buffer area into the external memory.
In the step, in the process of storing the sampling data in the FPGA chip memory into the external memory, aiming at the condition that the data width of the FPGA chip memory is inconsistent with the data width of the external memory, in order to match the data widths of the FPGA chip memory and the external memory, the FPGA logic testing device is provided, the FPGA logic testing device can be used for exchanging control data between the external memory and the FPGA chip memory, and a testing storage module in the FPGA logic testing device can be used for reorganizing the data width during data buffering. When the data of the FPGA on-chip memory is stored into the external memory, the data width of the FPGA on-chip memory is inconsistent with that of the external memory, and the data is stored into the data writing buffer area of the test memory module to reorganize the data, so that the data width meets the data width to be stored into the FPGA on-chip memory or the external memory. When the data width is the same, the data in the FPGA on-chip memory is directly transferred to the storage space of an external memory in sequence without data buffering; and when the data widths are not consistent, performing data buffering in the data writing cache region, reorganizing the data, and organizing the data width of the data into the data width of an external memory to realize data migration. The data writing buffer area can be a storage space used by the FPGA on-chip memory as a data buffer.
The data writing buffer area and the data reading buffer area provide data buffering between the FPGA on-chip memory and the external memory, and no matter whether the data is written into the external memory from the FPGA on-chip memory or the external memory into the FPGA on-chip memory, when the data width between the data writing buffer area and the external memory is inconsistent, the data buffering is needed, the data is reorganized, and the data width of the signal is changed into the data width of the target memory.
The data in the FPGA on-chip memory can be stored in the external memory, and the sampling depth in the logic test is improved.
Optionally, after determining that the storage mode is off-chip storage, the storage space of the external memory may be divided to facilitate data storage, and the method specifically includes the following steps:
selecting partial space in the external memory according to the required resource storage amount, dividing the partial space into N data blocks, wherein,
Figure BDA0003147639070000091
x is the storage amount of required resources, R is the data width of the FPGA on-chip memory, L is the residual data depth of the FPGA on-chip memory, and R X L is equal to the residual storage amount Y of the FPGA on-chip memory; the number of data blocks depends on the amount of memory in the on-chip memory of the FPGA. After the number of the data blocks is determined, the sampled data is processed in blocks, and therefore the specific step of storing the sampled data in the FPGA on-chip memory into an external memory comprises the following steps: and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.
In specific implementation, according to the storage amount of required resources, a part of space is selected from an external memory, the part of space is divided into a plurality of data blocks, wherein the total storage amount of the data blocks is equal to the storage amount of an FPGA on-chip memory, and data of the FPGA on-chip memory are sequentially migrated to the data blocks. And the required resource storage amount is equal to the total data amount stored in the data block.
By adopting the external memory to store the logic signal to be tested, the idle space of the external memory is fully utilized, and the storage capacity of the test signal is improved, so that the depth of the sampling signal is improved, and the efficiency in logic test is accelerated.
Optionally, after the embedded logic analyzer completes the test, the FPGA logic test method according to the embodiment of the present application further includes the following steps:
the data are stored in an external memory according to blocks, and after the test is finished, in order to transfer the data to an external display for display, the data blocks which store the sampling data in the external memory are firstly written into an FPGA on-chip memory in sequence; the first data block is the first data block stored in the external memory from the data buffer of the FPGA on-chip memory. When the second data block is written into the FPGA on-chip memory, the data stored in the FPGA on-chip memory can be refreshed into the data of the second data block, the data blocks are stored into the FPGA on-chip memory one by one, and when the reading of one data block is finished, the next data block is written into the FPGA on-chip memory to refresh the FPGA on-chip memory until the reading of the data block is finished, namely when the last data block is written into the FPGA on-chip memory.
Specifically, when the storage space of the FPGA chip memory does not meet the test requirement, and after the storage space is stored by using the external memory, in order to display and observe the sampling signal, the sampling data also needs to be written into the FPGA chip memory, and is connected to the display through the JTAG interface for display, so that the external memory also needs to be written into the FPGA chip memory.
At the moment, the data of the external memory is sequentially written into the FPGA on-chip memory according to the data blocks divided when the data are written from the FPGA on-chip memory, and when the first data block is completely written into the FPGA on-chip memory, the second data block is then written into the FPGA on-chip memory to refresh the data of the FPGA on-chip memory.
When the sampling signal is stored by the external memory, in order to display the sampling signal, after the sampling signal is stored in the external memory, the sampling signal can still be written into the FPGA chip memory in sequence according to the data block format when the sampling signal is written into the external memory, but due to the size of the storable amount of the FPGA chip memory, when the sampling signal is stored in the external memory, the sampling signal can be written into the FPGA chip memory in sequence according to the data block format when the sampling signal is written into the external memory
Figure BDA0003147639070000101
In the meantime, due to the fact that the required resource storage amount is consistent with the on-chip storage amount, the on-chip memory only stores data amount of R × L size, and the data amount is a data block. Meanwhile, the data blocks can be sequentially written into the FPGA on-chip memory one by one, and by adopting the method, the sampling signal is not limited by the requirement of the data width of the FPGA on-chip memory and the external memory, and the range of the applicable external memory is expanded.
Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the data stored in the external memory still needs to be written into the FPGA on-chip memory for storage, and at this time, the specific steps of writing the data blocks stored in the external memory into the FPGA on-chip memory in sequence include: and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area into R, and storing the data blocks with the data width of R in the data reading buffer area into an FPGA on-chip memory.
Specifically, when the external memory is equal to the data width of the on-chip memory of the FPGA, the data width from the external memory to the on-chip memory of the FPGA is not required to be corrected, and the external memory is directly written into the on-chip memory of the FPGA. When the data widths are not consistent, data buffering is carried out in a data reading buffer area of a data buffer unit in the FPGA logic testing device, data are reorganized, the data width of the data is converted into the data width of an FPGA chip memory, and then data blocks of an external memory are written into the FPGA chip memory in sequence.
When the external memory stores the sampling signal, the storage data of the external memory is written into the FPGA on-chip memory to be sent to the display for displaying. In the specific signal display process, firstly, the storage data of the external memory is written into the on-chip memory according to blocks, and after the first data block is written into the on-chip memory, signal oscillography is carried out through an external display connected with JTAG; and simultaneously, gradually reading out the data of the first data block, gradually writing the second data block into the FPGA on-chip memory to refresh the data of the FPGA on-chip memory, and writing the repeated data into the on-chip memory and displaying the data by the external display until the data is displayed by the external display. The data width is adapted through reorganization by buffering in the test storage module, so that the condition of inconsistent data width is avoided, and the applicable scene of the test method is enlarged.
In a possible implementation manner, the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program into the FPGA, and at this time, the FPGA configuration chip is in an idle state.
Specifically, the external memory may be an FPGA configuration chip, and the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off. And when the FPGA is powered off, the program in the power-on process cannot be stored, and the FPGA configuration chip is used for storing the program which can be lost after the FPGA is powered off. When the FPGA is electrified again, the FPGA configuration chip can be reconfigured into FPGA hardware in a short time, after the configuration is completed, the off-chip configuration chip is in an idle state, and when an embedded logic analyzer is used for testing a logic source code to be tested, the off-chip configuration chip can be used for storing a signal to be tested, which cannot be stored by an on-chip storage resource.
Because the FPGA on-chip memory is volatile, the FPGA configuration chip can be used for storing a program of the FPGA on-chip memory after the FPGA is powered off, and when the embedded logic analyzer is used for storing after the FPGA is powered on, the idle FPGA configuration chip is used for storing a signal to be tested, so that the sampling depth of the test can be effectively improved, idle resources in the FPGA are fully utilized, an external memory does not need to be additionally arranged, and the equipment cost is reduced.
Referring to fig. 4, the FPGA logic testing apparatus 30 according to the present invention includes:
the memory space determining module 301 is configured to determine, based on a to-be-tested signal bandwidth and a sampling depth of a to-be-tested logic source code, a required resource memory space required for testing the to-be-tested logic source code;
a storage mode determining module 302, configured to determine that the storage mode is on-chip storage if the required resource storage amount is less than the remaining storage amount of the FPGA on-chip memory, and otherwise determine that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage;
and the test storage module 303 is configured to test the logic source code to be tested based on the embedded logic analyzer core, and store the sampling data generated by the test in the corresponding memory according to the determined storage mode.
Optionally, when the storage mode is off-chip storage, the test storage module 303 is specifically configured to:
writing sampling data generated by testing into the FPGA on-chip memory;
and when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into the external memory.
Optionally, the apparatus further comprises a counting module:
recording the writing times of writing sampling data into the FPGA on-chip memory;
and if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested.
Optionally, in the counting module, the data transfer threshold is
Figure BDA0003147639070000121
And Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.
Optionally, when the data width C of the external memory is not equal to the data width R of the FPGA on-chip memory, the test storage module 303 is specifically configured to:
and sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to R, and storing the sampling data with the data width of R in the data writing buffer area into the external memory.
Optionally, the apparatus further includes a space selection module, specifically configured to:
selecting a partial space in the external memory according to the demand resource storage amount, and dividing the partial space into N data blocks,
Figure BDA0003147639070000122
x is the storage amount of the required resources, R is the data width of the FPGA on-chip memory, and L is the residual data depth of the FPGA on-chip memory;
the test storage module 303 is further specifically configured to:
and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.
Optionally, after the embedded logic analyzer is tested, the apparatus further includes a data migration module, specifically configured to:
writing the data blocks storing the sampling data in the external memory into the FPGA on-chip memory in sequence;
and after each data block is read out, writing the next data block into the on-chip memory to realize the refreshing of the on-chip memory until the data block is read out completely.
Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test storage module 303 is further configured to:
and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area to C, and storing the data blocks with the data width of C in the data reading buffer area into the FPGA chip memory.
Optionally, the external memory specifically used by the test module 303 is an FPGA configuration chip, where the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program to the FPGA, and at this time, the FPGA configuration chip is in an idle state.
The FPGA logic testing device 30 provided in the embodiment of the present application and the FPGA logic testing method adopt the same inventive concept, and can obtain the same beneficial effects, which are not described herein again.
Based on the same inventive concept as the FPGA logic testing method, the embodiment of the present application further provides an electronic device 40, as shown in fig. 5, the electronic device 40 may include a processor 401 and a memory 402.
The Processor 401 may be a general-purpose Processor, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor.
Memory 402, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The Memory may include at least one type of storage medium, and may include, for example, a flash Memory, a hard disk, a multimedia card, a card-type Memory, a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Programmable Read Only Memory (PROM), a Read Only Memory (ROM), a charged Erasable Programmable Read Only Memory (EEPROM), a magnetic Memory, a magnetic disk, an optical disk, and so on. The memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 402 in the embodiments of the present application may also be circuitry or any other device capable of performing a storage function for storing program instructions and/or data.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; the computer storage media may be any available media or data storage device that can be accessed by a computer, including but not limited to: various media that can store program codes include a removable Memory device, a Random Access Memory (RAM), a magnetic Memory (e.g., a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical Memory (e.g., a CD, a DVD, a BD, an HVD, etc.), and a semiconductor Memory (e.g., a ROM, an EPROM, an EEPROM, a nonvolatile Memory (NAND FLASH), a Solid State Disk (SSD)).
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media that can store program codes include a removable Memory device, a Random Access Memory (RAM), a magnetic Memory (e.g., a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical Memory (e.g., a CD, a DVD, a BD, an HVD, etc.), and a semiconductor Memory (e.g., a ROM, an EPROM, an EEPROM, a nonvolatile Memory (NAND FLASH), a Solid State Disk (SSD)).
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.

Claims (10)

1. An FPGA logic test method is characterized by comprising the following steps:
determining the required resource storage amount required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;
if the required resource storage amount is less than the residual storage amount of the FPGA on-chip memory, determining that the storage mode is on-chip storage, otherwise, determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage;
and testing the logic source code to be tested based on the embedded logic analyzer kernel, and storing the sampling data generated by testing into a corresponding memory according to the determined storage mode.
2. The method of claim 1, wherein when the storage mode is off-chip storage, the storing the sample data generated by the test into the corresponding memory according to the determined storage mode comprises:
writing sampling data generated by testing into the FPGA on-chip memory;
and when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into the external memory.
3. The method of claim 2, further comprising:
recording the writing times of writing sampling data into the FPGA on-chip memory;
and if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested.
4. The method of claim 3, wherein the data transfer threshold is
Figure FDA0003147639060000011
And Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.
5. The method according to claim 2, wherein when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the step of storing the sampled data in the FPGA on-chip memory into the external memory comprises the following steps:
and sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to R, and storing the sampling data with the data width of R in the data writing buffer area into the external memory.
6. The method according to any one of claims 2 to 5, further comprising:
selecting a partial space in the external memory according to the demand resource storage amount, and dividing the partial space into N data blocks,
Figure FDA0003147639060000012
x is the storage amount of the required resources, R is the data width of the FPGA on-chip memory, and L is the FPGA on-chip memoryThe remaining data depth;
the storing the sampling data in the FPGA on-chip memory into the external memory comprises:
and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.
7. The method of any of claims 2 to 5, further comprising, after the embedded logic analyzer test is completed:
writing the data blocks storing the sampling data in the external memory into the FPGA on-chip memory in sequence;
and after each data block is read out, writing the next data block into the on-chip memory to realize the refreshing of the on-chip memory until the data block is read out completely.
8. The method according to claim 7, wherein when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the writing the data blocks stored in the external memory into the FPGA on-chip memory in sequence comprises:
and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area to C, and storing the data blocks with the data width of C in the data reading buffer area into the FPGA chip memory.
9. The method according to any one of claims 2 to 5, wherein the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and when the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program into the FPGA, and at this time, the FPGA configuration chip is in an idle state.
10. An FPGA logic test device, comprising:
the memory space determining module is used for determining the required resource memory space required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;
the storage mode determining module is used for determining that the storage mode is on-chip storage if the storage capacity of the required resources is less than the residual storage capacity of the FPGA on-chip storage, or determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage;
and the test storage module is used for testing the logic source code to be tested based on the embedded logic analyzer kernel and storing the sampling data generated by the test into the corresponding memory according to the determined storage mode.
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