CN112331253A - Chip testing method, terminal and storage medium - Google Patents

Chip testing method, terminal and storage medium Download PDF

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Publication number
CN112331253A
CN112331253A CN202011188415.8A CN202011188415A CN112331253A CN 112331253 A CN112331253 A CN 112331253A CN 202011188415 A CN202011188415 A CN 202011188415A CN 112331253 A CN112331253 A CN 112331253A
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test
chip
address
read
data
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CN202011188415.8A
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CN112331253B (en
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冯修圣
陈霖
刘敏
戴洋洋
陈宗廷
李斌
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Shenzhen Hongwang Microelectronics Co ltd
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Shenzhen Hongwang Microelectronics Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

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Abstract

The application is applicable to the field of computers, and provides a chip detection method, a terminal and a storage medium. The detection method of the chip comprises the following steps: acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested; writing the first test data into the chip to be tested according to the read-write mode and the test address; reading first storage data pointed by the test address in the chip to be tested according to the read-write mode; and comparing the first storage data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to a comparison result. The embodiment of the application can improve the reliability of chip testing.

Description

Chip testing method, terminal and storage medium
Technical Field
The present application belongs to the field of computers, and in particular, relates to a chip testing method, a terminal and a storage medium.
Background
The memory is a storage unit for storing programs and various data information. The testing algorithm for the memory chip is the core of the memory testing, and the existing main testing mode is March algorithm, which can detect various fault types, such as fixed-at faults (SAF), Transition Faults (TF), Coupling Faults (CF), and Addressing Faults (AF).
However, the reliability of March algorithm is low.
Disclosure of Invention
The embodiment of the application provides a chip testing method, a terminal and a storage medium, and can solve the problem that the existing chip testing method is low in reliability.
A first aspect of an embodiment of the present application provides a chip detection method, including:
acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested;
writing the first test data into the chip to be tested according to the read-write mode and the test address;
reading first storage data pointed by the test address in the chip to be tested according to the read-write mode;
and comparing the first storage data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to a comparison result.
A second aspect of the embodiments of the present application provides a chip detection apparatus, including:
the device comprises an acquisition unit, a test unit and a control unit, wherein the acquisition unit is used for acquiring first test data, a test address and a read-write mode, and the test address is a data storage address of a chip to be tested;
the writing unit is used for writing the first test data into the chip to be tested according to the reading and writing mode and the test address;
the reading unit is used for reading first storage data pointed by the test address in the chip to be tested according to the reading and writing mode;
and the test unit is used for comparing the first storage data with the first test data and determining whether the read-write of the chip to be tested is abnormal or not according to a comparison result.
A third aspect of the embodiments of the present application provides a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the method when executing the computer program.
A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the above method.
A fifth aspect of embodiments of the present application provides a computer program product, which when run on a terminal, causes the terminal to perform the steps of the method.
According to the embodiment of the application, firstly, a chip to be tested, first test data, a test address and a read-write mode are obtained. And then writing the first test data into the test address according to the read-write mode. And then, reading the first storage data stored in the test address according to the read-write mode. And comparing the first storage data with the first test data, and determining whether the reading and writing of the chip are abnormal or not according to the comparison result. The embodiment of the application considers the test data, the test address and the read-write mode to test the read-write capability of the chip. Compared with a March algorithm, the fault existing in reading and writing in the practical application process can be tested. Therefore, the method and the device can detect the fault which cannot be detected by the March algorithm, and improve the reliability of chip testing.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic implementation flow diagram of a chip detection method provided in an embodiment of the present application;
fig. 2 is a schematic flowchart of a first implementation of obtaining first test data according to an embodiment of the present disclosure;
FIG. 3 is a schematic flow chart of an implementation of a test using data with different capacities according to an embodiment of the present application;
FIG. 4 is a schematic flow chart of a second implementation of obtaining first test data according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart illustrating an implementation of parallel read/write according to an embodiment of the present application;
fig. 6 is a schematic flowchart of a chip test provided in an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a chip detection apparatus according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
The memory is a storage unit for storing programs and various data information. The testing algorithm for the memory chip is the core of the memory testing, and the existing main testing mode is the March algorithm. The basic principle of the algorithm is that a finite state machine is utilized to carry out read-write operation on all addresses one by one, the algorithm instruction is simple and only has, and the algorithm instruction comprises read-write 0, read-write 1 and change instructions. Generally, the algorithm writes "0" to each memory cell, then reads "0" and writes "1" to each memory cell, and finally reads "1" to determine whether the data stored in the memory cells are all "1". Then, each memory cell can be read and written with "1" and "0", and finally "0" is read, and whether the data stored in the memory cell are all "0" is judged.
The March algorithm is capable of detecting a variety of fault types, such as Stuck-at faults (SAF), Transition Faults (TF), Coupling Faults (CF), and Addressing Faults (AF).
The fixed fault means that the value of one memory cell is fixed at 0 or 1 and is not changed. A transition fault is a failure of a storage unit to make a 0 to 1 or 1 to 0 transition in the memory array. Coupling failures refer to short circuits and couplings between memory cells that cause a change in one memory cell necessarily resulting in a change in the state of another memory cell. An addressing failure means that the corresponding address cannot be found correctly. These faults are all the most common types of faults.
However, the reliability of March algorithm is low. Therefore, the method for testing the chip can detect the fault type which is difficult to detect by the March algorithm, and improves the reliability of chip detection.
In order to explain the technical means of the present application, the following description will be given by way of specific examples.
Fig. 1 shows a schematic implementation flow diagram of a chip testing method provided in an embodiment of the present application, where the method can be applied to a terminal and is applicable to a situation where reliability of chip detection needs to be improved.
Specifically, the chip detection method may include the following steps S101 to S104.
Step S101, obtaining first test data, a test address and a read-write mode.
The test address is a data storage address of the chip to be tested. The chip to be tested refers to a memory chip to be tested.
Generally, before the memory leaves a factory, the memory is provided for a tester to test so as to ensure that the memory flowing to the market is not easy to break down and guarantee the rights and interests of consumers. In other scenarios, the memory user may also provide the tester with the memory to perform the test in order to know or confirm whether the chip of the memory is working properly. Therefore, when a tester tests the chip of the memory, the memory chip in the memory is the chip to be tested.
In the embodiment of the application, before the test, the terminal may establish a connection with a chip to be tested, so that the terminal may perform a read-write operation on the chip to be tested, thereby completing the test on the chip to be tested. The connection establishing mode can be selected by a tester according to actual conditions. For example, a memory carrying a chip to be tested may be inserted into a Printed Circuit Board (PCB) of the terminal by an administrator.
The first test data is data written into the memory cells of the chip to be tested during the test process. The data can be provided directly by testers with abundant testing experience, or can be test data calculated by a certain random algorithm.
The test address refers to an address corresponding to a memory cell to which first test data needs to be written during a test. Similarly, the address may be provided directly by a tester with a great test experience, or may be test data calculated by a certain random algorithm.
The read/write method is a write method used when the first test data is written into the memory cell corresponding to the test address, or a read method used when the data is read from the memory cell corresponding to the test address.
In an embodiment of the application, the terminal may test the chip to be tested in consideration of three aspects, namely the first test data, the test address and the read-write mode, so as to detect a fault type caused by a difference between the test data, the test address or the read-write mode.
And step S102, writing the first test data into the chip to be tested according to the read-write mode and the test address.
In an embodiment of the application, after the first test data, the test address and the read-write mode are acquired, the terminal may generate a plurality of commands for instructing the terminal to perform a write operation, and then execute the generated commands to write the first test data into the storage unit to which the test address points according to the read-write mode.
Step S103, reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode.
The first storage data refers to data read from the memory cell to which the test address points.
In the embodiment of the present application, normally, after the first test data is written to the test address, the first storage data stored in the memory cell corresponding to the test address is the same as the first test data. Therefore, the first storage data stored in the test address can be read according to the read-write mode to judge whether the read-write of the chip is abnormal or not.
Similarly, the terminal may generate a plurality of commands for instructing the terminal to perform a data reading operation according to the test address and the read-write mode, and then execute the generated commands to read the first storage data stored in the storage unit to which the test address points according to the read-write mode.
And step S104, comparing the first storage data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result.
In an embodiment of the present application, after the first stored data is read out, the first stored data and the first test data may be compared. If the first storage data is different from the first test data, it indicates that there is some abnormality in the read-write process of the memory chip, and the abnormality may be caused by at least one of the read-write mode, the first test data, and the test address.
If the first storage data is the same as the first test data, it is indicated that no exception exists in the read-write process of the memory chip. Therefore, it can be confirmed that the performance of the memory chip is normal at least when the first test data is read from or written to the memory cell to which the test address points using the read/write method.
In some embodiments of the present application, a plurality of first test data, a plurality of test addresses, and a plurality of read-write modes are obtained, and read-write tests are performed on different test addresses with different first test data according to different read-write modes, so as to ensure reliability of chip tests.
According to the embodiment of the application, firstly, a chip to be tested, first test data, a test address and a read-write mode are obtained. And then writing the first test data into the test address according to the read-write mode. And then, reading the first storage data stored in the test address according to the read-write mode. And comparing the first storage data with the first test data, and determining whether the reading and writing of the chip are abnormal or not according to the comparison result. The embodiment of the application considers the test data, the test address and the read-write mode to test the read-write capability of the chip. Compared with a March algorithm, the fault existing in reading and writing in the practical application process can be tested. Therefore, the embodiments of the present application can detect a fault that cannot be detected by the March algorithm, for example, a fault in a read-write mode, a fault of special test data, and the like, and can improve reliability of chip testing.
In consideration of practical application, the March algorithm reads and writes all the memory units, but the chip may only use part of the memory units in the actual use process, so the March algorithm detects the states of all the memory units in use only and cannot completely simulate the states of the chip in the actual use process.
Based on this, in some embodiments of the present application, a plurality of first test data of different sizes may be determined according to chip capacity and sequentially tested.
Specifically, in some embodiments of the present application, as shown in fig. 2, the acquiring the first test data may include: step S201 to step S203.
Step S201, acquiring the total storage capacity of the chip to be tested.
The total storage capacity refers to the total storage capacity of the chip to be tested, that is, the maximum data amount that the chip to be tested can store.
In some embodiments of the present application, the terminal may determine the total storage capacity according to the specification of the chip to be tested.
Specifically, in some embodiments of the present application, the terminal may read the specification of the chip after establishing a connection with the chip to be tested. In practical application, an identification code or a description strip carrying chip information is posted on a chip after the chip is produced, so that in other embodiments of the application, the terminal can acquire the specification of the chip by reading the identification code or acquiring an image of the description strip.
After the specification of the chip is obtained, the terminal may determine the total storage capacity according to a standard provided by the solid state technology association (JEDEC), or may determine the total storage capacity according to a specification provided by a vendor that supplies the chip to be tested.
Among them, the solid state technology association is a leading standard organization of the microelectronics industry. Typically, one specification will correspond to one total storage capacity in a solid state technology association standard or vendor specification. Therefore, the terminal can determine the total storage capacity according to the specification of the chip.
Step S202, a plurality of test data volumes are determined according to the total storage capacity.
The test data volume refers to the data volume of the first test data.
In some embodiments of the present application, the total storage capacity may be multiplied by a plurality of preset ratios to obtain a plurality of test data volumes. For example, 1/4, 1/2, 3/4, respectively, of the total storage capacity is determined as a test data volume.
In other embodiments of the present application, a plurality of predetermined capacities may be predetermined, then a predetermined capacity smaller than or equal to the total storage capacity is selected from the plurality of predetermined capacities according to the total storage capacity, and each selected predetermined capacity is determined as a test data volume.
Step S203, a plurality of first test data are obtained, wherein the volumes of the first test data correspond to the volumes of the test data one to one.
In the embodiment of the present application, a plurality of first test data may be determined according to the test data volume, and the volume (i.e., the data size) of each first test data is the same as one test data volume. The specific data content of the first test data can be directly provided by a tester with abundant test experience according to the test data volume, or can be the test data calculated by a certain random algorithm. The method can also be used for intercepting a large volume of test data according to the volume of the test data to obtain first test data.
For example, if the total memory capacity of a chip to be tested is 8Gb, 1/4, 1/2, 3/4 of the total memory capacity can be respectively determined as a test data volume according to the total memory capacity, and thus, first test data of 2Gb, 4Gb and 6Gb can be respectively acquired. On this basis, a predetermined preset capacity, which may be a smaller capacity such as 4MB, may also be obtained. Therefore, one 4MB first test data, one 2Gb first test data, one 4Gb first test data, and one 6Gb first test data can be obtained finally. The chip can now be tested with these first test data.
Specifically, as shown in fig. 3, the testing of the chip may include the following steps S301 to S307.
Step S301, a second test data is selected from the plurality of first test data.
The second test data is the test data which needs to be written into the chip at present.
In some embodiments of the present application, the specific manner of screening out one second test data from the first test data is not limited. For example, any data may be selected from the first test data as the second test data, or the plurality of first test data may be sequentially determined as the second test data according to the order of the capacity size from small to large.
Step S302, a test initial address is obtained.
The test first address refers to a start position of writing the second test data. The test head address can be selected according to actual needs. For example, the first address of the entire chip may be used as the test first address, or a test first address preset by an administrator may be obtained.
And step S303, determining a test end address according to the volume of the second test data and the test head address.
The test end address refers to an end position where writing of the second test data is completed. After the data size and the test head address of the second test data are acquired, the address where writing is completed after the writing operation of the second test data is performed can be calculated according to the test head address.
Specifically, in some embodiments of the present application, the storage capacity of each memory cell in the chip to be tested, and the number of memory blocks (banks), the number of rows, and the number of columns of the chip to be tested may be obtained, and the test end address may be determined according to the volume of the second test data, the test head address, and the storage capacity.
Generally, a chip to be tested may be divided into a plurality of memory blocks, each memory block including a number of rows and a number of columns. In each memory block, one memory cell corresponds to one column of each row, and the storage capacity of each memory cell is generally the same.
The storage capacity, the number of storage blocks, the number of rows, and the number of columns of the storage unit are generally determined at the time of factory shipment, and the corresponding obtaining manner may refer to the obtaining manner of the chip specification in step S201.
For example, a 4MB of second test data is currently required to be tested. If the row address line of the chip to be tested is 15, the column address line is 10, the memory block address line is 3, namely the row number is 215Number of bars and columns 210Number of banks and memory blocks is 23And (4) respectively. The capacity of each memory cell is 32 bits. If the calculation is performed with a column as a constraint, the second test data of 4MB requires 4 MB-4096K-4194304 Byte-33554432 bit, 33554432 bit/32 bit/1024 columns-1024 rows. That is, the second test data of 4MB requires 1024 rows by 1024 columns, and if the first address is memory block 0, 0 row, 0 column, the last address is memory block 0, 1023 row, 1023 column.
And step S304, writing the second test data into the chip to be tested according to the read-write mode, the test first address and the test last address.
In some embodiments of the application, after the read-write mode, the test head address, and the test tail address are obtained, the terminal may generate a corresponding command line according to the read-write mode, the test head address, and the test tail address, and the terminal executes the command line, so as to completely write the second test data from the storage unit to which the test head address points to the storage unit to which the test tail address points according to the read-write mode.
Step S305, reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode.
Step S306, comparing the first storage data with the second test data, and determining whether the read-write of the chip is abnormal or not according to the comparison result.
The above steps S305 and S306 can refer to the descriptions of the foregoing steps S103 and S104, which are not described in detail herein.
Step S307, if there is no abnormality in the reading and writing of the chip, returning to execute the operation of screening out one second test data from the plurality of first test data until all the first test data are written into the chip to be tested.
The screened second test data is data which is not tested in the plurality of first test data.
It should be noted that, after new second test data is screened, the test head address may also be adjusted according to the actual situation. That is, when each second test data is tested, the corresponding test head addresses may be different. For example, a predetermined test start address may be associated with each second test datum. Or each test may start from the first address of the entire memory chip. Alternatively, the first address of each test may be identified as the address next to the last address of the last test.
According to the embodiment of the application, through multiple times of cycle tests, the data size corresponding to the data used in each test is equal to part or all of the total storage capacity, a process that the chip is continuously started to be started from part to all in the using process is actually simulated, and the actual situation of the chip in the actual using process is better fitted. Compared with the March algorithm which directly writes and reads all the storage units, the testing method provided by the application can test the faults which may occur in the process of partial reading and writing.
In some embodiments of the present application, the memory address of the chip to be tested includes: a storage block address, a row address, and a column address. A general test mode, such as March algorithm, is only applicable to a read/write mode for writing and reading, that is, a conventional write mode is to select a memory block, select a row, complete writing all columns of the row, and then write the next column.
However, in the practical application process, since the reading and writing of the chip are generally completed by executing the command, and the corresponding command timings are different in different reading and writing modes. For example, before selecting a memory block, an Active command needs to be executed to activate the memory block. Before switching rows, there will be a precharge command to close the current row and open a new row. Different writing schemes will therefore cause the timing of the commands to vary. In practical application, various read/write modes can occur, so for such a situation, a plurality of write modes are added in the embodiment of the present application for testing.
Specifically, in some embodiments of the present application, the number of the read/write modes is greater than 1, and the writing the first test data into the chip to be tested according to the read/write modes and the test address may include: and writing the first test data into the chip to be tested for multiple times according to each read-write mode and the test address.
The read-write modes adopted for writing the chips to be tested in each time are different. That is, in some embodiments of the present application, the test can be performed multiple times in multiple read/write modes to test the performance of the chip in different read/write modes.
In some embodiments of the present application, the data storage address of the chip to be tested includes: the storage device comprises a storage block address, a row address and a column address, wherein each read-write mode comprises a read-write sequence of the storage block address, the row address and the column address, and the read-write sequences of the read-write modes are different. Therefore, in some embodiments of the present application, the first test data may be written to the test address in the chip to be tested according to a read-write sequence included in a single read-write manner.
Specifically, the plurality of read/write modes may include at least two of the following read/write modes.
The first read-write mode is memory block-row-column. The specific operation is to select a memory block, select a row, write all columns of the row, and then change the row after all columns of the row are written. Until all the rows of the memory block are written, finally replacing the memory block until all the addresses are written. Reading is the same as writing.
The second read-write mode is memory block-column-row. The specific operation is to select a memory block, select a column, write all rows in the column, change the column, and finally change the memory block until all addresses are written. Reading is the same as writing.
The third read-write mode is row-storage block-column, a row (the row of all storage blocks) is selected first, then a storage block is selected, all columns of the storage block are written, the storage block is replaced after the column is written, and the row is replaced until all the storage blocks are written. Looping is continued until all address writes are complete. Reading is the same as writing.
The fourth read-write mode is column-memory block-row. Selecting a column (the column of all the storage blocks), selecting a storage block, reading and writing all rows of the storage block, and replacing the storage block after the rows are written until the storage blocks are all written and then replacing the columns. Looping is continued until all address writes are complete. Reading is the same as writing.
The fifth read-write mode is row-column-memory block. A row (row of all memory blocks) is selected, then all columns (columns of all memory blocks) of the row are selected, and finally a memory block is selected for writing. Looping is continued until all address writes are complete. Reading is the same as writing.
The sixth read-write mode is column-row-memory block, where a column (column of all memory blocks) is selected first, then all rows (rows of all memory blocks) of the row are selected, and finally a memory block is selected for writing. Looping is continued until all address writes are complete. Reading is the same as writing.
In order to ensure the comprehensiveness of the test, in some embodiments of the present application, six read/write modes are obtained simultaneously, and the six read/write modes are tested separately.
In other embodiments of the present application, after obtaining the multiple read-write modes, multiple write tests may be performed according to the multiple read-write modes, where the read-write modes, the first test data, and the test address of each write test are different.
And by utilizing a plurality of reading and writing modes, reading operation can be carried out once after each writing, and the storage data stored in the storage unit pointed by the corresponding test address is read. And then comparing the stored data with the first test data, if the stored data is different from the first test data, determining that the read-write of the chip to be tested is abnormal, and indicating that the chip to be tested cannot apply the current read-write mode.
In the implementation mode of the application, through the test to different read-write modes, the read-write mode that each test used is different, has simulated the different write-in modes that the chip probably appears in the use, more laminates the actual conditions of chip in the in-service use. Compared with the March algorithm or other testing algorithms which are only suitable for one read-write mode, the testing method provided by the application can test the faults caused by different command time sequences corresponding to different read-write modes in the process of utilizing different read-write modes to read and write.
In order to more fully simulate the operation condition of the chip in the actual use process, in other embodiments of the present application, a preset first random algorithm may be further obtained, and a test address may be generated according to the first random algorithm. And then, performing read-write test according to the test address.
Since the detection mode of March algorithm is generally sequential read-write, it is impossible to detect the failure simulating the read-write of random address. In practice, however, the chip may be read from or written to a particular location. Therefore, according to the embodiment of the application, a plurality of random addresses can be generated, the plurality of random addresses are read and written, whether the chip fails in the application of the random addresses is detected, and the random address failure which cannot be detected in a conventional test is made up.
The first random algorithm is used to generate a random address, and may be selected by an administrator according to actual situations, for example, the first random algorithm may be to generate three random numbers, where each random number corresponds to a memory block, a row, and a column.
The test of the random address can test whether the chip fails in the application of the random address, and the test of the random data can test whether the chip fails in the process of reading and writing the random data. Thus, in some embodiments of the present application, testing of random data may be performed. Specifically, as shown in fig. 4, the method may include: step S401 to step S404.
Step S401, the storage capacity of each storage unit in the chip to be tested is obtained.
The storage capacity of the storage unit is generally determined at the time of factory shipment, and the corresponding obtaining manner may refer to the obtaining manner of the chip specification in step S201.
Step S402, acquiring a preset second random algorithm.
In step S403, a plurality of random data is generated according to the storage capacity and a second random algorithm, and the size of each random data is equal to the storage capacity.
Wherein the second random algorithm is used for generating random data, and can be selected by the actual situation of the administrator.
In some embodiments of the present application, the terminal may directly generate numbers corresponding to the storage capacity according to the storage capacity of a single storage unit by using the second random algorithm, and concatenate the numbers to obtain random data. For example, if the storage capacity of a single memory cell is 32 bits, the second random algorithm may generate 32 numbers, each of which is one of 0 and 1, and concatenating the 32 numbers may obtain a random data.
In other embodiments of the present application, the terminal may directly generate a data with a capacity larger than the storage capacity by using the second random algorithm. Then, the terminal may intercept the data according to the storage capacity to obtain random data with a size equal to the storage capacity.
It should be noted that, in the present application, a plurality of random data may be generated, and each random data may be tested, so as to ensure the comprehensiveness of the test.
Step S404, determining first test data according to the plurality of random data.
Based on the above description, after obtaining a plurality of random data, each random data may be determined as one first test data. Then, the read-write test is respectively carried out on each first test data, and whether the read-write of a certain random data is abnormal or not can be determined when the chip is read and written.
Since the detection mode of the March algorithm and the like is generally to directly read and write 0 or 1, that is, if one memory cell can store 32 bits of data, the reading and writing are "00000000000000000000000000000000" (32 0 s) or "11111111111111111111111111111111" (32 1 s). However, in practical application, if there are both 0 and 1 in 32-bit data, it is considered whether the ratio of 0 to 1 will affect the working performance of the chip. Therefore, in the embodiment of the present application, data having the same size as the storage capacity is randomly composed by the read-write detection of the random data, and therefore, the first test data may include a plurality of 0 s and a plurality of 1 s. Through various arrangements of 0 and 1, more data presentation is increased, which is not available in normal definition data, and faults which cannot be detected by a detection mode of a March algorithm and the like can be detected.
In normal operation of a chip, the chip may store data and read data at the same time. Therefore, in some embodiments of the present application, testing of parallel reads and writes may also continue. Specifically, in some embodiments of the present application, the test address includes a read test address and a write test address.
The writing test address refers to a position where first test data needs to be written in the test process; the read test address refers to a position where data needs to be read in parallel during the test process.
Both the read test address and the write test address may be selected by an administrator. It should be noted that the read test address and the write test address are generally different, but an intersection may occur.
If the memory block, row and column corresponding to the write test address are (0, 0, 0) to (2, 2, 2), the read test address cannot be (0, 0, 0) to (2, 2, 2), but may be (1, 1, 1) to (3, 3, 3).
As shown in fig. 5, the writing the first test data into the test address according to the read/write method further includes: step S501 to step S502.
Step S501, writing the first test data into the chip to be tested according to the read-write mode and the write test address.
Step S502, in the process of writing the first test data into the chip to be tested, reading the second storage data pointed by the read test address in the chip to be tested according to the read-write mode.
The second storage data refers to data stored in the storage unit pointed by the read test address.
Correspondingly, the reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode may include: and reading the first storage data pointed by the write test address in the chip to be tested according to the read-write mode.
After the first test data is written into the write test address, the first storage data stored in the test address can be read according to the read-write mode, and the first storage data and the first test data are compared. If the first storage data is the same as the first test data, the chip can perform parallel reading and writing, that is, the second storage data is read in the process of writing the first test data, and the result of the writing operation is not affected.
For example, while writing to the memory cells corresponding to the part a test address, reading is performed to the memory cells corresponding to the part B test address. If the first storage data in the part A storage unit is read after the write operation is finished, if the first storage data is the same as the first test data, the chip can perform the read-write operation at the same time.
In the embodiment of the application, in the process of writing the first test data into the write test address, the data of the read test address is read according to the read-write mode, so that the test of parallel read-write is realized.
It should be noted that, in some embodiments of the present application, a plurality of test modes may be combined.
In order to ensure the comprehensiveness and reliability of the chip test, as shown in fig. 6, in some embodiments of the present application, after the test is performed using the March algorithm, a test of data with different capacities, a test of different read-write modes, a random address test, a random data test, and a parallel read-write test may be performed, respectively. If any one of the tests fails, the read-write of the chip can be confirmed to be abnormal. If all tests are successful, the chip can be confirmed to be abnormal.
It should be noted that the above test sequences may be exchanged, that is, the parallel read-write test may be performed first, and then the test of the March algorithm may be performed.
In the embodiment of the application, the combination test is carried out by using various test modes, so that the read-write capability of the chip can be more comprehensively known, and the chip can be conveniently marked, recovered and reworked by a tester.
It should be noted that, for simplicity of description, the foregoing method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts, as some steps may, in accordance with the present application, occur in other orders.
Fig. 7 is a schematic structural diagram of a chip detection apparatus 700 according to an embodiment of the present disclosure, where the chip detection apparatus 700 is configured on a terminal. The detection apparatus 700 of the chip may include:
an obtaining unit 701, configured to obtain first test data, a test address, and a read-write mode, where the test address is a data storage address of a chip to be tested;
a writing unit 702, configured to write the first test data into the chip to be tested according to the read-write manner and the test address;
a reading unit 703, configured to read, according to the read-write manner, first storage data pointed by the test address in the chip to be tested;
the testing unit 704 is configured to compare the first stored data with the first test data, and determine whether the read-write of the chip to be tested is abnormal according to a comparison result.
In some embodiments of the present application, the obtaining unit 701 is further specifically configured to: acquiring the total storage capacity of the chip to be tested; determining a plurality of test data volumes based on the total storage capacity; acquiring a plurality of first test data, wherein the volumes of the first test data correspond to the test data volumes one to one.
In some embodiments of the present application, the writing unit 702 is further specifically configured to: screening a second test data from a plurality of said first test data; acquiring a test initial address; determining a test end address according to the volume of the second test data and the test head address; and writing the second test data into the chip to be tested according to the read-write mode, the test initial address and the test final address. Correspondingly, the detecting device 700 of the above detecting chip further includes a circulating unit, configured to: and if the reading and writing of the chip are not abnormal, returning to execute the operation of screening out one second test data from the plurality of first test data until all the first test data are written into the chip to be tested.
In some embodiments of the present application, the writing unit 702 is further specifically configured to: acquiring the storage capacity of each storage unit in the chip to be tested, and the number of storage blocks, the number of rows and the number of columns of the chip to be tested; and determining a test end address according to the volume of the second test data, the test head address and the storage capacity.
In some embodiments of the present application, the number of the read/write modes is greater than 1, and the writing unit 702 further includes: and writing the first test data into the chip to be tested for multiple times according to the read-write modes and the test address, wherein the read-write modes adopted for writing into the chip to be tested each time are different.
In some embodiments of the present application, the data storage address of the chip to be tested includes: a storage block address, a row address, and a column address; each read-write mode comprises a read-write sequence for a storage block address, a row address and a column address, and the read-write sequences contained in each read-write mode are different; correspondingly, the writing unit 702 is further specifically configured to: and writing the first test data into the test address in the chip to be tested according to the read-write sequence contained in the read-write mode.
In some embodiments of the present application, the obtaining unit 701 is further specifically configured to: and acquiring a preset first random algorithm, and generating the test address according to the first random algorithm.
In some embodiments of the present application, the obtaining unit 701 is further specifically configured to: acquiring the storage capacity of each storage unit in the chip to be tested; acquiring a preset second random algorithm; generating a plurality of random data according to the storage capacity and the second random algorithm, wherein the size of each random data is equal to the storage capacity; and determining the first test data according to the plurality of random data.
In some embodiments of the present application, the test address includes a read test address and a write test address; the writing unit 702 is further specifically configured to: writing the first test data into the chip to be tested according to the read-write mode and the write test address; and reading second storage data pointed by the read test address in the chip to be tested according to the read-write mode in the process of writing the first test data into the chip to be tested. Accordingly, the reading unit 703 further includes: and reading first storage data pointed by the write test address in the chip to be tested according to the read-write mode.
It should be noted that, for convenience and simplicity of description, the specific working process of the chip detection apparatus 700 may refer to the corresponding process of the method described in fig. 1 to fig. 6, and is not described herein again.
Fig. 8 is a schematic diagram of a terminal according to an embodiment of the present application. The terminal 8 may include: a processor 80, a memory 81 and a computer program 82, such as a chip detection program, stored in said memory 81 and operable on said processor 80. The processor 80, when executing the computer program 82, implements the steps in the above-described embodiments of the chip detection method, such as the steps S101 to S104 shown in fig. 1. Alternatively, the processor 80, when executing the computer program 82, implements the functions of the modules/units in the above-described device embodiments, such as the functions of the units 701 to 704 shown in fig. 7.
The computer program may be divided into one or more modules/units, which are stored in the memory 81 and executed by the processor 80 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program in the terminal.
For example, the computer program may be partitioned into an acquisition unit, a writing unit, a reading unit, and a testing unit. The specific functions of each unit are as follows:
the device comprises an acquisition unit, a test unit and a control unit, wherein the acquisition unit is used for acquiring first test data, a test address and a read-write mode, and the test address is a data storage address of a chip to be tested;
the writing unit is used for writing the first test data into the chip to be tested according to the reading and writing mode and the test address;
the reading unit is used for reading first storage data pointed by the test address in the chip to be tested according to the reading and writing mode;
and the test unit is used for comparing the first storage data with the first test data and determining whether the read-write of the chip to be tested is abnormal or not according to a comparison result.
The terminal may include, but is not limited to, a processor 80, a memory 81. Those skilled in the art will appreciate that fig. 8 is merely an example of a terminal and is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or different components, e.g., the terminal may also include input-output devices, network access devices, buses, etc.
The Processor 80 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 81 may be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 81 may also be an external storage device of the terminal, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are equipped on the terminal. Further, the memory 81 may also include both an internal storage unit and an external storage device of the terminal. The memory 81 is used for storing the computer program and other programs and data required by the terminal. The memory 81 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal and method may be implemented in other ways. For example, the above-described apparatus/terminal embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer-readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (11)

1. A method for testing a chip, the method comprising:
acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested;
writing the first test data into the chip to be tested according to the read-write mode and the test address;
reading first storage data pointed by the test address in the chip to be tested according to the read-write mode;
and comparing the first storage data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to a comparison result.
2. The method for testing a chip according to claim 1, wherein the acquiring of the first test data comprises:
acquiring the total storage capacity of the chip to be tested;
determining a plurality of test data volumes based on the total storage capacity;
acquiring a plurality of first test data, wherein the volumes of the first test data correspond to the test data volumes one to one.
3. The method for testing a chip according to claim 2, wherein the writing the first test data to the chip to be tested according to the read-write method and the test address comprises:
screening a second test data from a plurality of said first test data;
acquiring a test initial address;
determining a test end address according to the volume of the second test data and the test head address;
writing the second test data into the chip to be tested according to the read-write mode, the test initial address and the test final address;
correspondingly, the chip testing method further comprises the following steps:
and if the reading and writing of the chip are not abnormal, returning to execute the operation of screening out one second test data from the plurality of first test data until all the first test data are written into the chip to be tested.
4. The method for testing a chip according to claim 3, wherein the determining a test end address based on the data size of the second test data and the test start address comprises:
acquiring the storage capacity of each storage unit in the chip to be tested, and the number of storage blocks, the number of rows and the number of columns of the chip to be tested;
and determining a test end address according to the volume of the second test data, the test head address and the storage capacity.
5. The method for testing a chip according to claim 1, wherein the number of the read/write modes is greater than 1, and the writing the first test data into the chip to be tested according to the read/write modes and the test address comprises:
and writing the first test data into the chip to be tested for multiple times according to the read-write modes and the test address, wherein the read-write modes adopted for writing into the chip to be tested each time are different.
6. The method for testing a chip of claim 5, wherein the data storage address of the chip under test comprises: a storage block address, a row address, and a column address;
each read-write mode comprises a read-write sequence for a storage block address, a row address and a column address, and the read-write sequences contained in each read-write mode are different;
correspondingly, writing the first test data into the chip to be tested for multiple times according to the single read-write mode and the test address, including:
and writing the first test data into the test address in the chip to be tested according to the read-write sequence contained in the read-write mode.
7. The method for testing a chip according to claim 1, wherein the obtaining of the test address comprises:
and acquiring a preset first random algorithm, and generating the test address according to the first random algorithm.
8. The method for testing a chip according to claim 1, wherein the acquiring of the first test data comprises:
acquiring the storage capacity of each storage unit in the chip to be tested;
acquiring a preset second random algorithm;
generating a plurality of random data according to the storage capacity and the second random algorithm, wherein the size of each random data is equal to the storage capacity;
and determining the first test data according to the plurality of random data.
9. The method for testing a chip according to claim 1, wherein the test address includes a read test address and a write test address;
the writing the first test data into the chip to be tested according to the read-write mode and the test address comprises:
writing the first test data into the chip to be tested according to the read-write mode and the write test address;
reading second storage data pointed by the read test address in the chip to be tested according to the read-write mode in the process of writing the first test data into the chip to be tested;
the reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode comprises the following steps:
and reading first storage data pointed by the write test address in the chip to be tested according to the read-write mode.
10. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 9 when executing the computer program.
11. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 9.
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