CN113497605A - Clock signal generating circuit and clock signal generating method - Google Patents
Clock signal generating circuit and clock signal generating method Download PDFInfo
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Abstract
The embodiment of the application provides a clock signal generating circuit and a clock signal generating method. The clock signal generating circuit obtains the functional clock signal and the test clock signal with different phase relations according to the clock signal through the enabling signal, so that the independent functional clock signal and the independent test clock signal with different phase relations are provided for the integrated circuit, the integrated circuit is enabled to realize the selective input of the test signal of the functional signal, an input signal logic selection module for selecting the functional signal and the test signal is prevented from being added in the integrated circuit, the transmission delay of the signal is avoided, the propagation speed of the signal from input to output is improved, and the performance of the integrated circuit is improved. In addition, because the input signal logic selection module is not required to be added, the power consumption and the logic area of the input signal logic selection module are reduced, and the overall power consumption and the occupied logic area of the integrated circuit are reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a clock signal generating circuit and a clock signal generating method.
Background
Integrated circuit testing is the process of testing an integrated circuit or module, determining or evaluating the function and performance of integrated circuit components by comparing the output response and expected output of the integrated circuit, and is an important means for verifying design, monitoring production, ensuring quality, analyzing failures and guiding applications. With the increase of the integration level of the integrated circuit, the circuit becomes more complex and the test difficulty increases. In order to improve the efficiency of the integrated circuit test, the testability design is adopted when the integrated circuit is designed, namely, the hardware logic for improving the testability of the integrated circuit is inserted into the design of the integrated circuit, so that the efficiency of the integrated circuit test is improved, and the test cost is saved. Thus, the integrated circuit can operate in a test mode and a functional mode, which requires selecting the current operating mode of the integrated circuit.
The Clock Signal (Clock Signal) is the basis of sequential logic, and is a Signal quantity with fixed period and irrelevant to operation, which is used for determining when the state in the logic unit is updated, so that the working mode of the integrated circuit can be selected by the Clock Signal. However, the current clock signal generating circuit (e.g. clock signal generator) for generating clock signals only provides a single clock signal output, and cannot meet the design requirements of the integrated circuit.
Disclosure of Invention
Embodiments of the present application provide a clock signal generation circuit and a clock signal generation method, which can obtain a functional clock signal and a test clock signal having different phase relationships.
In a first aspect, an embodiment of the present application provides a clock signal generation circuit, where the clock signal generation circuit includes a clock source and a clock signal generation sub-circuit;
the clock signal generating sub-circuit is provided with a clock signal input end, an enabling signal input end, a functional clock signal output end and a test clock signal output end; the clock source is connected with the clock signal input end; wherein the content of the first and second substances,
the clock source is used for generating a clock signal and outputting the clock signal to the clock signal input end;
the clock signal input end is used for receiving a clock signal;
the enable signal input end is used for receiving an enable signal, and the enable signal is used for enabling the clock signal generating circuit to obtain a functional clock signal and a test clock signal which have different phase relationships according to the clock signal;
the functional clock signal output end is used for outputting the functional clock signal;
and the test clock signal output end is used for outputting the test clock signal.
Optionally, when the enable signal is in the first state, the functional clock signal is an active signal, and the test clock signal is an inactive signal;
when the enable signal is in a second state, the test clock signal is an active signal, and the functional clock signal is an inactive signal.
Optionally, the clock signal generating sub-circuit further includes a clock gating module;
the clock gating module is used for controlling whether to output the functional clock signal and/or the test clock signal according to a control signal, and the control signal is used for indicating whether the clock gating module outputs the functional clock signal and/or the test clock signal.
Optionally, the clock signal generating sub-circuit further includes a control signal input terminal;
and the control signal input end is used for receiving the control signal and sending the control signal to the clock gating module.
Optionally, the clock signal generating circuit further includes a clock tree;
the clock tree is located between the clock source and the clock signal generating sub-circuit;
the clock tree is used for preprocessing the clock signal and transmitting the preprocessed clock signal to the clock signal input end.
Optionally, the clock tree comprises an inverter or a buffer.
In a second aspect, an embodiment of the present application provides a clock signal generating method, including:
acquiring a clock signal and an enable signal;
obtaining a functional clock signal and a test clock signal which are different in phase relation according to the clock signal and the enabling signal;
and respectively outputting the functional clock signal and the test clock signal.
Optionally, the obtaining a functional clock signal and a test clock signal with different phase relationships according to the clock signal and the enable signal includes:
when the enable signal is in a first state, obtaining an effective functional clock signal and an ineffective test clock signal;
and when the enable signal is in a second state, obtaining an effective test clock signal and an ineffective functional clock signal.
Optionally, before outputting the functional clock signal and the test clock signal, the method further includes:
judging whether to output the functional clock signal and the test clock signal according to a control signal, wherein the control signal is used for indicating whether the clock gating module outputs the functional clock signal and/or the test clock signal;
and outputting the functional clock signal and the test clock signal when the control signal determines to output the functional clock signal and the test clock signal.
Optionally, the method further includes: and receiving the control signal.
Optionally, before obtaining the functional clock signal and the test clock signal with different phase relationships according to the clock signal and the enable signal, the method further includes:
preprocessing the clock signal;
the obtaining a functional clock signal and a test clock signal with different phase relationships according to the clock signal and the enable signal includes:
and acquiring a functional clock signal and a test clock signal with different phase relationships according to the preprocessed clock signal and the enable signal.
Optionally, the preprocessing the clock signal includes: the clock signal is input to a clock tree.
In a third aspect, an embodiment of the present application provides an integrated circuit, including the clock signal generation circuit and the timing circuit according to any one of the first aspect; the time sequence circuit comprises a time sequence sub-circuit, wherein the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; wherein;
the functional signal input end is used for inputting functional signals to the time sequence sub-circuit;
the test signal input end is used for inputting a test signal to the sequential sub-circuit;
when the time sequence circuit works in a functional mode, the functional clock signal input end inputs an effective functional clock signal to the time sequence sub-circuit, and the test clock signal input end inputs an ineffective test clock signal to the time sequence sub-circuit so as to control the output end of the time sequence sub-circuit to output a functional signal;
when the time sequence circuit works in a test mode, the test clock signal input end inputs an effective test clock signal to the time sequence sub-circuit, and the functional clock signal input end inputs and outputs an ineffective functional clock signal to the time sequence sub-circuit so as to control the output end of the time sequence sub-circuit to output a test signal.
Optionally, the timing sub-circuit includes: the device comprises a storage module and a time sequence control module;
the time sequence control module is provided with the functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and a signal output end;
the storage module is provided with the output end and is connected with the time sequence control module;
the time sequence control module is used for storing the functional signal input by the functional signal input end to the storage module through the signal output end and outputting the functional signal through the output end when in a functional mode; and in a test mode, storing the test signal input through the test signal input end to the storage module through the signal output end, and outputting the test signal through the output end.
Optionally, the timing control module includes a first timing control unit and a second timing control unit;
the first time sequence control unit is provided with the functional signal input end, the functional clock signal input end and a functional signal output end, and the functional signal output end is connected with the storage module;
the second time sequence control unit is provided with a function test input end, a test clock signal input end and a test signal output end, and the test signal output end is connected with the storage module;
the first timing control unit is used for receiving a functional signal input through the functional signal input end, storing the functional signal into the storage module and outputting the functional signal through the output end when in a functional mode;
and the second time sequence control unit is used for receiving the test signal input by the test signal input end in the test mode, storing the test signal into the storage module and outputting the test signal by the output end.
Optionally, when the sequential circuit operates in the functional mode, a functional clock signal input through the functional clock signal input terminal and a test clock signal input through the test clock signal input terminal have different phases;
and when the sequential circuit works in a test mode, the phase of the functional clock signal input through the functional clock signal input end is different from that of the test clock signal input through the test clock signal input end.
Optionally, the functional clock signal and the test clock signal are the same clock signal; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input end has no signal input;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test clock signal to the sequential sub-circuit, and the functional clock signal input end has no signal input.
Optionally, the functional clock signal and the test clock signal are different clock signals; wherein the content of the first and second substances,
when the sequential circuit works in a functional mode, the functional clock signal input end inputs a functional clock signal to the sequential sub-circuit, and the test clock signal input through the test clock signal input end is an invalid signal;
when the sequential circuit works in a test mode, the test clock signal input end inputs a test signal to the sequential sub-circuit, and the functional clock signal input through the functional clock signal input end is an invalid signal.
Optionally, the sequential circuit further includes: the test signal generating circuit is connected with the test signal input end;
the test signal generating circuit is configured to provide the test signal to the test signal input terminal.
Optionally, the timing sub-circuit is a latch or a flip-flop.
The embodiment of the application provides a clock signal generating circuit and a clock signal generating method. The clock signal generating circuit comprises a clock source and a clock signal generating sub-circuit; the clock signal generating sub-circuit is provided with a clock signal input end, an enabling signal input end, a functional clock signal output end and a test clock signal output end; the clock source is connected with the clock signal input end. By adopting the technical scheme, the clock signal generating circuit can obtain the functional clock signal and the test clock signal with different phase relationships according to the clock signal under the control of the enable signal, so that the flexibility of the obtained clock signal is improved, and a single clock signal is not output. And when the functional clock signal and the test clock signal with different phase relations are provided for the integrated circuit with the functional signal and the test signal, the integrated circuit can realize the selective input of the test signal of the functional signal without an input signal logic selection module, thereby avoiding the transmission delay of the signal, improving the propagation speed of the signal from input to output and further improving the performance of the integrated circuit. In addition, because the input signal logic selection module is not required to be added, the power consumption and the logic area of the input signal logic selection module are reduced, and the overall power consumption and the occupied logic area of the integrated circuit are reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a block diagram of an integrated circuit designed using a design for testability approach;
fig. 2 is a schematic structural diagram of a clock signal generating circuit according to an embodiment of the present disclosure;
FIG. 3 is a waveform diagram of a clock signal generating circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a clock signal generating circuit according to another embodiment of the present disclosure;
FIG. 5 is a waveform diagram of a clock signal generating circuit according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a clock signal generating circuit according to another embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a clock signal generating circuit according to another embodiment of the present application;
FIG. 8 is a flowchart illustrating a clock signal generating method according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an integrated circuit according to an embodiment of the present application;
fig. 10 is a waveform diagram of a timing circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For example, for an integrated circuit designed using a design for testability method, a functional signal input and a test signal input are provided to test the integrated circuit. Since the integrated circuit has a function signal input and a test signal input, in the test stage, the function signal and the test signal need to be input separately, that is, the function signal and the test signal need to be input simultaneously. Therefore, it is necessary to select an input signal to be input to the integrated circuit. Thus, the input signal to the integrated circuit can be selected by the clock signal. However, since the current clock signal generating circuit can only output a single clock signal, if the clock signal is used as a signal for selecting input, it is necessary to add a logic selection module required for selecting the input signal, and the clock signal is used as an enable signal TE1 of the logic selection module to control the selection of the input signal. For example, an integrated circuit as shown in fig. 1, the input signal logic selection block is enabled by the enable signal TE1 to control whether the functional signal input or the scan signal input. However, the addition of the input signal logic selection block also increases the delay of input signal propagation, which affects the performance of the integrated circuit. That is, the single clock signal generated by the current clock signal generating circuit cannot meet the design requirement of the integrated circuit, which hinders the development of high performance of the integrated circuit.
Therefore, the clock signal generating circuit capable of generating two paths of clock signals with different phases, namely the functional clock signal and the test clock signal, corresponds the functional clock signal and the test clock signal to the functional signal and the test signal respectively, and meets the selection requirement of the functional signal and the test signal. For example, for the circuit shown in fig. 1, the functional signal input can be selected by the functional clock signal, and the test signal input can be selected by the test clock signal, without using the input signal logic selection module, and the selection input of the functional signal and the test signal is realized by two paths of independent clock signals with different phases, so that the propagation delay of the signals is reduced, and the performance of the integrated circuit is increased.
Fig. 2 is a schematic structural diagram of a clock signal generating circuit according to an embodiment of the present disclosure. As shown in fig. 2, the clock signal generating circuit includes a clock source 100 and a clock signal generating sub-circuit 200, wherein the clock signal generating sub-circuit 200 has a clock signal input terminal, an enable signal input terminal, a functional clock signal output terminal, and a test clock signal output terminal, and the clock source 100 is connected to the clock signal input terminal of the clock signal generating circuit.
And the clock signal input end is used for receiving a clock signal.
And the enable signal input end is used for receiving an enable signal, and the enable signal is used for enabling the clock signal generating circuit to obtain a functional clock signal and a test clock signal which have different phase relationships according to the clock signal.
And the functional clock signal output end is used for outputting a functional clock signal.
And the test clock signal output end is used for outputting the test clock signal.
In the embodiment shown in fig. 2, the clock signal generation circuit receives a clock signal, which may be sent by a clock source, through a clock signal input (CLK-in); the clock signal generating circuit receives an enable signal TE2 through an enable signal input Terminal (TE), and the clock signal generating circuit processes the clock signal according to the state of the enable signal to obtain a functional clock signal and a test clock signal.
As shown in fig. 3, the states of the enable signal include TE2 ═ 1 and TE2 ═ 0. As shown in fig. 3, the waveform of the clock signal input by the clock source 100 received by the clock signal generation sub-circuit 200 is shown as the waveform of the clock signal CLK in fig. 3. When TE2 is equal to 1, as shown in fig. 3, the test clock signal obtained by processing the clock signal CLK by the clock signal generation sub-circuit 200 is an active signal, the functional clock signal is an inactive signal, the functional clock signal in fig. 3 is set to 0, the active test clock signal is output through the test clock signal output terminal (Scan-CLK-out), and the inactive functional clock signal is output through the functional clock signal output terminal (Func-CLK-out).
When TE2 is equal to 0, as shown in fig. 3, the functional clock signal obtained by processing the clock signal CLK by the clock signal generation sub-circuit 200 is an active signal, the test clock signal is an inactive signal, the test clock signal in fig. 3 is set to 0, the active functional clock signal is output through the functional clock signal output terminal (Func-CLK-out), and the inactive test clock signal is output through the test clock signal output terminal (Scan-CLK-out).
The valid signal is a clock signal to which a test signal or a functional signal can be input, and for example, when the test clock signal is a valid signal, the integrated circuit inputs the test signal.
Optionally, when TE2 is equal to 1, the clock signal generating circuit may also obtain only a valid test clock signal, and output the test clock signal without obtaining a functional clock signal; when TE2 is equal to 0, the clock signal generation circuit may obtain only the valid functional clock signal and output the functional clock signal without obtaining the test clock signal.
Optionally, when TE2 is equal to 1, the clock signal generating circuit may also directly output the received clock signal through the test clock signal output terminal, and the functional clock signal output terminal has no clock signal output; when TE2 is equal to 0, the clock signal generation circuit directly outputs the received clock signal through the functional clock signal output terminal, and the test clock signal output terminal outputs no clock signal.
In the clock signal generating circuit provided by this embodiment, the clock signal generating circuit includes a clock source and a clock signal generating sub-circuit; the clock signal generating sub-circuit is provided with a clock signal input end, an enabling signal input end, a functional clock signal output end and a test clock signal output end; the clock source is connected with the clock signal input end. By adopting the technical scheme, the clock signal generating circuit can obtain the functional clock signal and the test clock signal with different phase relationships according to the clock signal under the control of the enable signal, so that the flexibility of the obtained clock signal is improved, and a single clock signal is not output. And when the functional clock signal and the test clock signal with different phase relations are provided for the integrated circuit with the functional signal and the test signal, the integrated circuit can realize the selective input of the test signal of the functional signal without an input signal logic selection module, thereby avoiding the transmission delay of the signal, improving the propagation speed of the signal from input to output and further improving the performance of the integrated circuit. In addition, because the input signal logic selection module is not required to be added, the power consumption and the logic area of the input signal logic selection module are reduced, and the overall power consumption and the occupied logic area of the integrated circuit are reduced.
Therefore, based on the embodiment shown in fig. 2 and shown in fig. 4, the clock signal generation sub-circuit further includes a clock gating module 210, and the clock gating module 210 is configured to control whether to output the functional clock signal and/or the test clock signal according to the control signal. The control signal is used to indicate whether the clock gating module 210 outputs the functional clock signal and/or the test clock signal.
In the embodiment shown in fig. 4, the clock gating module 210 is controlled by a control signal EN, and controls whether to output the functional clock signal and/or the test clock signal according to the state of the control signal EN. For example, as shown in fig. 5, when EN is 1, the clock gating module 210 turns off the outputs of the functional clock signal output terminal and the test clock signal output terminal, or makes the functional clock signal output by the functional clock signal output terminal be 1 or 0 constantly, and makes the test clock signal output by the test clock signal output terminal be 1 or 0 constantly. When EN is equal to 1, the functional clock signal output by the functional clock signal output terminal and the test clock signal output by the test clock signal output terminal may be the same or different, that is, the functional clock signal and the test clock signal are constantly 1 or 0 at the same time, or when the functional clock signal is constantly 1 (or 0), the test clock signal is constantly 0 (or 1).
When EN is 0, the clock signal generation circuit may generate the functional clock signal and the test clock signal having different phase relationships according to the state of the enable signal TE2, and output the functional clock signal and the test clock signal through the functional clock signal output terminal and the test clock signal output terminal, respectively. As shown in fig. 5, the waveform of the clock signal input from the clock source 100 received by the clock signal generation sub-circuit 200 is as shown in the waveform of the clock signal CLK in fig. 5. When EN is equal to 0 and TE2 is equal to 0, the clock signal generating sub-circuit 200 processes the clock signal CLK to obtain an effective functional clock signal, the test clock signal is an invalid signal, the test clock signal is set to 0 in fig. 5, the effective functional clock signal is output through the functional clock signal output terminal (Func-CLK-out), and the invalid test clock signal is output through the test clock signal output terminal (Scan-CLK-out).
When EN is equal to 0 and TE2 is equal to 1, the clock signal generating sub-circuit 200 processes the clock signal CLK to obtain a valid test clock signal, the functional clock signal is an invalid signal, the functional clock signal is set to 0 in fig. 5, the valid test clock signal is output through the test clock signal output terminal (Scan-CLK-out), and the invalid functional clock signal is output through the functional clock signal output terminal (Func-CLK-out).
The control signal EN may be generated internally by the clock signal generating circuit, or, referring to fig. 4, received through a control signal input terminal of the clock signal generating sub-circuit 200. In the latter implementation, after the control signal EN is received by the control signal input terminal, the control signal EN is transmitted to the clock gating module.
On the basis of fig. 2 or fig. 4, as shown in fig. 6, the clock signal generating circuit further includes a clock tree 300, wherein the clock tree 300 is located between the clock source 100 and the clock signal generating sub-circuit 200.
For the embodiment shown in fig. 5, after the clock source 100 generates the clock signal, the clock signal is preprocessed by the clock tree 300 to ensure the waveform quality of the clock signal during long-distance propagation, and the preprocessed clock signal is input to the clock signal generating sub-circuit 200 through the clock signal input terminal, so that the clock signal generating sub-circuit 200 obtains the functional clock signal and the test clock signal according to the preprocessed clock signal.
Optionally, the clock tree 300 is a mesh structure built by a buffer unit (buffer) or an even-numbered inverter (inverter), and receives a clock signal from a clock source, and the clock signal propagates through the buffer unit at one stage and finally propagates to a clock signal receiving end of the clock signal generating sub-circuit 200.
As shown in fig. 7, the clock tree 300 is constructed by 4 stages of inverters, and on the basis of fig. 7, two stages of inverters correspond to one stage of buffer unit, so that when the inverters in fig. 7 are replaced by buffer units, two stages of buffer units are corresponded. Wherein the output of each inverter is connected to a clock signal generation sub-circuit 200, as shown in fig. 7.
With respect to the clock signal generating circuit provided in any of the above embodiments, the clock signal generating method is as shown in fig. 8, and the method includes the steps of:
s101, acquiring a clock signal and an enabling signal.
Specifically, the clock signal may be obtained by a clock source, and the enable signal TE2 includes two states, so that the clock signal generating sub-circuit 310 obtains two paths of independent functional clock signals and test clock signals with different phases according to different states of the enable signal TE 2.
And S102, acquiring a functional clock signal and a test clock signal which are different in phase relation according to the clock signal and the enable signal.
Specifically, the enable signal TE2 includes two states, i.e., TE2 ═ 1 and TE2 ═ 0, when TE2 ═ 1, a valid test clock signal is obtained by the clock signal, and the functional clock signal is an invalid signal; when TE2 is equal to 0, the active functional clock signal is obtained and the test clock signal is an inactive signal. Wherein, since the valid test clock signal and the valid functional clock signal are obtained in two states of the enable signal TE2, respectively, the valid test clock signal and the valid functional clock signal are independent of each other and have different phases.
And S103, respectively outputting a functional clock signal and a test clock signal.
Specifically, TE2 obtains a valid test clock signal and an invalid functional clock signal, and then outputs the test clock signal through the test clock signal output terminal, and outputs the functional clock signal through the functional clock signal output terminal, or directly does not output the invalid functional clock signal. After TE2 obtains the valid functional clock signal and the invalid test clock signal, the functional clock signal is outputted through the functional clock signal output terminal, the test clock signal is outputted through the test clock signal output terminal or the invalid test clock signal is not outputted directly
In this embodiment, when the enable signal is in two different states, two independent clock signals with different phases are obtained according to the clock signal by using the enable signal, that is, when the enable signal is in one state, an effective test clock signal is obtained, and when the enable signal is in another state, an effective functional clock signal is obtained, so that two independent clock signals with different phases are output, and thus, a circuit receiving the two independent clock signals with different phases can work in two working modes (that is, in two states).
Optionally, the clock signal generating circuit does not output the functional clock signal and the test clock signal in real time, and in order to reduce the functional consumption of the clock signal generating circuit, a clock gating module is arranged in the clock signal generating circuit, and the clock gating module can control the functional clock signal and the test clock signal according to whether the output signal is controlled. Therefore, before S103, the clock signal generation control method further includes:
and judging whether to output the functional clock signal and the test clock signal according to the control signal, and outputting the functional clock signal and the test clock signal when the control signal determines to output the functional clock signal and the test clock signal.
Specifically, the control signal EN may be generated inside the clock signal generating circuit or may be input externally. For example, as shown in fig. 5, when the control signal EN is in the first state (EN ═ 1), the clock signal generation circuit can output any one of the valid test-time signal and the functional clock signal, and when the control signal EN is in the second state (EN ═ 0), the clock signal stops inverting, and the clock signal generation circuit cannot output the valid test-time signal and the functional clock signal, thereby reducing the power consumption of the clock propagation path. Moreover, if the generated valid test-time signal and functional clock signal are output to the integrated circuit, the integrated circuit will stop working when the integrated circuit does not have the valid test-time signal or functional clock signal, thus reducing the power consumption of the integrated circuit.
The waveform of the clock signal outputted by the clock source 100 is susceptible to influence during the transmission process, so as to influence the quality of the clock signal received at the clock signal input terminal, therefore, before S102, the clock signal generation control method further includes:
the clock signal is pre-processed. Correspondingly, the functional clock signal and the test clock signal with different phase relationships are obtained according to the preprocessed clock signal and the preprocessed enable signal.
Specifically, as shown in fig. 6, a clock tree 300 may be disposed between the clock source 100 and the clock signal generating sub-circuit 200, and the clock tree 300 is used to process the clock signal output by the clock source 100 to obtain a processed clock signal, so as to ensure the waveform quality of the clock signal during long-distance propagation, so that the clock signal generating sub-circuit 200 obtains the functional clock signal and the test clock signal with different phase relationships under the control of the enable signal TE2 according to the processed clock signal.
Fig. 9 is a schematic structural diagram of an integrated circuit according to an embodiment of the present application. As shown in fig. 9, the integrated circuit includes a timing circuit 1000 and a clock signal generation circuit 2000. In the embodiment of the present application, the structure of the timing circuit 1000 is not limited, and the timing circuit 1000 is, for example, as shown in fig. 9, and has a functional signal input terminal (Func-in), a test signal input terminal (Scan-in), a functional clock signal input terminal (Func-CLK-in), a test clock signal input terminal (Scan-CLK-in), and an output terminal.
The clock signal generating circuit 2000 is a clock signal generating circuit described in any one of fig. 2 to 8 of the present application. The clock signal generation circuit 2000 shown in fig. 9 is a configuration of the clock signal generation circuit shown in fig. 2.
As shown in fig. 9, the test clock signal output terminal (Scan-CLK-out) of the clock signal generating sub-circuit 200 is connected to the test clock signal input terminal (Scan-CLK-in) of the timing circuit, and the functional clock signal output terminal (Func-CLK-out) is connected to the functional clock signal input terminal (Func-CLK-in), so that the test clock signal (Scan-CLK) generated by the clock signal generating circuit is supplied to the timing circuit, and the functional clock signal (Func-CLK) is supplied to the timing circuit, so that the timing circuit selectively inputs the test signal and the functional signal according to the test clock signal and the functional clock signal. And an input signal logic selection module is not required to be added, so that the power consumption consumed by the input signal logic selection module added in the sequential circuit and the area of the sequential circuit can be saved, and the performance of the sequential circuit is improved.
Fig. 10 shows a waveform diagram of the sequential circuit 1000. As shown in fig. 10, when the functional clock signal provided by the clock signal generating circuit 2000 is an active signal and the test clock signal is an inactive signal, the timing circuit operates in a functional mode, such as the first stage of fig. 10. In the first phase, the functional clock signal is a valid clock signal, and the test clock signal sets 0, thereby inputting the functional signal. When the rising edge of the functional clock signal arrives, the timing sub-circuit 1100 receives the functional signal through the functional signal input terminal and outputs it through the output terminal. If the functional signal changes, the output terminal of the timing sub-circuit 1100 outputs the changed functional signal when the rising edge of the first functional clock signal after the change of the functional signal arrives. Therefore, the waveform of the signal output from the output terminal of the sequential sub-circuit 1100 corresponds to the waveform of the functional signal.
When the test clock signal provided by the clock signal generating circuit 2000 is an active signal and the functional clock signal is an inactive signal, the timing circuit operates in a test mode, such as the second stage of fig. 10. In the second phase, the test clock signal is a valid clock signal, and the functional clock signal is set to 0, thereby inputting the test signal. When the rising edge of the test clock signal arrives, the timing sub-circuit 1100 receives the functional signal through the test signal input terminal and outputs it through the output terminal. If the test signal changes, the output end of the timing sub-circuit 1100 outputs the changed test signal when the rising edge of the first test clock signal after the change of the test signal arrives. Therefore, the waveform of the signal output from the output terminal of the timing sub-circuit 1100 corresponds to the waveform of the test signal.
Therefore, the sequential circuit 1000 implements separate sampling of the functional signal and the test signal by the phase difference between the functional clock signal and the test clock signal provided by the clock signal generating circuit 2000, that is, when the functional signal is sampled, the test signal cannot be sampled; while the test signal is being sampled, the functional signal cannot be sampled. Therefore, an input signal logic selection module does not need to be added in the sequential circuit, so that the propagation delay of the input signal is reduced, the propagation speed of the signal from input to output is improved, and the performance of the sequential circuit is improved.
As shown in fig. 9, the clock signal generation circuit may input the test clock signal and the functional clock signal to a plurality of sequential circuits, and the plurality of sequential circuits do not affect each other.
It should be noted that the clock signal generation circuit shown in any embodiment of the present application may also provide clock signals for other circuits that need two clock signals with different phases, which is not limited in the present application.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (12)
1. A clock signal generation circuit, wherein the clock signal generation circuit includes a clock source and a clock signal generation sub-circuit;
the clock signal generating sub-circuit is provided with a clock signal input end, an enabling signal input end, a functional clock signal output end and a test clock signal output end; the clock source is connected with the clock signal input end; wherein the content of the first and second substances,
the clock source is used for generating a clock signal and outputting the clock signal to the clock signal input end;
the clock signal input end is used for receiving a clock signal;
the enable signal input end is used for receiving an enable signal, and the enable signal is used for enabling the clock signal generating circuit to obtain a functional clock signal and a test clock signal which have different phase relationships according to the clock signal;
the functional clock signal output end is used for outputting the functional clock signal;
and the test clock signal output end is used for outputting the test clock signal.
2. The clock signal generation circuit of claim 1, wherein when the enable signal is in a first state, the functional clock signal is an active signal and the test clock signal is an inactive signal;
when the enable signal is in a second state, the test clock signal is an active signal, and the functional clock signal is an inactive signal.
3. The clock signal generation circuit of claim 1 or 2, wherein the clock signal generation sub-circuit further comprises a clock gating module;
the clock gating module is used for controlling whether to output the functional clock signal and/or the test clock signal according to a control signal, and the control signal is used for indicating whether the clock gating module outputs the functional clock signal and the test clock signal.
4. The clock signal generation circuit of claim 3, wherein the clock signal generation sub-circuit further comprises a control signal input;
and the control signal input end is used for receiving the control signal and sending the control signal to the clock gating module.
5. The clock signal generation circuit according to claim 1 or 2, wherein the clock signal generation circuit further comprises a clock tree;
the clock tree is located between the clock source and the clock signal generating sub-circuit;
the clock tree is used for preprocessing the clock signal and transmitting the preprocessed clock signal to the clock signal input end.
6. The clock signal generation circuit of claim 5, wherein the clock tree comprises an inverter or a buffer.
7. A clock signal generation method, comprising:
acquiring a clock signal and an enable signal;
obtaining a functional clock signal and a test clock signal which are different in phase relation according to the clock signal and the enabling signal;
and respectively outputting the functional clock signal and the test clock signal.
8. The method of claim 7, wherein obtaining the functional clock signal and the test clock signal with different phase relationships according to the clock signal and the enable signal comprises:
when the enable signal is in a first state, obtaining an effective functional clock signal and an ineffective test clock signal;
and when the enable signal is in a second state, obtaining an effective test clock signal and an ineffective functional clock signal.
9. The method of claim 7 or 8, wherein prior to outputting the functional clock signal and the test clock signal, further comprising:
judging whether to output the functional clock signal and the test clock signal or not according to a control signal, wherein the control signal is used for indicating whether the clock gating module outputs the functional clock signal and/or the test clock signal or not;
and outputting the functional clock signal and the test clock signal when the control signal determines to output the functional clock signal and the test clock signal.
10. The method according to claim 7 or 8, wherein before obtaining the functional clock signal and the test clock signal with different phase relationships according to the clock signal and the enable signal, further comprising:
preprocessing the clock signal;
the obtaining a functional clock signal and a test clock signal with different phase relationships according to the clock signal and the enable signal includes:
and acquiring a functional clock signal and a test clock signal with different phase relationships according to the preprocessed clock signal and the enable signal.
11. An integrated circuit comprising the clock signal generation circuit and the timing circuit of any one of claims 1 to 6; the time sequence circuit comprises a time sequence sub-circuit, wherein the time sequence sub-circuit is provided with a functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and an output end; wherein;
the functional signal input end is used for inputting functional signals to the time sequence sub-circuit;
the test signal input end is used for inputting a test signal to the sequential sub-circuit;
when the time sequence circuit works in a functional mode, the functional clock signal input end inputs an effective functional clock signal to the time sequence sub-circuit, and the test clock signal input end inputs an ineffective test clock signal to the time sequence sub-circuit so as to control the output end of the time sequence sub-circuit to output a functional signal;
when the time sequence circuit works in a test mode, the test clock signal input end inputs an effective test clock signal to the time sequence sub-circuit, and the functional clock signal input end inputs and outputs an ineffective functional clock signal to the time sequence sub-circuit so as to control the output end of the time sequence sub-circuit to output a test signal.
12. The integrated circuit of claim 11, wherein the timing subcircuit comprises: the device comprises a storage module and a time sequence control module;
the time sequence control module is provided with the functional signal input end, a test signal input end, a functional clock signal input end, a test clock signal input end and a signal output end;
the storage module is connected with the time sequence control module and is provided with the output end;
the time sequence control module is used for storing the functional signal input by the functional signal input end to the storage module through the signal output end and outputting the functional signal through the output end when in a functional mode; and in a test mode, storing the test signal input through the test signal input end to the storage module through the signal output end, and outputting the test signal through the output end.
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