CN113472323A - D flip-flop circuit with strong latch structure - Google Patents
D flip-flop circuit with strong latch structure Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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- H03K3/3562—Bistable circuits of the master-slave type
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- H—ELECTRICITY
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Abstract
The invention discloses a D trigger circuit with a strong latch structure, which comprises four logic input inverters, a strong latch circuit and two transmission gates which are sequentially connected, wherein the strong latch circuit comprises two NMOS transistors and four PMOS transistors, the transistors at the left part are sequentially connected in series, the transistors at the right part are also sequentially connected in series, and the two side parts form the strong latch structure; the grid electrode of the PMOS transistor PM6 is connected with the node Q, and the grid electrode of the PMOS transistor PM8 is connected with the node Q, so that a negative feedback loop is formed; the strong latch circuit receives square wave signals given by four logic input inverters and stores the square wave signals at Q and Q non-nodes, and current of a left side or a right side part can be reduced to flow into GND from VDD every time conversion is carried out, so that dynamic leakage is greatly reduced. The circuit solves the problems of leakage power consumption and large short circuit power consumption in the signal turning process of the traditional latch, and reduces the power consumption of the whole chip design.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a D flip-flop circuit with a strong latch structure.
Background
The D flip-flop is widely applied to Very Large Scale Integration (VLSI) circuits, and improving the performance of the D flip-flop is one of the most important tasks for enhancing the performance of the whole VLSI circuit. As an important application field of emerging information industry, trillion-level markets of the Internet of things are gradually formed, and devices and nodes in a trillion level can realize the interconnection and intelligent association of everything through the technology of the Internet of things. The nodes of the internet of things (such as wearable equipment, intelligent home nodes, wireless sensor nodes and environment monitoring nodes) need to continuously work for years or even more than ten years under the condition that the micro battery supplies power, so that harsh low-power consumption requirements are provided for the chip, and the D trigger is an important part in chip design, so that the realization of the D trigger with ultralow power consumption and quick response has very important significance for reducing the power consumption of the whole chip design.
The traditional D flip-flop topology is composed of an input inverter, two half-latches (a master latch and a slave latch), and an output inverter. Because of the strong competing current between the pull-up network and the pull-down network with complementary half latch structures, especially when VDDL is located in the sub-threshold region, there are papers and experiments to show that converting a signal from the sub-threshold voltage to a voltage higher than the threshold voltage requires amplifying the sizes of two NMOS transistors by several orders of magnitude to overcome the strength of the pull-up network, resulting in additional consumption of area, which is unrealistic and unacceptable; meanwhile, due to the half-latch, in the process of conversion, the PMOS and the NMOS are turned on simultaneously, which leads to increase of dynamic power consumption, and due to the two half-latches, the rate of the D flip-flop is also slowed down, which also causes additional consumption of area.
Disclosure of Invention
The invention aims to provide a D trigger circuit with a strong latch structure, which adopts a Dynamic Leakage Suppression (DLS) strong latch structure to latch the circuit, reduces the area consumption and the power consumption of each conversion, and improves the response speed, thereby reducing the power consumption of the whole chip design.
The purpose of the invention is realized by the following technical scheme:
a D flip-flop circuit with a strong latch structure comprises four logic input inverters, a strong latch circuit and two transmission gates which are connected in sequence, wherein:
the first logic input inverter is composed of an NMOS transistor NM0, a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of PM0 and the drain of NM0 are connected to each other as an output signal, and the gate of PM0 and the gate of NM0 are connected to each other as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1, a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected to the power supply VDD, the source of the NMOS transistor NM1 is connected to GND, the drain of PM1 and the drain of NM1 are connected to each other as an output signal, and the gate of PM1 and the gate of NM1 are connected to each other as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4, a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of PM4 and the drain of NM4 are connected to each other as an output signal, and the gate of PM4 and the gate of NM4 are connected to each other as an input signal;
the fourth logic input inverter is composed of one NMOS transistor NM5, one PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected to the power supply VDD, the source of the NMOS transistor NM5 is connected to GND, the drain of PM5 and the drain of NM5 are connected to each other as an output signal, and the gate of PM5 and the gate of NM5 are connected to each other as an input signal;
and the four logic input inverters are all connected with the drain electrode of the NMOS through the PMOS drain electrode;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, two side parts form a strong latch structure, only one tube is conducted when an NMOS transistor NM6 and a PMOS transistor PM7 of the left part change every time, and only one tube is conducted when an NMOS transistor NM7 and a PMOS transistor PM9 of the right part change every time;
the grid electrode of the PMOS transistor PM6 is connected with the node Q, and the grid electrode of the PMOS transistor PM8 is connected with the node Q, so that a negative feedback loop is formed;
the strong latch circuit receives square wave signals input by four logic input inverters and stores the square wave signals in Q and Q non-nodes, the transistors are used for being cut off excessively in the conversion process, and the current of the left side or the right side can be reduced to flow into GND from VDD in each conversion process, so that dynamic leakage is greatly reduced, and power consumption is reduced;
a first transmission gate, which is composed of a PMOS transistor PM2 and an NMOS transistor NM2, is located between the first logic input inverter and the third logic input inverter as a control signal of a clock CLK, and allows a high level of the first logic input inverter to be input to the third logic input inverter when CLK is always high, and closes the first transmission gate not to allow a signal transmission between the first logic input inverter and the third logic input inverter when CLK is low;
and a second transmission gate, which is composed of a PMOS transistor PM3 and an NMOS transistor NM3, is provided between the second logic input inverter and the fourth logic input inverter as a control signal of the clock CLK, and allows the high level of the second logic input inverter to be input to the fourth logic input inverter when CLK is always high, and closes the second transmission gate to prevent signal transmission between the second logic input inverter and the fourth logic input inverter when CLK is low.
According to the technical scheme provided by the invention, the circuit solves the problems of high leakage power consumption and high short circuit power consumption in the signal turning process of the traditional latch, and adopts a dynamic leakage inhibition strong latch structure to latch the circuit, so that the area consumption and the power consumption of each conversion are reduced, the response speed is improved, and the power consumption of the whole chip design is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a D flip-flop circuit with a strong latch structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a prior art D flip-flop counter circuit;
FIG. 3 is a simulation diagram of a D flip-flop and a comparison circuit of a prior art D flip-flop when input signals D and CLK change simultaneously according to an embodiment of the present invention;
fig. 4 is a simulation diagram of a comparison circuit of a D flip-flop and a prior art D flip-flop provided in an embodiment of the present invention when the input signals D and CLK do not change simultaneously.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, not all embodiments, and this does not limit the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of a circuit structure of a D flip-flop with a strong latch structure according to an embodiment of the present invention, where the circuit includes four logic input inverters, a strong latch circuit, and two transmission gates, which are connected in sequence, where:
the first logic input inverter is composed of an NMOS transistor NM0, a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of PM0 and the drain of NM0 are connected to each other as an output signal, and the gate of PM0 and the gate of NM0 are connected to each other as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1, a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected to the power supply VDD, the source of the NMOS transistor NM1 is connected to GND, the drain of PM1 and the drain of NM1 are connected to each other as an output signal, and the gate of PM1 and the gate of NM1 are connected to each other as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4, a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of PM4 and the drain of NM4 are connected to each other as an output signal, and the gate of PM4 and the gate of NM4 are connected to each other as an input signal;
the fourth logic input inverter is composed of one NMOS transistor NM5, one PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected to the power supply VDD, the source of the NMOS transistor NM5 is connected to GND, the drain of PM5 and the drain of NM5 are connected to each other as an output signal, and the gate of PM5 and the gate of NM5 are connected to each other as an input signal;
and the four logic input inverters are all connected with the drain electrode of the NMOS through the PMOS drain electrode;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, two side parts form a strong latch structure, only one tube is conducted when an NMOS transistor NM6 and a PMOS transistor PM7 of the left part change every time, and only one tube is conducted when an NMOS transistor NM7 and a PMOS transistor PM9 of the right part change every time;
the grid electrode of the PMOS transistor PM6 is connected with the node Q, and the grid electrode of the PMOS transistor PM8 is connected with the node Q, so that a negative feedback loop is formed;
the strong latch circuit receives square wave signals input by four logic input inverters and stores the square wave signals in Q and Q non-nodes, the transistors are used for being cut off excessively in the conversion process, and the current of the left side or the right side can be reduced to flow into GND from VDD in each conversion process, so that dynamic leakage is greatly reduced, and power consumption is reduced;
a first transmission gate, which is composed of a PMOS transistor PM2 and an NMOS transistor NM2, is located between the first logic input inverter and the third logic input inverter as a control signal of a clock CLK, and allows a high level of the first logic input inverter to be input to the third logic input inverter when CLK is always high, and closes the first transmission gate not to allow a signal transmission between the first logic input inverter and the third logic input inverter when CLK is low;
and a second transmission gate, which is composed of a PMOS transistor PM3 and an NMOS transistor NM3, is provided between the second logic input inverter and the fourth logic input inverter as a control signal of the clock CLK, and allows the high level of the second logic input inverter to be input to the fourth logic input inverter when CLK is always high, and closes the second transmission gate to prevent signal transmission between the second logic input inverter and the fourth logic input inverter when CLK is low.
In a specific implementation, referring to fig. 1, the connection relationship inside the strong latch circuit is specifically:
the source of the PMOS transistor PM7 is connected with the power supply VDD, and the drain of the PMOS transistor PM7 is connected with the source of the PMOS transistor PM 6;
the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to GND, and the gate of the NMOS transistor NM6 and the gate of the PMOS transistor PM7 are connected to each other as an input port for the output of the third logic input inverter;
the drain of the PMOS transistor PM8 and the drain of the NMOS transistor NM7 are connected to the Q point, and the gate of the PMOS transistor PM6 is connected to the Q point;
the substrate of the NMOS transistor NM6 is connected with GND, the substrate of the PMOS transistor PM7 is connected with a power supply VDD, and the substrate of the PMOS transistor PM6 is connected with the power supply VDD;
the source of the PMOS transistor PM9 is connected with the power supply VDD, and the drain of the PMOS transistor PM9 is connected with the source of the PMOS transistor PM 8;
the drain of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM7, the source of the NMOS transistor NM7 is connected to GND, and the gate of the NMOS transistor NM7 and the gate of the PMOS transistor PM9 are connected to each other as an input port of the fourth logic input inverter output;
the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 are connected to the Q-not point, and the gate of the PMOS transistor PM8 is connected to the Q-not point;
the substrate of the NMOS transistor NM7 is connected to GND, the substrate of the PMOS transistor PM8 is connected to the power supply VDD, and the substrate of the PMOS transistor PM8 is connected to the power supply VDD.
Referring to fig. 1, the connection relationship among the components of the first transmission door is specifically as follows:
the substrate of the NMOS transistor NM2 is connected with GND, and the substrate of the PMOS transistor PM2 is connected with a power supply VDD;
the drain of the NMOS transistor NM2 is connected as an input to the drain of the PMOS transistor PM2, while being connected to the output of the first logic input inverter;
the source of the NMOS transistor NM2 is connected as an output to the source of the PMOS transistor PM2, while being connected to the input of the third logic input inverter;
the gate of the PMOS transistor PM2 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM2 is connected to the clock CLK.
Referring to fig. 1, the connection relationship of each component of the second transmission gate specifically includes:
the substrate of the NMOS transistor NM3 is connected with GND, and the substrate of the PMOS transistor PM3 is connected with a power supply VDD;
the drain of the NMOS transistor NM3 is connected to the drain of the PMOS transistor PM3 as an input, and is also connected to a D input signal (i.e., an externally input square wave signal);
the source of the NMOS transistor NM3 is connected as an output to the source of the PMOS transistor PM3, while being connected to the input of the fourth logic input inverter;
the gate of the PMOS transistor PM3 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM3 is connected to the clock CLK.
Based on the D trigger circuit structure, the circuit principle specifically is as follows:
the input of the first logic input inverter is connected at the gates of PM0 and NM0, and the output is connected at the drains of PM0 and NM0, so that the D signal input produces the D-not signal output. The input of the second logic input inverter is connected at the gates of PM1 and NM1, and the output is connected at the drains of PM1 and NM1, so that the CLK signal input produces the CLK non-signal output. The first transfer gate dfn is input to a junction between the drain of the PMOS transistor PM2 and the drain of the NMOS transistor NM2, the source of the PMOS transistor PM2 and the source of the NMOS transistor NM2 are connected as an output, the CLK dfn is input to the gate of the PMOS transistor PM2, the CLK signal is input to the gate of the NMOS transistor NM2, the dfn is controlled by the CLK signal to control the transfer of the dfn, the input of the third logic input inverter is pulled low if the dfn is low, and the input of the third logic input inverter is pulled high if the dfn is high. The second transmission gate D signal is input to a connection between the drain of the PMOS transistor PM3 and the drain of the NMOS transistor NM3, the source of the PMOS transistor PM3 and the source of the NMOS transistor NM3 are connected as an output, the CLK non-signal is input to the gate of the PMOS transistor PM3, the CLK signal is input to the gate of the NMOS transistor NM3, and the input of the fourth logic input inverter is pulled low if D is low level and pulled high if D is high level by the transmission of the CLK signal controlling the D signal.
The third logic input inverter is that the D-not signal input is connected between the gate of the PMOS transistor PM4 and the gate of the NMOS transistor NM4, the connection of the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM4 is connected to the strong latch circuit as an output port IN; the third logic input inverter is primarily intended to increase the drive. The fourth logic input inverter is a D signal input connected between the gate of the PMOS transistor PM5 and the gate of the NMOS transistor NM5, the connection of the drain of the PMOS transistor PM5 and the drain of the NMOS transistor NM5 is connected as an output port INB to the strong latch circuit, and the fourth logic input inverter is mainly aimed at increasing the drive.
The principle of the strong latch circuit is as follows:
when the input signal IN is low and INB is high, NM6 is off, PM7 is on, NM7 is on, pulling the voltage at Q low, PM9 is off, since pulling the voltage at Q low causes PM6 to turn on, pulling the voltage at Q off high, which causes PM8 to turn off;
when the input signal IN is high and INB is low, NM7 is IN off state, PM9 is IN on state, NM6 is IN on state, PM7 is IN off state, pulling the voltage at Q off low, thus causing PM8 to be IN on state, pulling the voltage at Q high;
when the input signal IN is high and INB is high, NM6 is on, PM7 is off, NM7 is on, and PM9 is off, pulling both Q and Q-bar low, which is a zero clearing state.
When the input signal IN is low and INB is low, NM6 is off, PM7 is on, NM7 is off, PM9 is on, if Q is high, Q is not low, PM8 is on, PM6 is off, Q is high, Q is not low, if Q is low, Q is high, PM8 is off, PM6 is on, Q is low, Q is high, and this is the hold state.
Fig. 2 is a schematic diagram of a structure of a prior art D flip-flop comparison circuit, which is a DFF flip-flop formed by an RS flip-flop, and determines high level or low level of R and S by controlling conduction between a power supply VDD and a ground GND through a CLK clock, and then adjusts RB and SB signals by external input square wave D signals, and finally stores RB and SB signals by a latch, thereby completing a DFF function.
As shown in fig. 3, which is a simulation diagram of a D flip-flop and a comparison circuit of a prior art D flip-flop provided in an embodiment of the present invention when input signals D and CLK change simultaneously, Q and QB are outputs of the circuit of the embodiment of the present invention, RB and SB are outputs of the comparison circuit of the prior art, and it can be seen from fig. 3 that: the external input signals D, CLK are varied simultaneously, while Q and QB are seen to collect and hold the signal well, while RB and SB are not.
Fig. 4 is a simulation diagram of a comparison circuit of a D flip-flop and a prior art D flip-flop provided in an embodiment of the present invention when input signals D and CLK do not change simultaneously, where GND (2) is a current change situation of the circuit ground of the present invention in fig. 1, and GND (1) is a current change situation of the circuit ground of the prior art in fig. 2, and it can be seen from fig. 4 that: the external input signals D and CLK do not change simultaneously, Q and QB, RB and SB can well collect and store signals, GND (2) can well control the magnitude of current, and GND (1) cannot reduce the magnitude of current.
Table 1 below shows a comparison of power consumption data of a comparison circuit of a D flip-flop and a prior art D flip-flop provided in an embodiment of the present invention when the input signals D and CLK do not change simultaneously, where the test simulation is performed under the conditions that the VDD power supply is 1.2V, the temperature is 27 ℃, and the process corner is TT:
| voltage (V) | Temperature (C)0C) | Art corner | Average power consumption (W) | |
| The invention | 1.2 | 27 | TT | 228.498n |
| Comparison circuit | 1.2 | 27 | TT | 181.534u |
As can be seen from table 1 above: the average power consumption of the circuit of the invention is 228.498 nw; and the average power consumption of the comparison circuit in the prior art is 181.534uw, and the power consumption is nearly 794.5 times less.
It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.
In summary, in the circuit according to the embodiment of the present invention, the CLK signal controls the transmission of the D signal input, and the signal is input to the strong latch, and each side of the latch cannot be turned from VDD to GND each time, because the other side of the latch needs to be changed to be fully turned on each time the latch is turned over, the power consumption is further reduced, and because the number of latches is reduced, the response speed of the D flip-flop is increased, and the power consumption of the whole chip design is reduced.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Claims (4)
1. The D flip-flop circuit with the strong latch structure is characterized by comprising four logic input inverters, a strong latch circuit and two transmission gates which are connected in sequence, wherein:
the first logic input inverter is composed of an NMOS transistor NM0, a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of PM0 and the drain of NM0 are connected to each other as an output signal, and the gate of PM0 and the gate of NM0 are connected to each other as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1, a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected to the power supply VDD, the source of the NMOS transistor NM1 is connected to GND, the drain of PM1 and the drain of NM1 are connected to each other as an output signal, and the gate of PM1 and the gate of NM1 are connected to each other as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4, a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of PM4 and the drain of NM4 are connected to each other as an output signal, and the gate of PM4 and the gate of NM4 are connected to each other as an input signal;
the fourth logic input inverter is composed of one NMOS transistor NM5, one PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected to the power supply VDD, the source of the NMOS transistor NM5 is connected to GND, the drain of PM5 and the drain of NM5 are connected to each other as an output signal, and the gate of PM5 and the gate of NM5 are connected to each other as an input signal;
and the four logic input inverters are all connected with the drain electrode of the NMOS through the PMOS drain electrode;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, two side parts form a strong latch structure, only one tube is conducted when an NMOS transistor NM6 and a PMOS transistor PM7 of the left part change every time, and only one tube is conducted when an NMOS transistor NM7 and a PMOS transistor PM9 of the right part change every time;
the grid electrode of the PMOS transistor PM6 is connected with the node Q, and the grid electrode of the PMOS transistor PM8 is connected with the node Q, so that a negative feedback loop is formed;
the strong latch circuit receives square wave signals input by four logic input inverters and stores the square wave signals in Q and Q non-nodes, the transistors are used for being cut off excessively in the conversion process, and the current of the left side or the right side can be reduced to flow into GND from VDD in each conversion process, so that dynamic leakage is greatly reduced, and power consumption is reduced;
a first transmission gate, which is composed of a PMOS transistor PM2 and an NMOS transistor NM2, is located between the first logic input inverter and the third logic input inverter as a control signal of a clock CLK, and allows a high level of the first logic input inverter to be input to the third logic input inverter when CLK is always high, and closes the first transmission gate not to allow a signal transmission between the first logic input inverter and the third logic input inverter when CLK is low;
and a second transmission gate, which is composed of a PMOS transistor PM3 and an NMOS transistor NM3, is provided between the second logic input inverter and the fourth logic input inverter as a control signal of the clock CLK, and allows the high level of the second logic input inverter to be input to the fourth logic input inverter when CLK is always high, and closes the second transmission gate to prevent signal transmission between the second logic input inverter and the fourth logic input inverter when CLK is low.
2. The D flip-flop circuit with the strong latch structure according to claim 1, wherein the connection relationship inside the strong latch circuit is specifically as follows:
the source of the PMOS transistor PM7 is connected with the power supply VDD, and the drain of the PMOS transistor PM7 is connected with the source of the PMOS transistor PM 6;
the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to GND, and the gate of the NMOS transistor NM6 and the gate of the PMOS transistor PM7 are connected to each other as an input port for the output of the third logic input inverter;
the drain of the PMOS transistor PM8 and the drain of the NMOS transistor NM7 are connected to the Q point, and the gate of the PMOS transistor PM6 is connected to the Q point;
the substrate of the NMOS transistor NM6 is connected with GND, the substrate of the PMOS transistor PM7 is connected with a power supply VDD, and the substrate of the PMOS transistor PM6 is connected with the power supply VDD;
the source of the PMOS transistor PM9 is connected with the power supply VDD, and the drain of the PMOS transistor PM9 is connected with the source of the PMOS transistor PM 8;
the drain of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM7, the source of the NMOS transistor NM7 is connected to GND, and the gate of the NMOS transistor NM7 and the gate of the PMOS transistor PM9 are connected to each other as an input port of the fourth logic input inverter output;
the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 are connected to the Q-not point, and the gate of the PMOS transistor PM8 is connected to the Q-not point;
the substrate of the NMOS transistor NM7 is connected to GND, the substrate of the PMOS transistor PM8 is connected to the power supply VDD, and the substrate of the PMOS transistor PM8 is connected to the power supply VDD.
3. The D flip-flop circuit with a strong latch structure according to claim 1, wherein the connection relationship between the components of the first transmission gate is specifically as follows:
the substrate of the NMOS transistor NM2 is connected with GND, and the substrate of the PMOS transistor PM2 is connected with a power supply VDD;
the drain of the NMOS transistor NM2 is connected as an input to the drain of the PMOS transistor PM2, while being connected to the output of the first logic input inverter;
the source of the NMOS transistor NM2 is connected as an output to the source of the PMOS transistor PM2, while being connected to the input of the third logic input inverter;
the gate of the PMOS transistor PM2 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM2 is connected to the clock CLK.
4. The D flip-flop circuit with a strong latch structure according to claim 1, wherein a connection relationship between each component of said second transmission gate is specifically:
the substrate of the NMOS transistor NM3 is connected with GND, and the substrate of the PMOS transistor PM3 is connected with a power supply VDD;
the drain of the NMOS transistor NM3 is connected as an input to the drain of the PMOS transistor PM3, while being connected to the D input signal;
the source of the NMOS transistor NM3 is connected as an output to the source of the PMOS transistor PM3, while being connected to the input of the fourth logic input inverter;
the gate of the PMOS transistor PM3 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM3 is connected to the clock CLK.
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| CN114050807A (en) * | 2021-11-05 | 2022-02-15 | 安徽大学 | Master-slave trigger based on TFET |
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| CN113472323B (en) | 2023-06-23 |
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