CN113471288B - Fully depleted silicon-on-insulator substrate, transistor, preparation method and application thereof - Google Patents

Fully depleted silicon-on-insulator substrate, transistor, preparation method and application thereof Download PDF

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Publication number
CN113471288B
CN113471288B CN202110548134.7A CN202110548134A CN113471288B CN 113471288 B CN113471288 B CN 113471288B CN 202110548134 A CN202110548134 A CN 202110548134A CN 113471288 B CN113471288 B CN 113471288B
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silicon
layer
silicon oxide
lines
top layer
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CN113471288A (en
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亨利·H·阿达姆松
王桂磊
戚璇
王云
叶甜春
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Guangdong Greater Bay Area Institute of Integrated Circuit and System
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

The invention relates to a fully-depleted silicon-on-insulator substrate, a transistor, a preparation method and application thereof. A method for preparing a fully depleted silicon-on-insulator substrate: forming a silicon oxide layer on the backing silicon layer; photoetching and etching are carried out to enable the silicon oxide to form a plurality of grooves, the grooves penetrate through the silicon oxide layer and penetrate into the back silicon layer, so that the surface of the back silicon layer is divided into a plurality of silicon lines, and the silicon oxide layer is divided into a plurality of silicon oxide lines; forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide line; thinning the top silicon layer; coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the interval areas of the adjacent silicon oxide lines; oxygen injection is carried out; and then annealing to form a silicon oxide isolation layer. The substrate manufactured by the invention can reduce parasitic capacitance and improve the running speed; the leakage can be reduced, and the power consumption is lower; the latch-up effect can be eliminated; the substrate pulse current interference can be restrained; while introducing strain.

Description

Fully depleted silicon-on-insulator substrate, transistor, preparation method and application thereof
Technical Field
The invention relates to the field of semiconductor production technology, in particular to a fully-depleted silicon-on-insulator substrate, a transistor and a preparation method thereof.
Background
The non-planar Fin FET device structure has stronger gate control capability as a core device, and has strong inhibition capability on short channel effect, but the process flow of the Fin FET device is complex; compared with the three-dimensional Fin FET process, the number of photoetching plates in the planar SOI device process is much smaller, the process is relatively easier, and the process cost is greatly reduced. However, it is still difficult to manufacture an SOI substrate with small parasitic capacitance and small leakage.
For this purpose, the present invention is proposed.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a fully-depleted silicon-on-insulator substrate, which can reduce parasitic capacitance and improve operation speed; the leakage can be reduced, and the power consumption is lower; the latch-up effect can be eliminated; the substrate pulse current interference can be restrained; while introducing strain.
In order to achieve the above object, the present invention provides the following technical solutions.
A method of preparing a fully depleted silicon-on-insulator substrate comprising:
Forming a silicon oxide layer on the backing silicon layer;
Performing photoetching and etching to enable silicon oxide to form a plurality of grooves, enabling the grooves to penetrate through the silicon oxide layer and penetrate deep into the back silicon layer, enabling the surface of the back silicon layer to be separated into a plurality of silicon lines, and enabling the silicon oxide layer to be separated into a plurality of silicon oxide lines;
forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide line;
Thinning the silicon top layer;
coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the interval areas of the adjacent silicon oxide lines;
oxygen implantation is carried out on the exposed area, and the depth of the oxygen implantation is deeper than the position of the silicon oxide line and is not higher than the top of the silicon oxide line;
and then annealing to form a silicon oxide isolation layer.
A method of fabricating a fully depleted transistor comprising:
the silicon-on-insulator substrate obtained by the preparation method is used;
and manufacturing a transistor on the silicon top layer area above the silicon oxide isolation layer.
Compared with the prior art, the invention achieves the following technical effects:
(1) Compared with a non-planar Fin FET device structure, the FDSOI (fully depleted silicon on insulator) substrate is simpler in process for manufacturing devices, and the cost is reduced;
(2) The isolation layer between the top silicon and the back silicon is manufactured through the processes of firstly forming the groove, then filling the silicon, injecting oxygen and annealing, so that the effects of reducing parasitic capacitance, improving the running speed, reducing electric leakage, eliminating latch-up effect, inhibiting the impulse current interference of the substrate and the like can be achieved; meanwhile, strain is introduced, so that the mobility of the device is improved;
(3) The fully depleted transistor manufactured by the invention has the advantages of excellent gate control capability, lower electric leakage and the like.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 to 6 are topography diagrams of different process steps in the fabrication of an FDSOI substrate and a transistor according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Although the existing FDSOI substrate has the advantages of small parasitic capacitance, high integration density, high speed and the like compared with the common substrate, the existing FDSOI substrate is still insufficient to meet the requirements of increasingly developed precision devices.
Therefore, the invention provides a novel FDSOI manufacturing process for further reducing parasitic capacitance, improving operation speed, reducing electric leakage, eliminating latch-up effect, inhibiting substrate pulse current interference and the like, and the specific process is as follows.
First, a silicon plate is selected as a backing layer, and a silicon oxide layer is formed thereon. Growth methods include, but are not limited to APCVD, UHVCVD, LPCVD, RTCVD, PECVD or oxide growth, and the like, preferably thermal oxidation, dry or wet oxidation may be employed.
Patterning and etching are then performed, typically with the aid of photoresist, which may be combined with CMP, wet etching, dry etching, atomic Layer Etching (ALE) (dry or wet), gas oxidation + wet etching, etc. Etching is performed to form a plurality of grooves in the silicon oxide layer, and the grooves penetrate through the silicon oxide layer and penetrate into the back silicon layer, so that the surface of the back silicon layer is separated into a plurality of silicon lines, and the silicon oxide layer is separated into a plurality of silicon oxide lines. Since two materials of different chemical composition (masking layer and backing silicon) are etched in this step, a step etch with different etchants is required. Examples of etchants suitable for wet etching of silicon oxide include, but are not limited to, buffered hydrofluoric acid (BHF), buffered Oxide Etchant (BOE), and the like. The silicon can adopt HF-HNO 3 corrosive, alkaline corrosive liquid and the like. The silicon lines and the silicon oxide lines formed in the step have important influence on the performance of the substrate, preferably, the width of 10 nm-100 nm is adopted, the depth-to-width ratio of the grooves is controlled to be more than 2:1, and the thickness of the insulating layer in the final FDSOI is limited by the height of the silicon lines. The appropriate thickness of the silicon oxide layer, etc. can be determined according to the above different requirements.
The silicon layer is then formed as monocrystalline silicon, preferably by selective epitaxial growth. The silicon top layer fills the trench and covers the silicon oxide layer.
The silicon top layer is thinned, typically by CMP.
And coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the adjacent silicon oxide line interval regions, wherein the silicon at intervals between the silicon oxide lines under the partial regions is oxidized in the next step.
And then oxygen implantation is carried out on the exposed area, and the depth of the oxygen implantation is deeper than the position where the silicon oxide line is located and is not higher than the top of the silicon oxide line. And combining with annealing treatment, at this time, the injected oxygen consumes the silicon at intervals between the silicon oxide lines to convert the silicon into silicon oxide, so that a continuous silicon oxide layer is formed, and the back silicon and the top silicon of the partial area are completely isolated, namely, a silicon oxide isolation layer is formed at this step, so that a semiconductor device can be manufactured on the silicon oxide isolation layer.
Taking the FDSOI transistor as an example, a transistor may be fabricated on the silicon top layer region above the silicon oxide isolation layer.
The invention also provides specific embodiments, which are described below with reference to the drawings.
Examples
In the first step, a silicon oxide layer 2 is formed on a silicon-backed layer 1 to obtain a morphology as shown in fig. 1.
In the second step, photolithography and etching are performed to form a plurality of trenches 3 in the silicon oxide layer 2, resulting in the morphology shown in fig. 2. The trench 3 penetrates through the silicon oxide layer 2 and goes deep into the silicon back layer 1, so that the surface of the silicon back layer 1 is separated into a plurality of silicon lines 1a, the silicon oxide layer 2 is separated into a plurality of silicon oxide lines 2a, the depth-to-width ratio of the trench 3 is above 2:1, and the width of each silicon line 1a and the width of each silicon oxide line 2a are 10 nm-100 nm.
And thirdly, selectively epitaxially growing to form a silicon top layer 3, so as to obtain the morphology shown in figure 3.
Fourth, the top silicon layer 3 is thinned, resulting in the topography shown in fig. 4.
And fifthly, coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the interval areas of the adjacent silicon oxide lines.
And a sixth step of performing oxygen implantation on the exposed area of the fifth step, wherein the oxygen implantation depth is deep into the position of the silicon oxide line 2a and is not higher than the top of the silicon oxide line 2a.
Seventh, annealing to form the silicon oxide isolation layer 5, the SOI substrate with small parasitic capacitance, high operation speed, small electric leakage and no latch-up effect is obtained, as shown in FIG. 5.
Eighth, a transistor structure 6 (the box is only schematic in the figure, and no specific structure is shown) is fabricated on the top silicon layer region above the silicon oxide isolation layer 5, as shown in fig. 6.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (10)

1. A method of preparing a fully depleted silicon-on-insulator substrate, comprising:
Forming a silicon oxide layer on the backing silicon layer;
Performing photoetching and etching to enable silicon oxide to form a plurality of grooves, enabling the grooves to penetrate through the silicon oxide layer and penetrate deep into the back silicon layer, enabling the surface of the back silicon layer to be separated into a plurality of silicon lines, and enabling the silicon oxide layer to be separated into a plurality of silicon oxide lines;
forming a silicon top layer, wherein the silicon top layer fills the groove and covers the silicon oxide line;
Thinning the silicon top layer;
coating photoresist on the surface of the silicon top layer, and patterning to expose the surface of the silicon top layer covering the silicon oxide lines and the interval areas of the adjacent silicon oxide lines;
oxygen implantation is carried out on the exposed area, and the depth of the oxygen implantation is deeper than the position of the silicon oxide line and is not higher than the top of the silicon oxide line;
and then annealing to form a silicon oxide isolation layer.
2. The method of claim 1, wherein the trench has an aspect ratio of greater than 2:1.
3. The method of claim 1, wherein the method of forming the silicon top layer is selective epitaxial growth.
4. The method of claim 1, wherein the thinning is chemical mechanical polishing.
5. The method of manufacturing according to claim 1, wherein the silicon oxide layer is formed by a thermal oxidation method.
6. The method of any one of claims 1-5, wherein the silicon lines and the silicon oxide lines have a width of 10nm to 100nm.
7. A silicon-on-insulator substrate obtained by the production method according to any one of claims 1 to 6.
8. Use of the silicon-on-insulator substrate of claim 7 in a semiconductor device.
9. A method of making a fully depleted transistor comprising:
a silicon-on-insulator substrate obtained by the production method according to any one of claims 1 to 6;
and manufacturing a transistor on the silicon top layer area above the silicon oxide isolation layer.
10. A silicon-on-insulator substrate obtained by the production method according to claim 9.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459052A (en) * 2007-12-11 2009-06-17 茂德科技股份有限公司 Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer
CN110941046A (en) * 2019-11-22 2020-03-31 中国科学院微电子研究所 Method for manufacturing SOI silicon grating

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19640308A1 (en) * 1996-09-30 1998-04-02 Siemens Ag Power MOS device
CN1193432C (en) * 2003-02-14 2005-03-16 中国科学院上海微***与信息技术研究所 Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method
KR20060004079A (en) * 2004-07-08 2006-01-12 삼성전자주식회사 Mos transistor with local soi and method thereof
US9882005B2 (en) * 2015-06-22 2018-01-30 International Business Machines Corporation Fully depleted silicon-on-insulator device formation
US10361219B2 (en) * 2015-06-30 2019-07-23 International Business Machines Corporation Implementing a hybrid finFET device and nanowire device utilizing selective SGOI
CN112635492B (en) * 2020-12-02 2023-04-07 广东省大湾区集成电路与***应用研究院 Strain GeSiOI substrate and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101459052A (en) * 2007-12-11 2009-06-17 茂德科技股份有限公司 Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer
CN110941046A (en) * 2019-11-22 2020-03-31 中国科学院微电子研究所 Method for manufacturing SOI silicon grating

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