CN101459052A - Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer - Google Patents
Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer Download PDFInfo
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- CN101459052A CN101459052A CNA2007101968363A CN200710196836A CN101459052A CN 101459052 A CN101459052 A CN 101459052A CN A2007101968363 A CNA2007101968363 A CN A2007101968363A CN 200710196836 A CN200710196836 A CN 200710196836A CN 101459052 A CN101459052 A CN 101459052A
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Abstract
The invention provides a manufacturing method of silicon-on-insulator, which comprises steps of forming a plurality of grooves on a substrate, forming oxide layers on the inner lateral surfaces and inner bottom surfaces of the grooves, forming nitride layers on the oxide layers, removing the nitride layers and the oxide layers on the inner bottom surfaces of the grooves, utilizing silicon anodization to form a porous silicon layer on part of the substrate, utilizing spin-on dielectric to fill the grooves and leading the dielectric to cover the porous silicon layer, and utilizing heating process to from an insulator layer on the porous silicon layer. The invention simultaneously provides a silicon-on-insulator structure manufactured by the method. Utilizing the method to manufacture the silicon-on-insulator structure can reduce cost with fast manufacturing process and increase production rate.
Description
Technical field
The invention relates to a kind of manufacture method of silicon-on-insulator and the structure of silicon-on-insulator, and particularly relevant for a kind of manufacture method of cost-effective silicon-on-insulator and the structure of silicon-on-insulator.
Background technology
In semiconductor technology, silicon-on-insulator (silicon on insulator) is very common semi-conductor electricity sexual isolation technology, the manufacture method of present silicon-on-insulator has two kinds: (1) engagement type silicon-on-insulator, and (2) high dose oxonium ion injects.Wherein:
(1) engagement type silicon-on-insulator, the method need be used two wafer, the wafer layer of oxide layer of growing up on the surface wherein, use hydrogen to be infused in the wafer depths earlier and form microporous layers, then this two wafer is pushed down face-to-face, and under high-temperature, utilize silicon dioxide layer diffusion between the two that they are bonded together, cut microporous layers again both are separated.
(2) the high dose oxonium ion injects, and the method is to be infused under the silicon wafer to form a high oxygen containing face that connects with the unusual oxonium ion of high dose, needs high temperature to anneal and could form buried oxide layer.
Above-mentioned two kinds of methods all need expensive and productivity ratio not high.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of silicon-on-insulator, produce a kind of structure of silicon-on-insulator, in order to solve the too high shortcoming of prior art cost.
The present invention is the characteristic that combines two kinds of technologies, and to reach the structure of silicon-on-insulator, these two kinds of technology are respectively the anode treatment (silicon anodization) and the rotary coating dielectric medium (spin-on dielectric) of silicon.The anode treatment of silicon is an electrochemical reaction, be that silicon is connected on the anode that contains hydrofluoric acid (HF) electrolyte electrolysis tank, apply voltage to reach a controllable Wet-type etching reaction, can form the porous silicon structure in the appropriate parameters interval, and its porosity and pore size can be waited and control by bath composition, temperature and the current potential current density that applies.Generally speaking, between the anode treatment condition portion for p type silicon substrate be: the hydrofluoric acid concentration of electrolyte is between 2-40wt%, and anode potential is less than 1.3 volts, and current density is between 0.5-150mA/cm
2The rotary coating dielectric medium then is to contain multi-silane class (polysilazane) or the predecessor (precursor) of type siloxane (silozane) is coated on substrate surface with method of spin coating, implements an annealing process then so that this coating layer converts dielectric medium to and reaches the densification effect.With multi-silane class (polysilazane) series is example, and it need transform under the atmosphere that contains aqueous vapor more than 400 ℃, and porous silicon is very easily oxidized and form silicon dioxide under this environment.
According to the manufacture method of a kind of silicon-on-insulator proposed by the invention, mainly comprise step: on base material, form a plurality of grooves; Inner surface and inner bottom surface in these grooves form oxide layer; On this oxide layer, form nitration case; Remove the described nitration case and the oxide layer of the inner bottom surface of each groove; Use anode treatment to make the part base material of each beneath trenches form porous silicon layer; The rotary coating dielectric medium fills up those grooves, and this dielectric medium is covered on the described porous silicon layer; And use heating process to make porous silicon layer form insulating barrier.
The manufacture method of silicon-on-insulator of the present invention, use anode treatment that the part base material is formed porous silicon, and the method with rotary coating is inserted dielectric medium in the groove, and use heating process to make porous silicon form insulating barrier, replace traditional engagement type to isolate and high dose oxonium ion injection technique by method of the present invention, can reduce cost, and manufacturing process is quick, productivity ratio is risen.
According to specific embodiments of the present invention, the described method that removes nitration case can be an anisotropic etching.
According to specific embodiments of the present invention, described heating process can be the annealing process that contains the oxidizability oxygen atmosphere of dry type or wet type, annealing temperature is between 400-1200 ℃, and operating pressure can be normal pressure (atmospheric pressure), inferior normal pressure (sub-atmospheric pressure) or low pressure (lowpressure).
According to a specific embodiments of the present invention, the manufacture method of silicon-on-insulator of the present invention comprises step: form a plurality of grooves on silicon base, inner surface and inner bottom surface in each described groove form oxide layer, on this oxide layer, form nitration case, then, remove this nitration case and oxide layer on the inner bottom surface of described groove, use anode treatment to make the part silicon base form porous silicon then, and, use an annealing process to make described porous silicon form insulating barrier at last in rotary coating dielectric material at the bottom of this porous silicon-base and on this nitration case.Via this process, use anode treatment that the part silicon base is formed porous silicon, and the method with rotary coating is evenly inserted dielectric medium in the groove, use annealing process to make the porous silicon oxidation form insulating barrier (silicon dioxide) at last, method can be finished shallow trench isolation simultaneously from (shallow trench isolation) and silicon-on-insulator structure thus, compare with traditional engagement type isolation and high dose oxonium ion injection technique, method of the present invention can reduce cost, and manufacturing process is quick, and productivity ratio is risen.
The present invention provides a kind of structure of silicon-on-insulator simultaneously, and this structure can be made according to the method described above and be obtained, and particularly, the structure of silicon-on-insulator of the present invention comprises:
Substrate (substrate), this substrate comprises base material, a plurality of protuberance and insulating barrier, and wherein insulating barrier is between described base material and described a plurality of protuberance; A plurality of grooves, those channel shaped are formed between each protuberance and the protuberance; Oxide layer, this oxide layer is positioned at the inner surface of each groove; Nitration case, this nitration case are positioned on the described oxide layer; And dielectric medium, this dielectric medium fills up each groove.
According to specific embodiments of the present invention, in the structure of silicon-on-insulator of the present invention, described substrate also can comprise the pad oxide that is formed at each protuberance top and be formed at pad nitration case on this pad oxide.
According to specific embodiments of the present invention, described base material can be silicon substrate.
According to specific embodiments of the present invention, the material of described protuberance and base material can be identical, for example is all silicon.
According to specific embodiments of the present invention, described insulating barrier can be silicon dioxide layer.
According to specific embodiments of the present invention, described nitration case can be silicon nitride layer.
Description of drawings
Fig. 1 is the sectional schematic diagram of structure of the silicon-on-insulator of one embodiment of the invention.
Fig. 2 a～Fig. 2 f is the manufacturing process schematic diagram of the structure of silicon-on-insulator embodiment illustrated in fig. 1.
Primary clustering symbol description among the figure:
100 substrates, 110 base materials, 120 protuberances, 130 pad oxides
140 pad nitration cases, 150 porous silicon layers, 151 insulating barriers, 200 grooves
300 oxide layers, 400 nitration cases, 500 first dielectric mediums, 510 second dielectric mediums
Embodiment
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, existing conjunction with figs. is described in detail as follows:
With reference to Fig. 1, it is the sectional schematic diagram of structure of the silicon-on-insulator of one embodiment of the invention.
Silicon-on-insulator of the present invention is called for short SOI (silicon on insulator) usually, be a kind of semi-conductor electricity sexual isolation technology, the structure of the silicon-on-insulator in the present embodiment comprises: substrate (substrate) 100, groove 200, oxide layer 300, nitration case 400 and second dielectric medium 510; Substrate 100 comprises base material 110, a plurality of protuberance 120, pad oxide 130, pad nitration case 140 and insulating barrier 151; Base material 110 is general silicon wafer, between this base material 110 and the described protuberance 120 insulating barrier 151 is arranged, and this insulating barrier 151 has the effect of electrical isolation; Pad oxide 130 is covered in the top of each protuberance 120, pad nitration case 140 is covered in the top of pad oxide 130, make pad oxide 130 between pad nitration case 140 and each protuberance 120, form groove 200 between each protuberance 120 and the protuberance 120, the both sides capping oxidation layer 300 of each protuberance 120, oxide layer 300 are connected with pad oxide 130 and insulating barrier 151 each protuberance 120 are coated on wherein; Nitration case 400 is a silicon nitride layer in the present embodiment, is covered in outside the oxide layer 300, is connected with pad nitration case 140; Second dielectric medium 510 fills up groove 200, forms the structure of silicon-on-insulator SOI (silicon on insulator).
With reference to Fig. 2 a～Fig. 2 f, be the manufacturing process schematic diagram (with the section signal of structure) of the structure of the silicon-on-insulator of this embodiment.
Shown in Fig. 2 a, deposit a pad oxide 130 and a pad nitration case 140 in regular turn in a base material 110 tops, wherein base material 110 is a silicon substrate; The material of pad oxide 130 can be silicon dioxide; The material of pad nitration case 140 can be silicon nitride.Then be coated with a photoresist layer and define assembly active region (active area) with photoetching process, remove pad nitration case 140 and the pad oxide 130 that is not covered with dry-etching again by photoresist layer, and remove photoresist layer, base material 110 is carried out dry-etching form a plurality of grooves 200.As shown in the figure, a plurality of protuberances 120 have been formed at base material 110 tops, and groove 200 is between each protuberance 120 and protuberance 120.
Shown in Fig. 2 b, in this groove 200, carry out thermal oxidation and form oxide layer 300, the composition of this oxide layer 300 is a silicon dioxide, this oxide layer 300 covers the interior side-wall surface (inner surface) of this groove 200 and the inner bottom surface of this groove 200, and this oxide layer 300 is connected with pad oxide 130; Then, cvd nitride layer 400 is covered on this oxide layer 300, and this nitration case 400 is connected with pad nitration case 140.The material of this nitration case 400 can be silicon nitride.
Shown in Fig. 2 c, use anisotropic etch process to remove with being covered in this nitration case 400 that described oxide layer 300 is positioned at the inner bottom surface top of groove, stay this nitration case 400 on surface, two side, form nitride spacer; Then shown in Fig. 2 d, remove the oxide layer 300 of the inner bottom surface that is positioned at groove, then carry out anode treatment to seeing through the part base material 110 that trench bottom surfaces comes out, the CURRENT DISTRIBUTION during anode treatment will make exposed portions base material 110 under it and side direction form porous silicon layer 150.
Shown in Fig. 2 e, rotary coating one first dielectric medium 500 fills up each groove 200, and this first dielectric medium 500 contacts with porous silicon layer 150.This first dielectric medium 500 is by containing multi-silane class (Polysilazane) or the predecessor of type siloxane (Silozane) is constituted through rotary coating.
At last, shown in Fig. 2 f, use heating process, for example present embodiment is to use annealing process to make oxygen see through described first dielectric medium 500 (Fig. 2 e) formation one insulating barrier 151 that combines with porous silicon layer 150 (Fig. 2 e) under oxidizability oxygen, annealing temperature is between 400-1200 ℃, and operating pressure can be normal pressure (atmospheric pressure), inferior normal pressure (sub-atmospheric pressure) (for example 100-700torr) or low pressure (low pressure) (for example 0.01-10torr).The constituent of this insulating barrier 151 is a silicon dioxide in the present embodiment.Owing to the cause of annealing process, make described first dielectric medium 500 (Fig. 2 e) change into one second dielectric medium 510 in this process.
Via above-mentioned process, mainly be the described base material 110 of part to be formed porous silicon layers 150 by oxide layer and the use anode treatment that removes the groove inner bottom surface, and the method with rotary coating is evenly inserted (dielectric material is coated on silicon base, pad nitration case and the nitration case simultaneously in the present embodiment) in the groove 200 with described first dielectric medium 500, use the oxidizability annealing process to make porous silicon layer 150 oxidations form the insulating barrier 151 of silicon dioxide at last, the method have reduce cost, processing procedure fast, effect that productivity ratio is risen.
Though the present invention discloses as above with an embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (9)
1, a kind of manufacture method of silicon-on-insulator, the method comprising the steps of:
On base material, form a plurality of grooves;
Inner surface and inner bottom surface in these grooves form oxide layer;
On this oxide layer, form nitration case;
Remove the described nitration case and the oxide layer of the inner bottom surface of each groove;
Use anode treatment to make the part base material of each beneath trenches form porous silicon layer;
The rotary coating dielectric medium fills up those grooves, and this dielectric medium is covered on the described porous silicon layer; And
Use heating process to make porous silicon layer form insulating barrier.
2, the manufacture method of silicon-on-insulator as claimed in claim 1, wherein, the method that removes nitration case is an anisotropic etching.
3, the manufacture method of silicon-on-insulator as claimed in claim 1, wherein, described heating process is the annealing process that contains the oxidizability oxygen atmosphere of dry type or wet type, and annealing temperature is between 400-1200 ℃, and operating pressure can be normal pressure, inferior normal pressure or low pressure.
4, a kind of structure of silicon-on-insulator, this structure comprises:
Substrate, this substrate comprises base material, a plurality of protuberance and insulating barrier, and wherein insulating barrier is between described base material and described a plurality of protuberance;
A plurality of grooves, those channel shaped are formed between each protuberance and the protuberance;
Oxide layer, this oxide layer is positioned at the inner surface of each groove;
Nitration case, this nitration case are positioned on the described oxide layer; And
Dielectric medium, this dielectric medium fills up each groove.
5, the structure of silicon-on-insulator as claimed in claim 4, wherein said substrate also comprise the pad oxide that is formed at each protuberance top and are formed at pad nitration case on this pad oxide.
6, the structure of silicon-on-insulator as claimed in claim 4, wherein said base material are silicon substrate.
7, the structure of silicon-on-insulator as claimed in claim 4, wherein said protuberance is identical with the material of base material, is silicon.
8, the structure of silicon-on-insulator as claimed in claim 4, wherein said insulating barrier are silicon dioxide layer.
9, the structure of silicon-on-insulator as claimed in claim 4, wherein said nitration case are silicon nitride layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2007101968363A CN101459052A (en) | 2007-12-11 | 2007-12-11 | Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer |
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| CNA2007101968363A CN101459052A (en) | 2007-12-11 | 2007-12-11 | Manufacturing method for silicon coating on insulation layer and construction for coating silicon on the insulation layer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104952886A (en) * | 2015-06-12 | 2015-09-30 | 宁波时代全芯科技有限公司 | Insulating layer silicon coating structure and preparation method thereof |
| CN110676310A (en) * | 2013-10-17 | 2020-01-10 | 意法半导体(图尔)公司 | High-voltage vertical power component |
| CN113471288A (en) * | 2021-05-19 | 2021-10-01 | 广东省大湾区集成电路与***应用研究院 | Fully-depleted silicon-on-insulator substrate, transistor, preparation method and application thereof |
-
2007
- 2007-12-11 CN CNA2007101968363A patent/CN101459052A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676310A (en) * | 2013-10-17 | 2020-01-10 | 意法半导体(图尔)公司 | High-voltage vertical power component |
| CN110676310B (en) * | 2013-10-17 | 2023-05-16 | 意法半导体(图尔)公司 | High voltage vertical power component |
| CN104952886A (en) * | 2015-06-12 | 2015-09-30 | 宁波时代全芯科技有限公司 | Insulating layer silicon coating structure and preparation method thereof |
| CN113471288A (en) * | 2021-05-19 | 2021-10-01 | 广东省大湾区集成电路与***应用研究院 | Fully-depleted silicon-on-insulator substrate, transistor, preparation method and application thereof |
| CN113471288B (en) * | 2021-05-19 | 2024-06-14 | 广东省大湾区集成电路与***应用研究院 | Fully depleted silicon-on-insulator substrate, transistor, preparation method and application thereof |
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Application publication date: 20090617 |