CN113470723B - Method and device for testing read retry, readable storage medium and electronic equipment - Google Patents
Method and device for testing read retry, readable storage medium and electronic equipment Download PDFInfo
- Publication number
- CN113470723B CN113470723B CN202110724696.2A CN202110724696A CN113470723B CN 113470723 B CN113470723 B CN 113470723B CN 202110724696 A CN202110724696 A CN 202110724696A CN 113470723 B CN113470723 B CN 113470723B
- Authority
- CN
- China
- Prior art keywords
- target
- data
- bit
- target page
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a read retry test method, a device, a readable storage medium and electronic equipment, which are used for traversing a target operation mode of a flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed; performing read operation on a preset target page in the traversed target block to obtain target original data; performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping; and reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining a test result of the read retry function according to the reading result, so that the data is forcedly modified to perform bit turning construction, thereby triggering and testing the main control read retry function and improving the efficiency of testing the read retry function.
Description
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a method and apparatus for testing read retry, a readable storage medium, and an electronic device.
Background
Due to poor factory quality, abrasion in use or high-temperature environmental influence and the like, when the NAND flash master control reads data on NAND flash particles, the data possibly has more bit overturning, error correction is needed through an ECC (Error Checking and Correcting) module of the master control, and the master control generally provides Read Retry (RR) and Deep Read Retry (DRR) functions, and cooperates with functions of adjusting read voltage offset (read offset), reading soft data (read soft data) and the like provided by particle manufacturers, so that the error correction capability can be further improved, and the data integrity is protected.
The NAND flash structures and control logic of different particle manufacturers are different, and the implementation methods of the functions of read offset, read soft data and the like are also quite different; meanwhile, supporting multiple flash particles is also a requirement for the general design of the NAND flash master control, so that adapting new flash particles based on the existing master control is a common task of master control software developers, and RR and DRR functions are important points in the task of adapting new particles.
In general, the verification of RR and DRR functions requires that the data of the NAND flash exceeds the error correction capability of the master control to trigger the execution, so that a common means is to perform high-temperature processing on NAND flash particles after erasing (erase) and encoding (program) on the NAND flash, so that the data quality in the NAND flash is poor, and further the master control is triggered to execute RR and DRR processes.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: a method, a device, a readable storage medium and an electronic device for testing read retry are provided, which can improve the efficiency of testing read retry functions.
In order to solve the technical problems, the invention adopts a technical scheme that:
a read retry test method, comprising:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining a test result of the read retry function according to the reading result.
In order to solve the technical problems, the invention adopts another technical scheme that:
a read retry test apparatus, comprising:
a bit flip architecture module for:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and the test module is used for reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining the test result of the read retry function according to the reading result.
In order to solve the technical problems, the invention adopts another technical scheme that:
a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of a read retry test method as described above.
In order to solve the technical problems, the invention adopts another technical scheme that:
an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of a read retry test method as described above when executing the computer program.
The invention has the beneficial effects that: the method comprises the steps of performing read operation on a preset target page in a traversed target block to obtain target original data, performing bit overturn on data of the preset target page based on the target original data, reading the data of the preset target page after bit overturn to obtain a read result, and obtaining a test result according to the read result.
Drawings
FIG. 1 is a flow chart showing the steps of a read retry test method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a read retry testing apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a flow chart of a read retry test method according to an embodiment of the invention.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings.
Referring to fig. 1, an embodiment of the present invention provides a read retry testing method, including:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining a test result of the read retry function according to the reading result.
From the above description, the beneficial effects of the invention are as follows: the method comprises the steps of performing read operation on a preset target page in a traversed target block to obtain target original data, performing bit overturn on data of the preset target page based on the target original data, reading the data of the preset target page after bit overturn to obtain a read result, and obtaining a test result according to the read result.
Further, the method further comprises the following steps:
traversing a plurality of operation modes of the flash memory to be tested according to the test request until all the operation modes of the flash memory to be tested are traversed;
and executing the step of traversing the target operation mode of the flash memory to be tested by taking the block as a unit according to the received test request of the read retry function of the flash memory to be tested for the traversed target operation mode.
As can be seen from the above description, since the flash memory to be tested includes multiple block operation modes, such as single level cell (slc, single layer storage) and triple level cell (tlc, 3 rd order unit), the multiple operation modes of the flash memory to be tested are traversed, and the operation modes are tested in turn, so that the comprehensiveness of the test is improved.
Further, the step of performing a read operation on a preset target page in the traversed target block to obtain target original data further includes the steps of:
performing an erasing operation on the data of the target block;
writing data into the target block according to a preset data template;
generating original data of a preset target page according to the data in the target block;
the reading operation is performed on the preset target page in the traversed target block, and the obtaining of the target original data comprises the following steps:
and reading the original data of a preset target page in the traversed target block to obtain target original data.
As can be seen from the above description, by performing the erasing operation on the target block, the initial standard data can be established on the target block of the flash memory to be tested, the subsequent operation of modifying the original data by repeating programming is performed on the basis, the original data of the preset target page is read only once, and the bit flipping of the subsequent structure is completed on the basis of the target original data, so that the data written in the preset target page by performing the writing operation twice successively is basically the same, the speed of increasing the number of bit flipping is effectively controlled, and the situation that the previous successful and the subsequent failure are caused by the larger difference of the number of bit flipping in the two times of reading at intervals is avoided, thereby improving the effectiveness of the read retry function test.
Further, the test request also includes the current random selection times;
the step of performing bit flipping on the data of the preset target page based on the target original data, before obtaining the preset target page after bit flipping, further includes the steps of:
determining randomly selected total times according to the target original data;
judging whether the current random selection times is greater than or equal to the total random selection times, if so, ending the test, outputting prompt information, if not, adding one to the current random selection times, and executing the step of bit turning the data of the preset target page based on the target original data;
the step of performing bit flipping on the data of the preset target page based on the target original data, where obtaining the preset target page after bit flipping includes:
randomly selecting any bit from the target original data to obtain a target bit;
and judging whether the data of the target bit is a first preset value, if not, returning to execute the step of judging whether the current random selection times are larger than or equal to the random selection total times, if so, turning the data of the target bit into a second preset value to obtain target original data after the bit is turned, and writing the target original data after the bit is turned into the preset target page to obtain the preset target page after the bit is turned.
According to the description, the total random selection times are determined according to the target original data, and whether the current random selection times exceed the total random selection times is judged before each random selection, so that invalid repeated selection can be well avoided, the test accuracy is improved, meanwhile, the test efficiency is improved, any bit is randomly selected from the target original data, a target bit is obtained, when the data of the target bit is a first preset value, bit overturn is carried out on the target bit, gradual increase of bit overturn is realized, bit overturn under a real use environment can be simulated, and the test accuracy is improved.
Further, before the step of reading the data of the preset target page after the bit flip, the method further comprises the steps of:
receiving a read retry function check instruction corresponding to the test request;
acquiring a trigger state of the read retry function according to the read retry function checking instruction;
and judging whether the triggering state of the read retry function is triggered, if so, executing the step of reading the data of the preset target page after the bit is turned, and if not, returning to execute the step of judging whether the current random selection times are larger than or equal to the random selection total times.
It can be seen from the above description that, before the data of the preset target page is finally read, it is first determined whether the main control read retry function is triggered, and only if the read retry function is triggered, the read retry function is tested, so that misjudgment of the read retry function is avoided, and the reliability of the test is improved.
Further, the reading the data of the preset target page after the bit is turned over to obtain a reading result, and the obtaining the test result of the read retry function according to the reading result includes:
reading the data of the preset target page after the bit is turned to obtain a reading result;
judging whether the reading result fails to read, if so, the reading retry function is abnormal, if not, the reading retry function is normal, and returning to the step of executing the judgment whether the current random selection times are greater than or equal to the random selection total times.
As can be seen from the above description, the reading result is used to determine whether the reading retry function is normal, and when the reading retry function is normal, the random selection step is repeatedly executed until the total number of random selections is reached, and then the test is stopped, thereby improving the reliability and accuracy of the reading retry function test.
Further, the flash memory to be tested comprises a NAND flash.
From the above description, it can be seen that the method can be used for testing the read retry function of the NAND flash master control.
Referring to fig. 2, another embodiment of the present invention provides a read retry testing apparatus, including:
a bit flip architecture module for:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and the test module is used for reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining the test result of the read retry function according to the reading result.
Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a read retry test method described above.
Referring to fig. 3, another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements the steps of the above-mentioned method for testing a read retry when executing the computer program.
The method, the device, the readable storage medium and the electronic device for the read retry test according to the present invention can be applied to any flash memory having a read retry function, such as a NAND flash (NAND flash), and the following description is made by specific embodiments:
example 1
Referring to fig. 1 and 4, a read retry test method of the present embodiment includes:
s0, traversing a plurality of operation modes of the flash memory to be tested according to the received test request of the read retry function of the flash memory to be tested until all the operation modes of the flash memory to be tested are traversed;
step S1 is executed for the traversed target operation mode;
wherein the plurality of operation modes are a plurality of block operation modes, in this embodiment, the plurality of operation modes include single level cell (slc, single layer storage) mode and triple level cell (tlc, 3 rd order cell) mode, and the read retry function includes Read Retry (RR) and Deep Read Retry (DRR);
specifically, as shown in fig. 4, traversing the slc mode and the tlc mode according to the received test request of RR or DRR of the NAND flash to be tested until all operation modes are traversed, executing step S1 for the traversed target operation mode, and executing step S1 for the slc mode if the traversed target operation mode is the slc mode;
s1, traversing a target operation mode of a flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
specifically, traversing a target operation model of the NAND flash to be tested by taking blocks as units until all blocks in the target operation mode are traversed;
s2, performing erasure operation on the traversed data of the target block;
specifically, as shown in fig. 4, performing an erase operation on the traversed data of the target block;
s3, writing data into the target block according to a preset data template;
specifically, as shown in fig. 4, a program (write) operation is performed on the target block according to a preset data template;
s4, generating original data of a preset target page according to the data in the target block;
specifically, raw data (original data) of a preset target page (page) is generated according to data in a target block;
the preset target page can be freely set and selected according to actual conditions;
s5, performing read operation on a preset target page in the traversed target block to obtain target original data;
specifically, as shown in fig. 4, reading raw data of a preset target page to obtain target raw data;
s6, carrying out bit turning on the data of the preset target page based on the target original data to obtain a preset target page after bit turning;
and S7, reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining a test result of the read retry function according to the reading result.
Example two
Referring to fig. 4, the present embodiment further defines how to gradually construct bit flip and test RR or DRR based on the first embodiment, specifically:
wherein the test request further includes a current random number of selections;
the step S6 further includes:
determining randomly selected total times according to the target original data;
judging whether the current random selection times is greater than or equal to the total random selection times, if so, ending the test, outputting prompt information, and if not, adding one to the current random selection times, and executing the step S6;
the prompting information may be prompting that the current random selection times are larger than the total random selection times, and the preset target page needs to be reselected;
specifically, as shown in fig. 4, determining the total random selection times according to the bit number of the target raw data, judging whether the current random selection times is greater than or equal to the total random selection times, if yes, ending the test, and outputting the prompt message, if not, adding one to the current random selection times, executing step S6, assuming that the bit number of the target raw data is 15, then the total random selection times is 15, and the current random selection times is 0 and less than the total random selection times 15, thus adding one to the random selection times to update to be 1, and then executing step S6;
the step S6 comprises the following steps:
s61, randomly selecting any bit from the target original data to obtain a target bit;
s62, judging whether the data of the target bit is a first preset value, if not, returning to the step of executing the judgment of whether the current random selection times are greater than or equal to the random selection total times, if so, turning the data of the target bit to a second preset value to obtain target original data after the bit is turned, and writing the target original data after the bit is turned into the preset target page to obtain a preset target page after the bit is turned;
the first preset value and the second preset value can be flexibly set according to actual conditions, and in the embodiment, the first preset value is 1, and the second preset value is 0;
specifically, as shown in fig. 4, randomly selecting any bit from the target raw data to obtain a target bit;
judging whether the data of the target bit is 1, if not, returning to execute the step of judging whether the current random selection times is greater than or equal to the total random selection times, if so, turning the data of the target bit to 0 to obtain target raw data after bit turning, and writing the target raw data after bit turning into a preset target page to obtain the preset target page after bit turning;
the step S7 further includes:
receiving a read retry function check instruction corresponding to the test request;
acquiring a trigger state of the read retry function according to the read retry function checking instruction;
judging whether the triggering state of the read retry function is triggered, if so, executing the step of reading the data of the preset target page after the bit is turned over, and if not, returning to execute the step of judging whether the current random selection times are greater than or equal to the random selection total times;
specifically, the triggering state of the RR or the DRR is obtained according to the reading retry function checking instruction, and the triggering state of the RR or the DRR can be displayed through log printing;
judging whether the triggering state of RR or DRR is triggered, if yes, executing step S7, and if not, returning to execute the step of judging whether the current random selection times are greater than or equal to the total random selection times;
the step S7 comprises the following steps:
s71, reading the data of the preset target page after the bit is turned to obtain a reading result;
s72, judging whether the reading result fails to read, if so, the reading retry function is abnormal, if not, the reading retry function is normal, and returning to the step of executing the judgment of whether the current random selection times is greater than or equal to the random selection total times;
specifically, as shown in fig. 4, performing read operation on the data of the preset target page after bit flip to obtain a reading result;
judging whether the read result fails, if so, the RR or the DRR is abnormal, if not, the RR or the DRR is normal, and returning to the step of executing the judgment whether the current random selection times are larger than or equal to the total random selection times.
Example III
Referring to fig. 2, a read retry testing apparatus includes:
a bit flip architecture module for:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and the test module is used for reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining the test result of the read retry function according to the reading result.
Example IV
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the read retry test method of embodiment one or embodiment two.
Example five
Referring to fig. 3, an electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the read retry test method in the first or second embodiments when executing the computer program.
In summary, according to the read retry test method, the device, the readable storage medium and the electronic equipment provided by the invention, according to the received test request of the read retry function of the flash memory to be tested, traversing the target operation mode of the flash memory to be tested by taking the block as a unit until all blocks in the target operation mode are traversed, and reading the original data of the preset target page in the traversed target block to obtain the target original data; determining the random total selection times according to the target original data, if the current random selection times are smaller than the random total selection times, adding one to the current random selection times, randomly selecting any bit from the target original data, and if the data of the target bit is a first preset value, turning the target bit to obtain a preset target page after bit turning; reading data of a preset target page after bit turning to obtain a reading result, when the reading result is reading failure, reading retry function is abnormal, otherwise, reading retry function is normal, and executing random selection times judgment step is returned, so that the situation that the reading retry function is triggered and tested only by erasing and writing a flash memory and performing high-temperature processing operation in the prior art, but the data of the preset target page is turned on the basis of target original data of the preset target page, so that the data is forcedly modified to perform bit turning is avoided, the main control reading retry function is triggered and tested, the efficiency of testing the reading retry function is improved, only any bit is selected for each bit turning, the gradual increase of the number of bit turning is realized, the speed of increasing the number of bit turning is effectively controlled, the situation that the previous successful and subsequent times fail due to larger interval between two times of reading bit turning is avoided, and the effectiveness of the reading retry function test is improved.
In the foregoing embodiments provided by the present application, it should be understood that the disclosed method, apparatus, computer readable storage medium and electronic device may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple components or modules may be combined or integrated into another apparatus, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with respect to each other may be an indirect coupling or communication connection via some interfaces, devices or components or modules, which may be in electrical, mechanical, or other forms.
The components illustrated as separate components may or may not be physically separate, and components shown as components may or may not be physical modules, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the components may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (10)
1. A method of read retry testing comprising:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining a test result of the read retry function according to the reading result.
2. The method of claim 1, further comprising:
traversing a plurality of operation modes of the flash memory to be tested according to the test request until all the operation modes of the flash memory to be tested are traversed;
and executing the test request according to the read retry function of the flash memory to be tested for the traversed target operation mode, and traversing the target operation mode of the flash memory to be tested by taking a block as a unit.
3. The method for testing read retry according to claim 1, wherein the step of performing a read operation on a preset target page in the traversed target block, before obtaining the target original data, further comprises the steps of:
performing an erasing operation on the data of the target block;
writing data into the target block according to a preset data template;
generating original data of a preset target page according to the data in the target block;
the reading operation is performed on the preset target page in the traversed target block, and the obtaining of the target original data comprises the following steps:
and reading the original data of a preset target page in the traversed target block to obtain target original data.
4. The method of claim 1, wherein the test request further comprises a current random number of selections;
the step of performing bit flipping on the data of the preset target page based on the target original data, before obtaining the preset target page after bit flipping, further includes the steps of:
determining randomly selected total times according to the target original data;
judging whether the current random selection times is greater than or equal to the total random selection times, if so, ending the test, outputting prompt information, if not, adding one to the current random selection times, and executing the step of bit turning the data of the preset target page based on the target original data;
the step of performing bit flipping on the data of the preset target page based on the target original data, where obtaining the preset target page after bit flipping includes:
randomly selecting any bit from the target original data to obtain a target bit;
and judging whether the data of the target bit is a first preset value, if not, returning to execute the step of judging whether the current random selection times are larger than or equal to the random selection total times, if so, turning the data of the target bit into a second preset value to obtain target original data after the bit is turned, and writing the target original data after the bit is turned into the preset target page to obtain the preset target page after the bit is turned.
5. The method for read retry testing as recited in claim 4, further comprising the step of, before said reading said bit flipped data of said predetermined target page:
receiving a read retry function check instruction corresponding to the test request;
acquiring a trigger state of the read retry function according to the read retry function checking instruction;
and judging whether the triggering state of the read retry function is triggered, if so, executing the step of reading the data of the preset target page after the bit is turned, and if not, returning to execute the step of judging whether the current random selection times are larger than or equal to the random selection total times.
6. The method of claim 4, wherein the step of reading the data of the bit-flipped preset target page to obtain a read result, and obtaining the test result of the read retry function according to the read result comprises:
reading the data of the preset target page after the bit is turned to obtain a reading result;
judging whether the reading result fails to read, if so, the reading retry function is abnormal, if not, the reading retry function is normal, and returning to the step of executing the judgment whether the current random selection times are greater than or equal to the random selection total times.
7. The method according to any one of claims 1 to 6, wherein the flash memory under test comprises a NAND flash.
8. A read retry test apparatus, comprising:
a bit flip architecture module for:
traversing a target operation mode of the flash memory to be tested by taking a block as a unit according to a received test request of a read retry function of the flash memory to be tested until all blocks in the target operation mode are traversed;
performing read operation on a preset target page in the traversed target block to obtain target original data;
performing bit flipping on the data of the preset target page based on the target original data to obtain a preset target page after bit flipping;
and the test module is used for reading the data of the preset target page after the bit is turned to obtain a reading result, and obtaining the test result of the read retry function according to the reading result.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of a read retry test method according to any one of claims 1 to 7.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of a read retry test method according to any one of claims 1 to 7 when the computer program is executed by the processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110724696.2A CN113470723B (en) | 2021-06-29 | 2021-06-29 | Method and device for testing read retry, readable storage medium and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110724696.2A CN113470723B (en) | 2021-06-29 | 2021-06-29 | Method and device for testing read retry, readable storage medium and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113470723A CN113470723A (en) | 2021-10-01 |
| CN113470723B true CN113470723B (en) | 2023-07-14 |
Family
ID=77873591
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110724696.2A Active CN113470723B (en) | 2021-06-29 | 2021-06-29 | Method and device for testing read retry, readable storage medium and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113470723B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116913364B (en) * | 2023-06-27 | 2024-02-23 | 珠海妙存科技有限公司 | Flash memory read interference test method and system, electronic equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536864A (en) * | 2014-12-10 | 2015-04-22 | 山东华芯半导体有限公司 | Fault injection method for Nand Flash simulation model with controllable bit flipping |
| CN106776109A (en) * | 2016-12-26 | 2017-05-31 | 湖南国科微电子股份有限公司 | Solid state hard disc read error detection means and reading can not entangle the detection method of error reason |
| CN108241549A (en) * | 2016-12-27 | 2018-07-03 | 北京京存技术有限公司 | NAND data Read Retry error correction methods and NAND controller based on ECC |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110659146A (en) * | 2019-08-05 | 2020-01-07 | 广州妙存科技有限公司 | Temperature-based flash memory re-reading method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11494254B2 (en) * | 2019-12-20 | 2022-11-08 | Cnex Labs, Inc. | Storage system with predictive adjustment mechanism and method of operation thereof |
-
2021
- 2021-06-29 CN CN202110724696.2A patent/CN113470723B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536864A (en) * | 2014-12-10 | 2015-04-22 | 山东华芯半导体有限公司 | Fault injection method for Nand Flash simulation model with controllable bit flipping |
| CN106776109A (en) * | 2016-12-26 | 2017-05-31 | 湖南国科微电子股份有限公司 | Solid state hard disc read error detection means and reading can not entangle the detection method of error reason |
| CN108241549A (en) * | 2016-12-27 | 2018-07-03 | 北京京存技术有限公司 | NAND data Read Retry error correction methods and NAND controller based on ECC |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110659146A (en) * | 2019-08-05 | 2020-01-07 | 广州妙存科技有限公司 | Temperature-based flash memory re-reading method |
Non-Patent Citations (2)
| Title |
|---|
| 一种MLC闪存存储***的比特翻转译码算法;张旋;慕建君;焦晓鹏;;西安电子科技大学学报(第05期);81-86+152 * |
| 基于多精度感知的MLC闪存比特翻转译码算法;张旋;燕莎;李晓强;刘强辉;;计算机测量与控制(第09期);199-204 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113470723A (en) | 2021-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8418030B2 (en) | Storage system with data recovery function and method thereof | |
| US9703627B2 (en) | Error correction code unit, self-test method and associated controller applied to flash memory device for generating soft information | |
| US8862953B2 (en) | Memory testing with selective use of an error correction code decoder | |
| US20180174665A1 (en) | Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic | |
| US8572444B2 (en) | Memory apparatus and testing method thereof | |
| US20230195994A1 (en) | Chip design verification system, chip design verification method, and computer readable recording media with stored program | |
| CN113035259A (en) | DRAM test method and device, readable storage medium and electronic equipment | |
| CN115440294A (en) | Multi-command hybrid test method for NAND Flash controller | |
| CN113778822A (en) | Error correction capability test method and device, readable storage medium and electronic equipment | |
| CN111459708B (en) | Bad block processing method and device | |
| US9009548B2 (en) | Memory testing of three dimensional (3D) stacked memory | |
| CN113470723B (en) | Method and device for testing read retry, readable storage medium and electronic equipment | |
| CN102929740A (en) | Method and device for detecting bad block of storage equipment | |
| CN102646453A (en) | Method and system for testing error correcting code module in NandFlash controller | |
| US7181641B2 (en) | Data storage verification techniques for disk drivers | |
| CN113470728B (en) | Error correction capability test method and device, readable storage medium and electronic equipment | |
| CN111897685A (en) | Method and device for checking data in power failure, storage medium and electronic equipment | |
| TWI442406B (en) | Method for enhancing verification efficiency regarding error handling mechanism of a controller of a flash memory, and associated memory device and controller thereof | |
| CN112102875A (en) | LPDDR test method, device, readable storage medium and electronic equipment | |
| CN111597699A (en) | FLASH simulator supporting power-down data randomization | |
| US20180261298A1 (en) | Memory system including a delegate page and method of identifying a status of a memory system | |
| US11836035B2 (en) | Data storage device with data verification circuitry | |
| CN105787388B (en) | The method and apparatus for controlling black box | |
| CN102033791B (en) | Method for improving verification efficiency of controller of flash memory, memory device and controller | |
| CN113032222B (en) | Solid state disk resistant to single event functional interruption |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |