CN113032222B - Solid state disk resistant to single event functional interruption - Google Patents
Solid state disk resistant to single event functional interruption Download PDFInfo
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- CN113032222B CN113032222B CN202110393004.0A CN202110393004A CN113032222B CN 113032222 B CN113032222 B CN 113032222B CN 202110393004 A CN202110393004 A CN 202110393004A CN 113032222 B CN113032222 B CN 113032222B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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Abstract
The invention relates to a solid state disk resistant to single event function interruption, which comprises a solid state disk, wherein a control chip is arranged in the solid state disk, one side of the control chip is connected with a flash memory array, one sides of the control chip and the flash memory array are connected with an input/output interface, and one side of the control chip, which is far away from the control chip, is also connected with a monitoring circuit; the solid state disk resisting single-particle functional interruption is provided aiming at the problem that a control chip in the existing solid state disk is weak in single-particle functional interruption resistance, and the single-particle functional interruption resistance of the solid state disk can be improved; by adding the monitoring circuit to the solid state disk and mutually monitoring the monitoring circuit and the control chip, the problem that the control chip in the solid state disk flies due to SEFI to respond to an operation request of an external interface is solved, and the SEFI resistance of the solid state disk is effectively improved.
Description
Technical Field
The invention relates to the technical field of solid state disks, in particular to a solid state disk resistant to single event functional interruption.
Background
The solid state disk is more and more widely applied to the aerospace field by virtue of the characteristics of large capacity, high access speed and the like; however, the solid state disk applied to severe radiation environments such as aerospace and the like is affected by a Single-event upset effect (SEU) and a Single-event functional interruption effect (SEFI) to cause errors, which results in immeasurable loss; at present, the SEU resistance of data stored by flash memory particles in a solid state disk is stronger through multi-level redundancy error correction, but a control chip in the solid state disk is seriously influenced by SEFI, and the improvement of the SEFI resistance of the control chip is the key for realizing the application of the solid state disk in severe radiation environments such as aerospace and the like;
data stored by flash memory particles in the solid state disk have certain error probability, so that the general solid state disk constructs a multi-level redundancy error correction mode to ensure the correctness of the stored data, the Single Event Upset (SEU) can cause errors of the stored data in the solid state disk, and the current multi-level redundancy error correction mode is also suitable for SEU reinforcement resistance; in addition, a number of papers and patents have also proposed various approaches to secure memory against SEU; however, the control chip in the solid state disk is also affected by single-particle irradiation, and a single-particle functional interruption (SEFI) effect occurs;
the SEFI can cause two consequences for the solid state disk: firstly, a control chip in the solid state disk is caused to run away and cannot respond to an operation request of an external interface; second, an operation error of the control chip in the solid state disk is caused, which includes but is not limited to the following cases: 1. writing error data into an error address, and 2, writing correct data into the error address; 3. writing the error data into the correct address; 4. the read address is wrong, and the returned data is also wrong; 5. reading an address error, and returning correct data of the error address; 6. the read address is correct, and the returned data is wrong; 7. erasure is not completed; aiming at the influence of SEFI on the solid state disk, no targeted reinforcing scheme exists at present.
In the industry, a method for reinforcing a memory including a solid state disk against single particles mainly focuses on reinforcing stored data against SEU, and at present, no technical scheme for reinforcing the memory including the solid state disk against single particle functional interruption exists.
Disclosure of Invention
The invention aims to provide a solid state disk resistant to single event function interruption, and aims to solve the problem that no technical scheme for resisting single event function interruption of the solid state disk exists in the background technology.
In order to realize the purpose, the invention adopts the technical scheme that: the solid state disk capable of resisting single event function interruption comprises a solid state disk, wherein a control chip is arranged inside the solid state disk, a flash memory array is connected to one side of the control chip, an input/output interface is connected to one side of the control chip and one side of the flash memory array, and a monitoring circuit is connected to one side, far away from the control chip, of the control chip.
Furthermore, the control chip, the flash memory array, the monitoring circuit and the input/output interface are electrically connected with each other.
In order to achieve the above purpose, the invention adopts the technical scheme that: a method for a solid state disk resisting single event function interruption comprises the following procedures:
s10, monitoring a working flow of the control chip by a monitoring circuit;
s20, controlling a monitoring working process of the monitoring circuit by the chip;
s30, controlling the flow of the chip reading operation;
s40, controlling the flow of writing operation of the chip;
and S50, controlling the flow of the chip erasing operation.
Further, the monitoring workflow of the monitoring circuit to the control chip includes:
step 1: electrifying, initializing an upper time limit T, initializing a time interval delta T, and starting to monitor the input and output interface;
step 2: waiting for a time Δ T;
and step 3: sending a response signal A to the control chip;
and 4, step 4: if the input/output interface is found to have operation request information for the control chip of the solid state disk, timing is started, a timing variable t =0 is set, the step 5 is switched, and otherwise, the step 2 is switched;
and 5: waiting for delta T time, and increasing the value of T by delta T;
step 6: sending a response signal A to the control chip;
and 7: and if the control chip of the solid state disk returns the operation completion information of the input/output interface, turning to the step 2, otherwise, turning to the step 8.
And 8: if the timing T is more than or equal to T, judging that the control chip generates SEFI, resetting and starting the control chip, and turning to the step 2; otherwise go to step 5.
Further, the monitoring work flow of the monitoring circuit by the control chip comprises;
step 1: powering on, initializing a waiting time interval multiple B, and initializing a count m =0;
and 2, step: waiting for a time Δ T;
and step 3: if a response signal A sent by the monitoring circuit is received, setting m =0, turning to step 2, otherwise increasing the value of m by 1, and turning to step 4;
and 4, step 4: if m is greater than B, judging that the monitoring circuit has SEFI, resetting and starting the monitoring circuit, setting m =0, and turning to the step 1; otherwise, turning to the step 2.
Further, the monitoring circuit can judge the operation request type of the input/output interface to the solid state disk control chip, and set different upper limit of the completion time for different operation request types.
Further, according to the anti-SEFI characteristics of the monitoring circuit and the control chip, the configured delta T range is between 1 millisecond and 10 seconds, and it is ensured that SEFI cannot occur to the monitoring circuit and the control chip at the same time.
Further, the flow of the read operation of the control chip includes;
step 1: receiving a read request of an input/output interface to a logical block address P0;
and 2, step: and performing a first read operation:
step 201: converting the logical block address P0 into a physical block address P1;
step 202: reading data Q1 of a physical block address P1 from the flash memory array;
and step 3: and performing a second read operation:
step 301: converting the logical block address P0 to a physical block address P2;
step 302: reading data Q2 of the physical block address P2 from the flash memory array;
and 4, step 4: comparing whether P1= P2 and Q1= Q2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: and carrying out a third read operation:
step 501: converting the logical block address P0 into a physical block address P3;
step 502: reading data Q3 of the physical block address P3 from the flash memory array;
step 6: comparing whether P1= P3 and Q1= Q3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3 and Q2= Q3, if so, turning to step 9, otherwise, judging that SEFI occurs and cannot be recovered, returning that the read operation of the input/output interface fails, and ending;
and 8: returning the input/output interface data Q1, and ending;
and step 9: and returning the input/output interface data Q2, and ending.
Further, the flow of the control chip write operation includes.
Step 1: receiving a write request of writing data Q0 into a logical block address P0 by an input/output interface;
and 2, step: converting the logical block address P0 into a physical block address P1;
and step 3: converting the logical block address P0 to a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 to a physical block address P3;
step 6: comparing whether P1= P3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning to the failure of the write operation of the input/output interface;
and 8: writing the data Q0 into a physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: writing the data Q0 into a physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: reading data Q1 of a physical block address P2 from the flash memory array, and turning to step 12;
step 12: comparing whether Q0= Q1, if so, returning that the write operation of the input/output interface is completed; otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, and returning that the write operation of the input/output interface fails.
Further, the flow of controlling the chip erasing operation includes:
step 1: receiving an erasing request of an input/output interface to a logical block address P0;
step 2: converting the logical block address P0 into a physical block address P1;
and step 3: converting the logical block address P0 into a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 to a physical block address P3;
step 6: comparing whether P1= P3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning to the failure of the input/output interface erasing operation;
and 8: erasing the physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: erasing the physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: reading data Q1 of a physical block address P2 from the flash memory array, and turning to step 12;
step 12: whether Q1 is completely erased or not, if so, returning to the completion of the erasing operation of the input/output interface; otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, and returning that the input/output interface erasing operation fails.
The invention has the beneficial effects that:
1. the solid state disk resisting single-particle functional interruption is provided aiming at the problem that a control chip in the existing solid state disk is weak in single-particle functional interruption resistance, and the single-particle functional interruption resistance of the solid state disk can be improved;
2. according to the solid state disk resistant to single event interruption, the monitoring circuit is added to the solid state disk, and the monitoring circuit and the control chip are mutually monitored, so that the problem that the control chip in the solid state disk is flown away due to SEFI to respond to an operation request of an external interface is solved, and the SEFI resistance of the solid state disk is effectively improved;
3. the solid state disk resisting the single event functional interruption eliminates recoverable operation errors of a control chip in the solid state disk caused by SEFI through a mode of multiple operations and cross check, alarms the unrecoverable operation errors, and effectively improves the SEFI resistance of the solid state disk.
Drawings
FIG. 1 is a flow chart of a solid state disk resistant to single event functional interruption according to the present invention;
FIG. 2 is a flowchart of the monitoring operation of the monitoring circuit of the solid state disk method for resisting single event interruption on the control chip according to the present invention;
FIG. 3 is a flowchart illustrating the monitoring operation of the monitoring circuit by the control chip according to the method of the solid state disk for resisting single event interruption of the present invention;
FIG. 4 is a flowchart of a control chip read operation of the method for a solid state disk resistant to single event functional interruption according to the present invention;
FIG. 5 is a flowchart of a control chip write operation of the method of the solid state disk resisting single event functional interruption according to the present invention;
FIG. 6 is a flowchart of the control chip erase operation of the method for a solid state disk resisting single event functional interruption according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the present invention provides a technical solution: the solid state disk capable of resisting single event function interruption comprises a control chip 1, a flash memory array 2, a monitoring circuit 3, an input/output interface 4 and a solid state disk 5, wherein the control chip 1 is arranged inside the solid state disk 5, one side of the control chip 1 is connected with the flash memory array 2, one sides of the control chip 1 and the flash memory array 2 are connected with the input/output interface 4, and one side of the control chip 1, which is far away from the control chip 1, is also connected with the monitoring circuit 3;
preferably, the control chip 1, the flash memory array 2, the monitoring circuit 3 and the input/output interface 4 are electrically connected, and the control chip 1 is connected with the flash memory array 2 and the monitoring circuit 3 and communicates with the outside through the input/output interface 4. The control chip 1 is used for interacting data with the input/output interface 4 and the monitoring circuit 3, for resetting and starting the circuit of the monitoring circuit 3, for reading and writing data in the flash memory array 2 and erasing all data in the flash memory array 2, the flash memory array 2 stores data and is used for storing, outputting and erasing data under the control of the control chip 1, and the monitoring circuit 3 is connected with the control chip 1 and is used for interacting data with the control chip 1, controlling the resetting and starting of the control chip 1 and monitoring and recording data of the input data interface.
As shown in fig. 2 to 6, the present invention provides a technical solution: a method for a solid state disk resisting single event function interruption comprises the following procedures:
monitoring the working process of the control chip by the monitoring circuit;
the control chip monitors the working flow of the monitoring circuit;
controlling the flow of chip reading operation;
controlling the flow of the writing operation of the chip;
and controlling the flow of the chip erasing operation.
As shown in fig. 2, the monitoring workflow of the monitoring circuit to the control chip provided by the embodiment of the present invention includes:
step 1: electrifying, initializing an upper time limit T, initializing a time interval delta T, and starting to monitor the input and output interface;
step 2: waiting for a time Δ T;
and step 3: sending a response signal A to the control chip;
and 4, step 4: if the input/output interface is found to have operation request information for the control chip of the solid state disk, timing is started, a timing variable t =0 is set, the step 5 is switched, and otherwise, the step 2 is switched;
and 5: waiting for delta T time, and increasing the value of T by delta T;
step 6: sending a response signal A to the control chip;
and 7: and if the control chip of the solid state disk returns the operation completion information of the input/output interface, turning to the step 2, otherwise, turning to the step 8.
And 8: if the timing T is more than or equal to T, judging that the control chip generates SEFI, resetting and starting the control chip, and turning to the step 2; otherwise go to step 5.
As shown in fig. 3, the monitoring work flow of the monitoring circuit by the control chip provided by the embodiment of the present invention includes;
step 1: powering on, initializing a waiting time interval multiple B, and initializing a count m =0;
step 2: waiting for a time Δ T;
and 3, step 3: if the response signal A sent by the monitoring circuit is received, setting m =0, turning to step 2, otherwise, increasing the value of m by 1, and turning to step 4;
and 4, step 4: if m is greater than B, judging that the monitoring circuit has SEFI, resetting and starting the monitoring circuit, setting m =0, and turning to the step 1; otherwise, turning to the step 2.
Preferably, the monitoring circuit may determine the operation request type of the input/output interface to the solid state disk control chip, and set different upper limit of completion time for different operation request types.
Preferably, the Δ T is configured to range from 1 millisecond to 10 seconds according to the anti-SEFI characteristics of the monitoring circuit and the control chip, so as to ensure that the monitoring circuit and the control chip cannot simultaneously generate SEFI.
Referring to fig. 4, the flow of the control chip read operation provided in the embodiment of the present invention includes;
step 1: receiving a read request of an input/output interface to a logical block address P0;
step 2: and performing a first read operation:
step 201: converting the logical block address P0 into a physical block address P1;
step 202: reading data Q1 of a physical block address P1 from the flash memory array;
and 3, step 3: and performing a second read operation:
step 301: converting the logical block address P0 to a physical block address P2;
step 302: reading data Q2 of the physical block address P2 from the flash memory array;
and 4, step 4: comparing whether P1= P2 and Q1= Q2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: and performing a third read operation:
step 501: converting the logical block address P0 into a physical block address P3;
step 502: reading data Q3 of a physical block address P3 from the flash memory array;
step 6: comparing whether P1= P3 and Q1= Q3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3 and Q2= Q3, if so, turning to step 9, otherwise, judging that SEFI occurs and cannot be recovered, returning that the read operation of the input/output interface fails, and ending;
and 8: returning the input/output interface data Q1, and ending;
and step 9: returning the input/output interface data Q2, and ending
Referring to fig. 5, the flow of the control chip write operation provided by the embodiment of the present invention includes.
Step 1: receiving a write request of writing data Q0 into a logical block address P0 by an input/output interface;
step 2: converting the logical block address P0 into a physical block address P1;
and step 3: converting the logical block address P0 to a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 into a physical block address P3;
step 6: comparing whether P1= P3, if so, turning to step 8, otherwise, turning to step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning to the failure of the write operation of the input/output interface;
and 8: writing the data Q0 into a physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: writing the data Q0 into a physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: reading data Q1 of a physical block address P2 from the flash memory array, and turning to step 12;
step 12: comparing whether Q0= Q1, if so, returning that the write operation of the input/output interface is completed; otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, and returning that the write operation of the input/output interface fails
As shown in fig. 6, the flow of controlling the chip erase operation provided in the embodiment of the present invention includes:
step 1: receiving an erasing request of an input/output interface to a logical block address P0;
step 2: converting the logical block address P0 into a physical block address P1;
and step 3: converting the logical block address P0 into a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 into a physical block address P3;
step 6: comparing whether P1= P3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning that the input/output interface erasing operation fails;
and 8: erasing the physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: erasing the physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: reading data Q1 of a physical block address P2 from the flash memory array, and turning to step 12;
step 12: whether Q1 is completely erased or not, if so, returning to the completion of the erasing operation of the input/output interface; otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, and returning that the input/output interface erasing operation fails.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.
Claims (8)
1. The utility model provides an anti single event interruption's solid state disk, includes solid state disk (5), its characterized in that: a control chip (1) is arranged inside the solid state disk (5), one side of the control chip (1) is connected with a flash memory array (2), one sides of the control chip (1) and the flash memory array (2) are connected with an input/output interface (4), and one side of the control chip (1) far away from the control chip (1) is also connected with a monitoring circuit (3);
the monitoring work flow of the monitoring circuit to the control chip comprises the following steps:
step 1: electrifying, initializing an upper time limit T, initializing a time interval delta T, and starting to monitor the input and output interface;
and 2, step: waiting for a time Δ T;
and step 3: sending a response signal A to the control chip;
and 4, step 4: if the input/output interface is found to have operation request information for the control chip of the solid state disk, timing is started, a timing variable t =0 is set, the step 5 is switched, and otherwise, the step 2 is switched;
and 5: waiting for delta T time, and increasing the value of T by delta T;
step 6: sending a response signal A to the control chip;
and 7: if the control chip of the solid state disk returns the operation completion information of the input/output interface, turning to the step 2, otherwise, turning to the step 8;
and step 8: if the timing T is more than or equal to T, judging that the control chip generates SEFI, resetting and starting the control chip, and turning to the step 2; otherwise, turning to the step 5;
the monitoring work flow of the control chip to the monitoring circuit comprises the following steps:
step 1: powering on, initializing a waiting time interval multiple B, and initializing a count m =0;
step 2: waiting for a time Δ T;
and step 3: if a response signal A sent by the monitoring circuit is received, setting m =0, turning to step 2, otherwise increasing the value of m by 1, and turning to step 4;
and 4, step 4: if m is>B, judging that the monitoring circuit generates SEFI, resetting and starting the monitoring circuit, setting m =0, and turning to the step1(ii) a Otherwise, turning to the step 2.
2. The solid state disk resisting the single event functional interruption of claim 1, wherein: the control chip (1), the flash memory array (2), the monitoring circuit (3) and the input/output interface (4) are electrically connected with each other.
3. The solid state disk resisting the single event functional interruption of claim 1, wherein: the method comprises the following steps:
the monitoring circuit monitors the working process of the control chip;
the control chip monitors the working flow of the monitoring circuit;
the flow of the read operation of the control chip;
the flow of the write operation of the control chip;
and controlling the flow of chip erasing operation.
4. The solid state disk resisting the single event functional interruption of claim 1, wherein: the monitoring circuit can judge the operation request type of the input/output interface to the solid state disk control chip, and set different upper limit of the completion time aiming at different operation request types.
5. The solid state disk resisting the single event functional interruption of claim 4, wherein: according to the SEFI resistance characteristics of the monitoring circuit and the control chip, the delta T is configured within the range of 1 millisecond to 10 seconds, and the monitoring circuit and the control chip are ensured not to simultaneously generate SEFI.
6. The solid state disk resisting single event functional interruption according to claim 3, wherein: the control chip reading operation process comprises the following steps:
step 1: receiving a read request of an input/output interface to a logical block address P0;
step 2: and (3) carrying out a first read operation:
step 201: converting the logical block address P0 into a physical block address P1;
step 202: reading data Q1 of a physical block address P1 from the flash memory array;
and step 3: and performing a second read operation:
step 301: converting the logical block address P0 to a physical block address P2;
step 302: reading physical block address P from flash memory array2The data Q2 of (1);
and 4, step 4: comparing whether P1= P2 and Q1= Q2, if so, turning to the step8Otherwise, turning to the step 5;
and 5: and carrying out a third read operation:
step 501: converting the logical block address P0 to a physical block address P3;
step 502: reading from flash memory arrayOut of physical block addressP3The data Q3 of (a);
step 6: comparing whether P1= P3 and Q1= Q3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3 and Q2= Q3, if yes, turning to the step9Otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, returning that the read operation of the input/output interface fails, and ending;
and 8: returning the input/output interface data Q1, and ending;
and step 9: and returning the input/output interface data Q2, and ending.
7. The solid state disk resisting the single event functional interruption of claim 3, wherein: the control chip write operation flow comprises the following steps;
step 1: receiving a write request of writing data Q0 into a logical block address P0 by an input/output interface;
step 2: converting the logical block address P0 into a physical block address P1;
and 3, step 3: converting the logical block address P0 to a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 to a physical block address P3;
step 6: comparing whether P1= P3, if so, turning to step 8, otherwise, turning to step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning to the failure of the write operation of the input/output interface;
and 8: writing the data Q0 into a physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: writing the data Q0 into a physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: reading data Q1 of a physical block address P2 from the flash memory array, and turning to step 12;
step 12: comparing whether Q0= Q1, if so, returning that the write operation of the input/output interface is completed; otherwise, judging that the SEFI occurs and the SEFI cannot be recovered, and returning that the write operation of the input/output interface fails.
8. The solid state disk resisting the single event functional interruption of claim 3, wherein: the flow of the control chip erasing operation comprises the following steps:
step 1: receiving an erasing request of an input/output interface to a logical block address P0;
step 2: converting the logical block address P0 into a physical block address P1;
and 3, step 3: converting the logical block address P0 into a physical block address P2;
and 4, step 4: comparing whether P1= P2, if so, turning to the step 8, otherwise, turning to the step 5;
and 5: converting the logical block address P0 to a physical block address P3;
and 6: comparing whether P1= P3, if so, turning to the step 8, otherwise, turning to the step 7;
and 7: comparing whether P2= P3, if so, turning to step 9, otherwise, judging that SEFI occurs and the SEFI cannot be recovered, and returning that the input/output interface erasing operation fails;
and 8: erasing the physical block address P1 of the flash memory array, and turning to the step 10;
and step 9: erasing the physical block address P2 of the flash memory array, and turning to the step 11;
step 10: reading data Q1 of a physical block address P1 from the flash memory array, and turning to step 12;
step 11: the data Q1 of the physical block address P2 is read from the flash memory array, step 12.
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