CN113452365B

CN113452365B - Automatic frequency correction circuit and correction method suitable for under-sampling phase-locked loop

Info

Publication number: CN113452365B
Application number: CN202110760825.3A
Authority: CN
Inventors: 孔祥键; 郭春炳; 高钧达; 陆维立
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2021-07-05
Filing date: 2021-07-05
Publication date: 2022-08-09
Anticipated expiration: 2041-07-05
Also published as: CN113452365A

Abstract

The invention discloses an automatic frequency correction circuit and a correction method suitable for an under-sampling phase-locked loop, which utilize the behavior characteristics of a phase discriminator with dead zones in the under-sampling phase-locked loop to judge frequency control words and utilize sequential logic to realize automatic calibration of the control words; the conventional closed loop AFC is calibrated by disconnecting the phase-locked loop to count the reference frequency and the output frequency versus the number of pulses in a certain time, which has the disadvantage that each calibration requires the disconnection of the loop to increase the locking time; the open-loop AFC judges whether a control word is calibrated or not by comparing a control line voltage Vctl through a comparator and adjusts the control word through a sequential logic, and has the defects that the control line voltage Vctl is utilized, and the noise of the comparator is coupled to a control line to provide more phase noise for a voltage-controlled oscillator VCO; the invention avoids the defects of the two, uses the mode of counting the output pulses of the phase discriminator with dead zone and realizes the function of automatically calibrating the VCO control word of the under-sampling phase-locked loop in continuous time.

Description

Automatic frequency correction circuit and correction method suitable for under-sampling phase-locked loop

Technical Field

The invention relates to the field of integrated circuit design, in particular to an automatic frequency correction circuit and a correction method suitable for an under-sampling phase-locked loop.

Background

Due to the rapid development of 5G millimeter wave radio frequency equipment and high-speed transmission technology, most of frequency synthesizers used as local oscillators in the radio frequency equipment are based on a phase-locked loop architecture, and in the high-speed transmission technology, a phase-locked loop is also used as an essential clock source to provide a stable and accurate clock for circuits. In the standard for evaluating the quality of a phase-locked loop, the parameters of the phase-locked loop, such as frequency modulation range, phase noise, power consumption and the like, are mainly concerned. The radio frequency millimeter wave field has extremely high requirements on phase noise, and a ring oscillator used in the traditional phase-locked loop cannot meet the requirements. Therefore, LC oscillators are used in frequency synthesizers which are mainly used in millimeter-wave local oscillators in academia and industry. The LC oscillator can achieve lower phase noise performance, but introduces another disadvantage, and through analysis of the transfer function of the phase-locked loop, an excessively large voltage-frequency Kvco transfer coefficient may generate a large output jitter, and is also not favorable for locking of the phase-locked loop. To solve this problem, a LC voltage-controlled oscillator in a phase-locked loop is typically operated in a suitable range using discrete digital bits and a continuous control voltage. Generally, a circuit without an automatic calibration control word needs to adjust a control bit by debugging from the outside of a chip to enable a voltage-controlled oscillator to work in a proper range.

The most widely known of the existing similar techniques are the closed-loop AFC technique and the open-loop AFC technique.

Open-loop AFC technique: when the phase-locked loop is started, the loop is disconnected, the VCO free oscillation count and the reference clock count are counted, the numerical difference value of the two counters is compared to change the VCO control bit change, and finally the locking of the closed loop is realized. The problems of the technology are as follows: the realization is complicated, the change of the bit position needs to be realized by disconnecting the phase-locked loop, thereby prolonging the phase-locked time, when the reference clock is changed or the frequency dividing ratio of the frequency divider is changed, the bit position can be determined again only by disconnecting the loop, and the bit position can not be adjusted dynamically.

Closed loop AFC technique: two comparators are connected to a phase-locked loop control line voltage Vctl, comparison voltages are connected to two ends of the comparators, and when the control line voltage is lower than or higher than a certain voltage, the logic circuit enables the digital control bit to rise or fall by one bit. This technique has the disadvantage of using a control line voltage which is very sensitive and directly controls the frequency of the VCO, and the comparator feed-through causes ripple jitter on the control line voltage resulting in worse clock jitter.

Disclosure of Invention

The invention aims to solve the technical problem of providing an automatic frequency correction circuit and a correction method suitable for an under-sampling phase-locked loop, which can realize continuous calibration of a phase-locked loop control word in continuous time.

In order to realize the task, the invention adopts the following technical scheme:

the utility model provides a be applicable to undersampled phase-locked loop automatic frequency correction circuit, includes undersampled phase-locked loop circuit and calibration circuit, wherein:

the phase-locked loop circuit comprises an under-sampling phase discriminator, a first charge pump, a pulse generator, a loop filter and a voltage-controlled oscillator, wherein the under-sampling phase discriminator, the first charge pump, the loop filter and the voltage-controlled oscillator are sequentially connected, the pulse generator is connected to the first charge pump, and a reference signal Vref is respectively connected to the under-sampling phase discriminator and the pulse generator; the output end of the voltage-controlled oscillator is connected to the under-sampling phase discriminator and the frequency divider;

the calibration circuit comprises a dead-zone phase detector, a digital circuit and a second charge pump, wherein the reference signal Vref is connected to the dead-zone phase detector, and the output signal of the dead-zone phase detector enters the second charge pump on one hand and enters the digital circuit on the other hand; the output of the digital circuit is connected to the voltage-controlled oscillator; the output of the voltage controlled oscillator generates a frequency divided signal Vdiv through a frequency divider and enters the dead band phase detector.

Further, the automatic frequency correction circuit suitable for the under-sampling phase-locked loop comprises two loops: a sampling phase-locked loop (SSPLL) and a frequency-locked loop (FLL);

the frequency locking loop FLL comprises the dead zone phase discriminator, a second charge pump, a loop filter, a frequency divider and a voltage-controlled oscillator; firstly, the frequency difference between an input reference signal Vref and an output signal Vvdiv of a frequency divider is identified, a dead zone phase discriminator can generate output signals up and down to control the charge and discharge of a second charge pump to a loop filter, so that the continuous tuning voltage output by the loop filter to a voltage-controlled oscillator is influenced, a frequency locking loop FLL has a coarse locking function and assists the locking of an under-sampling phase-locked loop SSPLL;

the SSPLL comprises an under-sampling phase discriminator, a pulse generator, a first charge pump, a loop filter and a voltage-controlled oscillator; after the coarse locking of the frequency locking loop is carried out, at the moment, the frequency of Vref is the same as that of Vdiv, but the phase is different, the SSPLL directly utilizes the output of the voltage-controlled oscillator to feed back to the under-sampling phase discriminator, so that the charging and discharging of the first charge pump to the loop filter are controlled through the sampling phase discriminator and the pulse generator, the continuous tuning voltage Vctl of the VCO is changed, and the complete phase locking is finally realized.

Further, when the phase is locked, the frequency locking loop FLL stops working, the input of the dead zone phase detector is the frequency division signal Vdiv output by the frequency locking loop FLL and the input reference signal Vref, the output signal signals up and down are supplied to the loop filter and the digital circuit, and the digital circuit operates and then supplies a bit signal to the tuning control word end of the voltage-controlled oscillator.

Further, the dead zone phase detector includes 4D flip-

flops

101, 102, 105, 106 and 2 voltage-controlled

delay units

103, 104, input terminals D of the D flip-

flops

101 and 102 are connected to a high level, the voltage-controlled

delay units

103, 104 are connected to a control voltage Vbias, a reference signal Vref is connected to the

units

101 and 103, a frequency division signal Vdiv output by the frequency locking loop FLL is connected to D terminals of the D flip-flop 102 and the voltage-controlled delay unit 104, output terminals Q of the D flip-

flops

101 and 102 are respectively connected to D terminals of the D flip-

flops

105 and 106 and simultaneously connected to an input terminal of an and gate, an output terminal of the and gate is connected to reset terminals of the D flip-

flops

101 and 102, and output terminals of the D flip-

flops

105 and 106 are connected to input terminals of the and gate

The terminals output signals up and down, respectively.

Further, the digital circuit includes two N-

bit counters

201 and 202, two pulse generators 203 and 204, an M-bit addition logic unit 205, an M-bit subtraction logic unit 206, two delays 207 and 208, two M-bit forward clock D flip-

flops

209 and 210, two M-bit inverted clock D flip-

flops

211 and 212, and an M-bit two-way selector 213;

output signals down and up of the dead zone phase detector are respectively connected to the input ends of the

counters

201 and 202, and the output ends of the

counters

201 and 202 are respectively connected to the input ends of the pulse generators 203 and 204; 203 to the summing logic 205 and to one of the delay units 207, 204 to the subtracting logic and to the other delay unit 208, the output of the delay unit 207 to the clock inputs of 209 and 211 and the output of the delay unit 208 to the clock inputs of 210 and 212; the outputs of the addition logic 205 and the addition logic 206 are respectively connected to the input terminals of the D flip-flop 209 and the D flip-flop 210, and finally the outputs of the D flip-flop 211 and the D flip-flop 212 are connected to the input terminal of the M-bit two-way selector 213, while the output of 213 is the control word of the VCO, and is fed back to the input terminals of 205 and 206 as the base number of the next calculation.

An automatic frequency correction method suitable for an undersampled phase-locked loop comprises the following steps:

step 1, inputting reference signals Vref and Vdiv into a dead zone phase discriminator, and when a VCO (voltage controlled oscillator) tuning control word is inaccurate, the dead zone phase discriminator can generate periodic pulses on an output signal up or down;

step 2, connecting the down and up signals to a Digital circuit Digital, judging and calibrating through Digital sequential logic, automatically searching for an accurate control word when the tuning control word of the VCO is judged to be inaccurate, and transmitting the accurate control word to the VCO;

and 3, aligning the VCO control word with the actual control word, locking the SSPLL, stopping the FLL from working, stopping the up and down from generating pulses, and judging that the VCO control word is calibrated by the

counters

201 and 202 without capturing any pulse message.

Further, in step 2, when the down and up signals have periodic pulses, the N-

bit counter

201 or 202 accumulates the pulses, if the down or up signal occurs N times, it is determined that the frequency control word of the phase-locked loop is out of control, and at this time, a pulse signal is generated to the M-bit addition logic unit 205 or the M-bit subtraction logic unit 206, after the M-bit addition logic unit 205 or the M-bit subtraction logic unit 206 performs operation, the delay unit 207, the delay unit 208, the D flip-flop 209, the D flip-flop 210, the D flip-flop 211, and the D flip-flop 212 only let the M-bit addition logic 205 or the M-bit subtraction logic 206 execute one time, and the output result of the M-bit addition logic 205 or the M-bit subtraction logic 206 is updated to the tuning control word of the VCO by the M-bit two-way selector 213 and the inputs of the M-bit addition logic 205 or the M-bit subtraction logic 206 are updated as the base number of the next calculation.

Compared with the prior art, the invention has the following technical characteristics:

the calibration technology combines the advantages of the two traditional calibration technologies and eliminates part of the defects, the calibration technology can realize real-time calibration without disconnecting a loop, so that the calibration time is greatly prolonged, and meanwhile, the voltage of Vctl is not required to be utilized, the voltage of the Vctl is a very sensitive voltage line of the phase-locked loop, and the voltage is prevented from being utilized to ensure the purity of the voltage.

Drawings

FIG. 1 is a schematic diagram of a calibration circuit connected to an under-sampled phase-locked loop circuit;

FIG. 2 is a dead-band phase discriminator configuration implemented by the present invention;

FIG. 3 is a diagram of a Digital circuit Digital according to an embodiment of the present invention;

fig. 4 is a working illustration picture 1 of a dead-zone phase detector implemented in the present invention;

fig. 5 is a working illustration picture 2 of a dead-zone phase detector implemented in the present invention;

FIG. 6 is a response to an out-of-lock condition of an under-sampled phase-locked loop incorporating a dead-zone phase detector;

FIG. 7 is a circuit for implementing digital sequential logic in Cadence according to the present invention;

FIG. 8 is a digital sequential logic simulation result of the present invention;

FIG. 9 illustrates a true undersampled PLL circuit in accordance with the present invention;

FIG. 10 shows the simulation result of the true under-sampled PLL circuit applied in the present invention.

Detailed Description

Referring to fig. 1, an automatic frequency correction circuit for an under-sampled phase-locked loop includes an under-sampled phase-locked loop circuit and a calibration circuit, wherein:

the phase-locked loop circuit comprises an under-sampling phase discriminator SSPD, a first charge pump CP, a pulse generator Pulser, a loop filter LP and a voltage-controlled oscillator VCO, wherein the under-sampling phase discriminator, the first charge pump CP, the loop filter and the voltage-controlled oscillator are sequentially connected, the pulse generator is connected to the first charge pump, and a reference signal Vref is respectively connected to the under-sampling phase discriminator and the pulse generator; the output of the VCO of the voltage controlled oscillator is connected to the under-sampling phase detector SSPD and the frequency divider/N.

The calibration circuit comprises a dead-zone phase detector PFD w/i DZ and a Digital circuit Digital, wherein the reference signal Vref is connected to the dead-zone phase detector, and an output signal up/down of the dead-zone phase detector enters a second charge pump on one hand and enters the Digital circuit on the other hand; the output of the digital circuit is connected to the voltage-controlled oscillator; the output of the voltage controlled oscillator generates a frequency divided signal Vdiv through a frequency divider and enters the dead band phase detector.

The invention comprises two loops, namely an under-sampling phase-locked loop (SSPLL) and a frequency-locked loop (FLL):

the frequency locking loop FLL comprises the dead zone phase discriminator, a second charge pump, a loop filter, a frequency divider and a voltage-controlled oscillator; firstly, the frequency difference between an input reference signal Vref and an output signal Vvdiv of the frequency divider is identified, the dead zone phase discriminator can generate output signals up and down to control the charge and discharge of the second charge pump CP to the loop filter LF, so that the continuous tuning voltage output by the loop filter LF to the voltage controlled oscillator VCO is influenced, and the frequency locking loop FLL has a coarse locking function and assists in the locking of the SSPLL.

The under-sampling phase-locked loop SSPLL comprises an under-sampling phase discriminator SSPD, a first charge pump CP, a loop filter LF and a voltage-controlled oscillator VCO; after the rough locking of the frequency locking loop FLL, at the moment, the frequency of Vref is the same as that of Vdiv, but the phase is different, the output of the VCO can be directly utilized by the SSPLL of the under-sampling phase locking loop SSPLL to feed back to the SSPD of the under-sampling phase detector, so that the charging and discharging of the first charge pump CP to the loop filter LF are controlled through the SSPD of the sampling phase detector, the continuous tuning voltage Vctl of the VCO is changed, and the complete phase locking is finally realized; the frequency locking loop FLL also stops working when the phase is locked, the input of the dead zone phase discriminator is a frequency division signal Vdiv output by the frequency locking loop FLL and a reference signal Vref, an output signal up/down is sent to a loop filter LF and a Digital circuit Digital, and the Digital circuit sends a bit signal to a tuning control word end of a voltage controlled oscillator VCO after operation, so that the frequency locking loop FLL stops working when locked, then the calibration circuit also stops working, no useful signal enters the calibration circuit, and the performance of the phase-locked loop is ensured when normally locked; in particular, the loop filter and the voltage controlled oscillator of both loops are common.

Referring to fig. 2, a schematic structural diagram of the dead-zone phase detector PFD w/i DZ according to the present invention is shown.

The dead zone phase detector comprises 4D triggers (101, 102, 105, 106) and 2 voltage-controlled delay units (103, 104), wherein input ends D of the

D triggers

101 and 102 are connected to a high level, the voltage-controlled

delay units

103 and 104 are connected to a control voltage Vbias, a reference signal Vref is connected to the

units

101 and 103, a frequency division signal Vdiv output by a frequency locking loop FLL is connected to the D ends of the D triggers 102 and the voltage-controlled delay unit 104, output ends Q of the

D triggers

101 and 102 are respectively connected to the D ends of the input ends of the

D triggers

105 and 106 and are simultaneously connected to the input end of an AND gate, the output end of the AND gate is connected to the reset ends of the

D triggers

101 and 102, and the output ends of the

D triggers

105 and 105 are connected to the reset ends of the

D triggers

101 and 102

The terminals output signals UP and DOWN respectively, so that the voltage controllable phase discriminator with the dead zone is connected.

The voltage-controlled

delay units

103 and 104 are voltage-controlled delay modules, and have the following functional relationship:

Δt＝f(Vbias) (1)

Δ t is the time amount of the delay, Vbias is the control voltage, the function shows that the delay amount of the delay unit is related to the input control voltage Vbias, i.e. the delay amount Δ t is controlled by the voltage Vbias when Vref and Vdiv have a certain phase difference, and the absolute phase difference | Δ θ | of Vref and Vdiv is equal to the absolute phase difference | Δ θ | in the time domainCorresponding Vref and Vdiv rising edge time difference Deltat _|Δθ| There is the following linear relationship:

where f denotes the clock frequency, when Δ t _|Δθ| At < Δ t, the signals passed by 101 and 102 to 105 and 106, 101 and 102, have been reset by the output of the and gate before the delayed rising edges activate 105 and 106 to flip their outputs, thus indicating no change in the output Q of 105 and 106, and the up and down signals are inverted, at which point the phase detector fails. Vice versa, when Δ t _|Δθ| At > Δ t, the phase detector can discriminate the phase difference between Vref and Vdiv, with the up and down signals in phase.

Fig. 3 shows simulation results for the dead-zone phase detector, where Δ t is set to 5ns by equation (1), as shown in fig. 4 _|Δθ| When 2.778ns, the up and down signals are inverted, that is, the phase detector cannot distinguish the phase difference between the input signals Vref and Vdiv; when Δ t is shown in FIG. 5 _|Δθ| At 8.331ns, the up and down signals are in phase, i.e., the phase detector is now successful in discriminating the phase difference.

Fig. 3 is a schematic diagram of a Digital circuit Digital according to the present invention.

The digital circuit comprises two N-bit counters (201 and 202), two pulse generators (203 and 204), an M-bit addition logic unit 205, an M-bit subtraction logic unit 206, two time delays (207 and 208), two M-bit forward clock D flip-flops (209 and 210), two M-bit reverse clock D flip-flops (211 and 212) and an M-bit two-way selector (213); the output signals down and up of the dead zone phase detector are respectively connected to the input ends of the

counters

201 and 202. The outputs of 201 and 202 are coupled to the inputs of pulse generators 203 and 204, respectively. 203 is connected to the addition logic unit 205 and to the output of a delay unit 207, 204 is connected to the subtraction logic unit and to a delay unit 208, the output of the delay unit 207 is connected to the clock input of 209 and 211 and the output of the delay unit 208 is connected to the clock input of 210 and 212, the outputs of 205 and 206 are connected to the input D of 209 and 210, respectively, and finally the outputs of 211 and 212 are connected to the input of an M-Bit two-way selector 213, and the output Bit [0: M-1] of 213 is the control word of the voltage-controlled oscillator VCO, and is fed back to the input Bit [0: M-1] of 205 and 206 as the base number for the next calculation.

The M-Bit addition logic 205 is a logic operation, when the a input is 1, Bit _ next [0: M-1] +1, that is, when the a input is 1, the next Bit _ next [0: M-1] adds 1 to the current Bit [0: M ] in the binary field, for example, when the Bit [0:2] + 101, then the next Bit _ next [0:2] + 110 when the a input is 1. When the a-side input is 0, Bit _ next [0: M-1] ═ Bit [0: M-1 ]. And I is an overflow Bit, when Bit [0: M-1] reaches the maximum value D and still an input signal arrives, the overflow Bit I of the addition unit indicates high level and stops working. The M-Bit subtraction logic 206 is also a logic operation, when the a-side input is 1, Bit _ next [0: M-1] ═ Bit [0: M-1] -1, when the a-side input is 0, Bit _ next [0: M-1] ═ Bit [0: M-1], and similarly, when the a-side input is 1, Bit _ next [0: M-1] subtracts Bit [0: M ] from the binary field by 1 and I is an overflow Bit, for example, Bit [0:2] ═ 101, when the a-side input is 1, Bit _ next [0:2] ═ 100, when the minimum value of Bit [0: M-1] reaches 0, and D still has an input signal arriving, the overflow Bit I of the subtraction unit is indicated as high and stops working.

Table 1 gives the logical truth table of the 3-bit addition unit and table 2 gives the logical truth table of the 3-bit subtraction unit. Because 205 and 206 are static logic blocks, the

units

207, 208, 209, 210, 211, 212, etc. are used to make the addition and subtraction digital logic become sequential logic, for example, when there is an impulse response adding unit 205, and the delay unit 207 outputs the rising edge of the impulse after the adding unit performs the calculation addition, the result of the addition is stored in 209, and then since the result of 209 is stored in 211 when the falling edge of the impulse comes, it can be guaranteed that each impulse adding logic 205 or subtraction logic 206 is only performed once.

TABLE 1

TABLE 2

FIG. 7 shows a simulation circuit diagram of a digital circuit, while FIG. 8 shows that simulation results, Clk _ up, are 203-unit outputs, Clk _ down is 204-unit output waveforms, each time a down-down pulse reaches 8 bits, a pulse is generated in Clk _ up, which causes output Bit [0:2] to go from <000> (which corresponds to 0 in the diagram) to <001> (which corresponds to 1 in the diagram) so that successive down-down pulses cause final Bit [0:2] to reach <111> (which corresponds to 7 in the diagram), and then the down-pulse signal is stopped, generating pulses for the up signal, and similarly, the up-pulse signal accumulation causes Bit [0:2] to go from <111> to <000 >. Thus, automatic traversal of the VCO control word is achieved, which can be accomplished under normal operating conditions without the need to break the loop.

The invention further provides an automatic frequency correction method suitable for the under-sampling phase-locked loop, which corrects the VCO tuning control word by taking the periodic signal output by the dead zone phase discriminator as a criterion, and comprises the following specific steps:

step 1, reference signals Vref and Vdiv are input into a dead-zone phase detector, and when a VCO (voltage controlled oscillator) tuning control word is inaccurate, the dead-zone phase detector generates periodic pulses in an output signal up or down.

In step 1, when the locking frequency is not in the current VCO control word, that is, the VCO tuning control word is not accurate now, the pll cannot be locked, which is caused by the VCO not being calibrated, and when the pll cannot be locked, when Vref and Vdiv are input to the dead-band phase detector, the following processes are performed:

(1) since Vref and Vdiv have a certain phase difference, but the phase difference still cannot satisfy the dead zone Δ t (vbias) controlled by voltage, the time for resetting the and gate is faster than the time for the signals of Vref and Vdiv to reach 105 or 106 after the time delay, in other words, the time difference caused by the phase difference is already larger than the time delay difference, and the output signals up and down at 105 and 106 are not changed in phase inversion.

(2) Since Vref and Vdiv fall in different frequency ranges, the phase difference is accumulated continuously, and when the phase difference satisfies Δ t _|Δθ| If the difference is larger than Δ t, the Vref and Vdiv signals delayed at this time can reach 105 or 106, because the time difference caused by the phase difference is larger than the delay time difference, the up and down signals output by 105 and 106 are in phase, and the phase difference continues to accumulate until the phase difference meets 360 degrees, then the process (1) is returned.

In this way, the output behavior of the dead-zone phase detector is periodically pulsed on the up signal or the down signal. As shown in fig. 6, Vctl is a control voltage of the VCO, and the voltage positively affects the oscillation frequency, that is, the higher the frequency of Vctl is, it is seen that Vctl is already close to 0 but still cannot meet the locking requirement, that is, the control word needs to be adjusted up if the control word is inaccurate. The up signal appears as a periodic pulse when the output Vdiv frequency is lower than the reference Vref frequency, and similarly, the down signal appears as a periodic pulse when the output Vdiv frequency is higher than the reference Vref frequency.

And 2, connecting the down and up signals to a Digital circuit Digital, judging and calibrating through Digital sequential logic, and automatically searching for an accurate control word and transmitting the accurate control word to the VCO when the tuning control word of the VCO is judged to be inaccurate.

In this step, when a periodic pulse occurs in the down and up signals, 201 or 202 accumulates the pulse, if the down or up signals occur N times, it is determined that the frequency control word of the phase-locked loop is out of control, at this time, a pulse signal is generated to the addition logic 205 or the subtraction logic 206, after the addition logic or the subtraction logic performs the operation, since the above-mentioned 207, 208, 209, 210, 211, 212 only performs the operation once on 205 or 206, the output result of 205 or 206 is updated to the tuning control word of the VCO by the 3-Bit data selector 213, and the input Bit [0:2] of 205 and 206 is updated as the base for the next calculation.

Simulation verification is given for step 2; FIG. 7 shows a simulation circuit diagram of a digital circuit, while FIG. 8 shows that simulation results, Clk _ up, are 203-unit outputs, Clk _ down is 204-unit output waveforms, each time a down-down pulse reaches 8 bits, a pulse is generated in Clk _ up, which causes output Bit [0:2] to go from <000> (which corresponds to 0 in the diagram) to <001> (which corresponds to 1 in the diagram) so that successive down-down pulses cause final Bit [0:2] to reach <111> (which corresponds to 7 in the diagram), and then the down-pulse signal is stopped, generating pulses for the up signal, and similarly, the up-pulse signal accumulation causes Bit [0:2] to go from <111> to <000 >. Thus, automatic traversal of the VCO control word is achieved, which can be accomplished under normal operating conditions without the need to break the loop.

For further example, when the VCO control word is lower than the control word for locking the frequency, assuming that the VCO control word is <000> and the actual accurate control word is <010> (i.e., Vdiv is higher than Vref), the dead zone phase detector may generate a down periodic signal. Therefore, the down periodic pulse responds to the pulse generator 203, and causes the pulse generator to trigger the

addition timing units

205, 207, 209, 211, 205 to output <001> which is updated to the VCO control word through the data selector 213, but <001> still does not meet the requirement, the down periodic signal continues to be generated, and then the

addition timing units

205, 209, 211, 205 continue to be triggered to output <010>, and similarly, when the VCO control word is higher than the control word of the locking frequency (i.e., Vdiv is higher than the frequency of Vref), the dead zone phase detector generates the periodic up signal at this time, and triggers 206, 208, 210, 212 in response to the dead zone phase detector 204 to drop the control word.

counters

201 and 202 without capturing any pulse message.

Example (b):

fig. 9 shows an SSPLL of self-contained design, where a 3-bit calibration circuit is placed in the SSPLL, and it has been verified that when the input reference voltage is 56M, the division ratio is 64, and the locking frequency is 3.584G, the bit of the VCO should be calibrated at <1010>, but the output frequency is intentionally set at <1001>, i.e. the output frequency is higher than the input frequency. According to the above analysis, down produces periodic pulses, and it can be seen that in fig. 10 down does produce periodic downward pulses. Then, according to the logic of the phase locked loop, when the output frequency is higher than the input frequency, the bit of the VCO should be decreased downwards to meet the locking requirement, and the accumulation of the down pulse signal in fig. 6 triggers the subtraction logic to achieve the bit decrease.

As shown in fig. 10, before 14us, the VCO cannot be normally locked, the output frequency can only reach 3.61GHz at the lowest, Vctl generates periodic jitter, and at the same time, the DOWN signal has periodic pulses, the calibration circuit counts the DOWN pulse signal, when 8 periods are reached, the Bit of the VCO is changed, the Bit is changed, and the phase-locked loop is locked at 18us from <1001> to <1001> (that is, in the figure, Bit0 is 0, Bit1 is 0, and Bit2 is 0). The VCO output frequency at this time is 3.584GHz and the lock frequency is reached.

The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. An automatic frequency correction circuit suitable for an under-sampling phase-locked loop, comprising a phase-locked loop circuit and a calibration circuit, wherein:

the calibration circuit comprises a dead zone phase detector and a digital circuit, wherein the reference signal Vref is connected to the dead zone phase detector, and the output signal of the dead zone phase detector enters the second charge pump on one hand and enters the digital circuit on the other hand; the output of the digital circuit is connected to the voltage-controlled oscillator; the output of the voltage-controlled oscillator generates a frequency division signal Vdiv through a frequency divider and enters the dead zone phase detector; the output of the second charge pump is connected with a loop filter;

the digital circuit comprises an N-bit counter 201, an N-bit counter 202, a pulse generator 203, a pulse generator 204, an M-bit addition logic unit (205), an M-bit subtraction logic unit (206), a time delay 207, a time delay 208, an M-bit forward clock D trigger 209, an M-bit forward clock D trigger 210, an M-bit reverse clock D trigger 211, an M-bit reverse clock D trigger 212 and an M-bit two-way selector (213);

output signals down and up of the dead zone phase detector are respectively connected to input ends of an N-bit counter 201 and an N-bit counter 202, and output ends of the N-bit counter 201 and the N-bit counter 202 are respectively connected to input ends of a pulse generator 203 and a pulse generator 204; the output end of the pulse generator 203 is connected to an M-bit addition logic unit (205) and a delay 207, the output end of the pulse generator 204 is connected to an M-bit subtraction logic unit (206) and another delay 208, the output end of the delay 207 is connected to the clock input ends of an M-bit forward clock D flip-flop 209 and an M-bit reverse clock D flip-flop 211, the output end of the M-bit forward clock D flip-flop 209 is connected to the input end of the M-bit reverse clock D flip-flop 211, the output end of the M-bit forward clock D flip-flop 210 is connected to the input end of an M-bit reverse clock D flip-flop 212, and the output end of the delay 208 is connected to the clock input ends of the M-bit forward clock D flip-flop 210 and the M-bit reverse clock D flip-flop 212; the outputs of the M-bit addition logic unit (205) and the M-bit subtraction logic unit (206) are respectively connected to the input ends of an M-bit forward clock D flip-flop 209 and an M-bit forward clock D flip-flop 210, and finally the output ends of an M-bit inverted clock D flip-flop 211 and an M-bit inverted clock D flip-flop 212 are connected to the input end of an M-bit two-way selector (213), while the output end of the M-bit two-way selector (213) is a control word of a voltage controlled oscillator VCO, and simultaneously feeds back to the input ends of the M-bit addition logic unit (205) and the M-bit subtraction logic unit (206) as a radix number of next calculation.

2. The under-sampled phase-locked loop automatic frequency correction circuit as claimed in claim 1, wherein the under-sampled phase-locked loop automatic frequency correction circuit comprises two loops: an under-sampling phase-locked loop (SSPLL) and a frequency-locked loop (FLL);

the frequency locking loop FLL comprises the dead zone phase discriminator, a second charge pump and a frequency divider; firstly, the frequency difference between Vref and Vdiv is identified, the dead zone phase discriminator can generate an output signal up or down to control the charge and discharge of a second charge pump to a loop filter, so that the continuous tuning voltage output to a voltage-controlled oscillator by the loop filter is influenced, a frequency locking loop FLL has a coarse locking function and assists the locking of an under-sampling phase-locked loop SSPLL;

the SSPLL comprises an under-sampling phase discriminator, a first charge pump, a loop filter and a voltage-controlled oscillator; after the coarse locking of the frequency locking loop is carried out, at the moment, the frequency of Vref is the same as that of Vdiv, but the phase is different, the SSPLL directly utilizes the output of the voltage-controlled oscillator to feed back to the under-sampling phase discriminator, so that the charging and discharging of the first charge pump to the loop filter are controlled through the sampling phase discriminator, the continuous tuning voltage Vctl of the VCO is changed, and the complete phase locking is finally realized.

3. The automatic frequency correction circuit suitable for the under-sampling pll of claim 2, wherein the frequency locked loop FLL stops working during phase locking, the input of the dead-zone phase detector is the frequency-divided signal Vdiv output by the frequency locked loop FLL and the reference signal Vref, the output signal up or down is provided to the loop filter and the digital circuit, and the digital circuit provides a bit signal to the tuning control word of the vco after operation, so that the frequency locked loop FLL stops working during locking, and the calibration circuit stops working, no useful signal enters the calibration circuit, and the performance of the pll during normal locking is ensured.

4. The automatic frequency correction circuit of the under-sampling phase-locked loop according to claim 1, wherein the dead-zone phase detector comprises a D flip-flop 101, a D flip-flop 102, a D flip-flop 105, a D flip-flop 106, a voltage-controlled delay unit 103, and a voltage-controlled delay unit 104, wherein the input terminals D of the D flip-flop 101 and the D flip-flop 102 are connected to a high level, the voltage-controlled delay unit 103 and the voltage-controlled delay unit 104 are connected to a control voltage Vbias, a reference signal Vref is connected to the D flip-flop 101 and the voltage-controlled delay unit 103, a frequency division signal Vdiv outputted by the frequency lock loop FLL is connected to the D terminal of the D flip-flop 102 and the input terminal of the voltage-controlled delay unit 104, the output terminals Q of the D flip-flop 101 and the D flip-flop 102 are respectively connected to the D terminals of the D flip-flop 105 and the D flip-flop 106 and are simultaneously connected to the input terminal of an and gate, the output terminal of the and gate is connected to the reset terminals of the D flip-flop 101 and the D flip-flop 102, the output end of the voltage-controlled delay unit 103 is connected with the clock input end of the D trigger 105, and the output end of the voltage-controlled delay unit 104 is connected with the clock input end of the D trigger 106; of D flip-flop 105

The output signal up is output from the terminal, and the output signal down is output from the Q terminal of the D flip-flop 106.

5. A method for performing automatic frequency correction using the automatic frequency correction circuit for an under-sampled phase-locked loop according to claim 2, comprising the steps of:

step 2, connecting the down and up signals to a digital circuit, judging and calibrating through digital sequential logic, automatically searching for an accurate control word when the tuning control word of the VCO is judged to be inaccurate, and transmitting the accurate control word to the VCO;

and 3, aligning the VCO control word with the actual control word, locking the under-sampling phase-locked loop (SSPLL), stopping the Frequency Locking Loop (FLL) from working, stopping the generation of pulses at both up and down, and judging that the VCO control word is calibrated because the N-bit counter 201 and the N-bit counter 202 do not capture any pulse message.

6. The method according to claim 5, wherein in step 2, when the down and up signals have periodic pulses, the N-bit counter 201 or the N-bit counter 202 accumulates the pulses, and if the down or up signals have N times, it is determined that the frequency control word of the pll is out of control, and then a pulse signal is generated to the M-bit add logic unit (205) or the M-bit subtract logic unit (206), and after the M-bit add logic unit (205) or the M-bit subtract logic unit (206) performs the operation, the delay 207, the delay 208, the M-bit forward clock D flip-flop 209, the M-bit forward clock D flip-flop 210, the M-bit invert clock D flip-flop 211, and the M-bit invert clock D flip-flop 212 only allow the M-bit add logic unit (205) or the M-bit subtract logic unit (206) to perform the operation once, and the output result of the M-bit add logic unit (205) or the M-bit subtract logic unit (206) is selected by the M-bit double-way selection unit The unit (213) will update the tuning control word of the VCO and will update the inputs of the M-bit addition logic (205) and the M-bit subtraction logic (206) as the basis for the next calculation.