CN113451371A - 具有减小的路由线电阻的大面板显示器 - Google Patents

具有减小的路由线电阻的大面板显示器 Download PDF

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Publication number
CN113451371A
CN113451371A CN202110272385.7A CN202110272385A CN113451371A CN 113451371 A CN113451371 A CN 113451371A CN 202110272385 A CN202110272385 A CN 202110272385A CN 113451371 A CN113451371 A CN 113451371A
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China
Prior art keywords
display
pixels
gate
additional
resistance
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CN202110272385.7A
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English (en)
Inventor
小野晋也
林敬伟
A·马祖泰拉
张钧杰
黄戎岩
P-E·张
R·基托蒙博罗哈
李思贤
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Apple Inc
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Apple Inc
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Publication of CN113451371A publication Critical patent/CN113451371A/zh
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
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Abstract

本公开涉及具有减小的路由线(routing line)电阻的大面板显示器。本文公开了一种电子设备，该电子设备可包括具有利用发光二极管、薄膜硅晶体管、薄膜半导体氧化物晶体管和电容器形成的像素的显示器。硅晶体管、半导体晶体管和电容器可具有耦接到栅极线或路由线的控制端子，该栅极线或路由线跨显示器的面延伸并且形成在低电阻源极‑漏极金属路由层中。利用低电阻源极‑漏极金属路由层形成路由/栅极线显著减小了栅极线的电阻，这使得对于以较高刷新率操作的大显示面板能够实现更好的定时裕度。

Description

具有减小的路由线电阻的大面板显示器
本专利申请要求2021年1月7日提交的美国专利申请第17/143,939号以及2020年3月25日提交的美国临时专利申请第62/994,747号的优先权，这些专利申请据此全文以引用方式并入本文。
背景技术
本公开整体涉及电子设备，并且更具体地涉及具有显示器的电子设备。
电子设备通常包括显示器。例如，电子设备可具有基于有机发光二极管像素的有机发光二极管(OLED)显示器。在这种类型的显示器中，每个像素都包括发光二极管和薄膜晶体管，薄膜晶体管用于控制向发光二极管施加信号以产生光。发光二极管可包括定位在阳极和阴极之间的OLED层。
传统显示器通常包括用于经由相应扫描线将扫描控制信号输出到对应像素行的栅极驱动器。扫描线常常连接到低温多晶硅(LTPS)晶体管并且是利用高电阻金属跨显示器的面路由。这对于具有较小显示器的设备而言可能不是问题，但是对于具有以高刷新率诸如120Hz操作的大面板显示器的设备而言，高电阻扫描线上的负载量可被提高使得扫描控制信号的上升时间和下降时间被增加到数据不再能够被正确采样到显示器像素上的点。
发明内容
提供了一种具有显示器的电子设备。该显示器可包括形成在有效区域中的像素阵列。每个像素可包括耦接到相关联的薄膜晶体管(TFT)结构的有机发光二极管，相关联的薄膜晶体管(TFT)结构诸如一个或多个硅晶体管、一个或多个半导体氧化物晶体管和/或一个或多个电容器。
像素可形成在衬底上。具体地讲，硅晶体管可包括形成在衬底上的有源硅区和形成在第一栅极金属层中的栅极导体。电容器可包括形成在第一栅极金属层中的第一电容器端子和形成在第二栅极金属层中的第二电容器端子。半导体氧化物晶体管可包括形成在第二栅极金属层上方的半导体氧化物区和形成在第三栅极金属层中的栅极导体。形成在第一栅极金属层、第二栅极金属层和第三栅极金属层中的导体可利用高电阻金属诸如钼和/或钛来形成。
硅晶体管的栅极导体、第二电容器端子和半导体氧化物晶体管的栅极导体可耦接到在第三栅极金属层上方的第一源极-漏极(SD1)路由层中形成的相应路由线。SD1路由层中的导体可利用低电阻金属诸如铝、铜、银或金来形成。耦接到硅晶体管和半导体氧化物晶体管的栅极导体的SD1路由线可用作栅极线、扫描线、发射线、初始化线、重置线或其他行控制线。在SD1路由层中路由行控制线可有助于减小这些线上的电阻，这将改善以高刷新率操作的大显示面板的定时裕度。
第一平面化层可形成在SD1路由层上方。第二源极-漏极(SD2)路由层可形成在第一平面化层上。第二平面化层可形成在第一平面化层上。SD2层中的路由线可被配置为路由电源信号，诸如正电源电压和接地电源电压。电源线可在任何方向上路由穿过有效区域，以帮助确保与接地电源线相关联的最高电压降的点定位在显示器的中心处和/或减小显示器上的亮度差异。
附图说明
图1是根据一个实施方案的具有显示器的例示性电子设备的示意图。
图2A是根据一个实施方案的具有发光元件阵列的例示性显示器的图示。
图2B是根据一个实施方案的例示性显示器像素的电路图。
图3是根据一个实施方案的显示器中的例示性薄膜晶体管电路的横截面侧视图。
图4是根据一个实施方案的例示性低电阻路由结构的横截面侧视图。
图5是根据一个实施方案的显示器像素的顶部平面图，示出了栅极导体如何耦接到形成在第一源极-漏极(SD1)层中的路由线。
图6是根据一个实施方案的显示器像素的顶部平面图，示出了栅极导体如何耦接到形成在第二源极-漏极(SD2)层中的路由线。
图7是根据一个实施方案的显示器的顶部平面图，示出了多个接地电源线可如何跨显示器的面路由。
图8是根据一个实施方案的显示器的顶部平面图，示出了多个正电源线可如何跨显示器的面路由。
具体实施方式
图1中示出了可具有显示器的类型的例示性电子设备。电子设备10可为计算设备诸如膝上型计算机、包含嵌入式计算机的计算机监视器、平板电脑、蜂窝电话、媒体播放器或其他手持式或便携式电子设备、较小的设备(诸如腕表设备、挂式设备、耳机或听筒设备、被嵌入在眼镜中的设备或者佩戴在用户的头部上的其他装备，或其他可穿戴式或微型设备)、显示器、包含嵌入式计算机的计算机显示器、不包含嵌入式计算机的计算机显示器、游戏设备、导航设备、嵌入式***(诸如其中具有显示器的电子装备被安装在信息亭或汽车中的***)、或其他电子装备。电子设备10可具有一副眼镜(例如，支撑框架)的形状，可形成具有头盔形状的外壳，或者可具有用于帮助将一个或多个显示器的部件安装和固定在用户的头部上或眼睛附近的其他构型。
如图1所示，电子设备10可包括控制电路16用于支持设备10的操作。控制电路16可包括存储装置，诸如硬盘驱动器存储装置、非易失性存储器(例如，被配置为形成固态驱动器的闪存存储器或其他电可编程只读存储器)、易失性存储器(例如，静态随机存取存储器或动态随机存取存储器)等等。控制电路16中的处理电路可用于控制设备10的操作。该处理电路可基于一个或多个微处理器、微控制器、数字信号处理器、基带处理器、电源管理单元、音频芯片、专用集成电路等。
设备10中的输入-输出电路诸如输入-输出设备12可用于允许将数据提供至设备10，并且允许将数据从设备10提供至外部设备。输入-输出设备12可包括按钮、操纵杆、滚轮、触摸板、小键盘、键盘、麦克风、扬声器、音频发生器、振动器、相机、传感器、发光二极管和其他状态指示器、数据端口等。用户可由通过输入-输出设备12的输入资源供应命令来控制设备10的操作，并且可使用输入输出设备12的输出资源从设备10接收状态信息和其他输出。
输入-输出设备12可包括一个或多个显示器，诸如显示器14。显示器14可为包括用于采集来自用户的触摸输入的触摸传感器的触摸屏显示器，或者显示器14可对触摸不敏感。显示器14的触摸传感器可基于电容性触摸传感器电极的阵列、声学触摸传感器结构、电阻性触摸部件、基于力的触摸传感器结构、基于光的触摸传感器，或其他合适的触摸传感器布置。用于显示器14的触摸传感器可由在具有显示器14的显示像素的公共显示器衬底上形成的电极形成，或可由与显示器14的像素重叠的独立触摸传感器面板形成。如果需要，显示器14可对触摸不敏感(即，触摸传感器可被省略)。电子设备10中的显示器14可以是抬头显示器，其可在不需要用户远离典型视点的情况下观看，或者可以是结合到佩戴在用户头部的设备中的头戴式显示器。如果需要，显示器14也可以是用于显示全息图的全息显示器。
可使用控制电路16来在设备10上运行软件，诸如操作***代码和应用程序。在设备10的操作期间，运行在控制电路16上的软件可在显示器14上显示图像。
显示器14可以是有机发光二极管显示器或者可以是基于其他类型的显示技术的显示器。在本文中有时将显示器14为有机发光二极管显示器的设备配置描述作为示例。然而，这仅为例示性的。如果需要，可使用任何合适类型的显示器。一般来讲，显示器14可以具有矩形形状(即，显示器14可以具有矩形占有面积和围绕矩形占有面积延伸的矩形周边边缘)或者可以具有其他合适的形状。显示器14可以是平面的或可具有曲线轮廓。
图2A中示出了显示器14的一部分的顶视图。如图2A所示，显示器14可具有在衬底上形成的像素22的阵列。像素22可通过信号路径诸如数据线D接收数据信号，并且可通过控制信号路径诸如水平控制线G(有时称为栅极线、扫描线、发射控制线等)接收一个或多个控制信号。显示器14中可以有任意适当数量的行和列的像素22(例如，数十个或更多、数百个或更多、或者数千个或更多)。每个像素22可具有发光二极管26，该发光二极管在由薄膜晶体管电路诸如薄膜晶体管28和薄膜电容器形成的像素控制电路的控制下发射光24。薄膜晶体管28可以是多晶硅薄膜晶体管、半导体氧化物薄膜晶体管(诸如氧化铟镓锌(IGZO)晶体管)和/或由其他半导体形成的薄膜晶体管。像素22可包含不同颜色(例如，红色、绿色和蓝色)的发光二极管以向显示器14提供显示彩色图像的能力，或者可为单色像素。
显示驱动器电路可用于控制像素22的操作。显示驱动器电路可由集成电路、薄膜晶体管电路和/或其他合适的电路形成。图2A的显示驱动器电路30可包含用于通过路径32与***控制电路诸如图1的控制电路16进行通信的通信电路。路径32可由柔性印刷电路上的迹线或其他缆线形成。在操作期间，控制电路(例如，图1的控制电路16)可为显示驱动器电路30提供有关将在显示器14上显示的图像的信息。
为了在显示器像素22上显示图像，显示驱动器电路30可将图像数据提供到对应数据线上，同时通过路径38向支持显示驱动器电路诸如栅极驱动器电路34发出时钟信号和其他控制信号。数据信号D、正电源信号VDD和接地电源信号VSS可经由对应的列线40供应到每个像素列。如果需要，显示驱动器电路30还可向显示器14的相对边缘上的栅极驱动器电路34提供时钟信号和其他控制信号。
栅极驱动器电路34(有时称为行控制电路)可被实现为集成电路的一部分和/或可使用薄膜晶体管电路来实现。显示器14中的水平控制线42可载送栅极(G)线信号，诸如扫描线信号、发射启用控制信号、重置信号、初始化信号、参考信号、和用于控制每行的显示器像素22的其他水平控制信号。每行像素22可存在任何合适数量的水平控制信号(例如，一个或多个行控制信号、两个或更多个行控制信号、三个或更多个行控制信号、四个或更多个行控制信号等)。
显示器14上形成显示器像素22的区域在本文中有时称为有效区域(AA)。电子设备10具有带有周边边缘的外部外壳。围绕有效区域并且在设备10的周边边缘内的区域是边界区域。图像只能在有效区域中显示给设备的用户。通常希望使设备10的边界区域最小化。例如，设备10可设置有在设备的整个正面上延伸的全面屏显示器14。如果需要，显示器14也可包裹在正面的边缘上，使得设备10的侧向边缘的至少一部分或背部表面的至少一部分用于显示目的。
图2B为显示器14中例示性有机发光二极管显示器像素22的电路图。如图2B所示，显示器像素22可包括存储电容器Cst和相关联的像素晶体管，诸如半导体氧化物晶体管Toxide、驱动晶体管Tdrive、数据加载晶体管Tdata、第一发射晶体管Tem1、第二发射晶体管Tem2和阳极重置晶体管Tar。虽然晶体管Toxide是利用半导体氧化物(例如，具有由半导体氧化物诸如氧化铟镓锌或IGZO形成的n型沟道的晶体管)形成，其他晶体管可以是由半导体诸如硅(例如，利用低温工艺沉积的多晶硅沟道，有时称为“LTPS”或低温多晶硅)形成的薄膜晶体管。半导体氧化物晶体管表现出比硅晶体管更低的泄漏，因此将晶体管Toxide实现为半导体氧化物晶体管将有助于(例如，通过防止电流泄漏离开驱动晶体管Tdrive的栅极端子)减少闪烁。
在另一种适当的布置中，晶体管Toxide和Tdrive可被实现为半导体氧化物晶体管，而其余的晶体管Tdata、Tem1、Tem2、和Tar为硅(LTPS)晶体管。晶体管Tdrive充当驱动晶体管，并且具有对像素22的发射电流至关重要的阈值电压。由于晶体管Tdrive的阈值电压可经历滞后，因此将驱动晶体管形成为顶栅半导体氧化物晶体管可帮助减少滞后(例如，顶栅IGZO晶体管经历比硅晶体管更小的Vth滞后)。如果需要，其余晶体管Tdata、Tem1、Tem2和Tar中的任意者可被实现为半导体氧化物晶体管。在又一种合适的布置中，像素22内的所有晶体管可被实现为硅晶体管(即，像素22不需要包括任何半导体氧化物晶体管)。一般来讲，任何硅晶体管可为n型(即，n沟道)或p型(即，p沟道)LTPS薄膜晶体管。如果需要，像素22可包括多于或少于六个晶体管和/或可包括多于或少于一个内部电容器。
显示器像素22可包括有机发光二极管(OLED)204。可将正电源电压VDDEL提供至正电源端子200，并且可将接地电源电压VSSEL提供至接地电源端子202。正电源电压VDDEL可以是3V、4V、5V、6V、7V、2V至8V或任何合适的正电源电压电平。接地电源电压VSSEL可以是0V、-1V、-2V、-3V、-4V、-5V、-6V、-7V或任何合适的接地或负电源电压电平。驱动晶体管Tdrive的状态控制通过二极管204从端子200流至端子202的电流的量，并且因此控制来自显示器像素22的发射光的量。有机发光二极管204可具有相关联的寄生电容COLED(未示出)。
端子209可用于提供阳极重置电压Var，以在未使用二极管204时帮助关断二极管204。因此，端子209有时被称为阳极重置或初始化线。来自显示驱动器电路诸如图2A的行驱动器电路34的控制信号被提供至控制端子，诸如行控制端子212、214-1、214-2和214-3。行控制端子212可用作发射控制端子(有时称为发射线或发射控制线)，而行控制端子214-1、214-2和214-3可用作第一扫描控制端子、第二扫描控制端子和第三扫描控制端子(有时称为扫描线或扫描控制线)。发射控制信号EM可被提供给端子212。扫描控制信号SC1、SC2和SC3可分别应用于扫描端子214-1、214-2和214-3。数据输入端子诸如数据信号端子210耦接至图2A的相应数据线D，以用于接收用于显示器像素22的图像数据。数据端子210也可以被称为数据线。
在图2B的例子中，晶体管Tem1、Tdrive、Tem2、和OLED 304可串联耦接在电源端子200与电源端子202之间。具体地，第一发射控制晶体管Tem1可具有耦接至正电源端子200的源极端子、经由发射线212接收发射控制信号EM2的栅极端子，以及漏极端子(被标记为节点1)。术语晶体管的“源极”端子和“漏极”端子有时可互换使用，并且因此可被称为“源极-漏极”端子。驱动晶体管Tdrive可具有耦接到节点1的源极端子、栅极端子(标记为节点2)和漏极端子(标记为节点3)。第二发射控制晶体管Tem2可具有耦接到节点3的源极端子、也经由发射线212接收发射控制信号EM的栅极端子、以及经由发光二极管204耦接到接地电源端子202的漏极端子(标记为节点4)。以这种方式配置，发射控制信号EM可在发射阶段期间被断言以接通晶体管Tem1和Tem2，以允许电流流过发光二极管204。
存储电容器Cst可具有耦接至正电源线200的第一端子和耦接至节点2的第二端子。加载到像素22中的图像数据可通过使用电容器Cst在整个发射阶段保持电荷来至少部分地存储在像素22上。晶体管Toxide可具有耦接到节点2的源极端子、被配置为经由扫描线214-1接收扫描控制信号SC1的栅极端子和耦接到节点3的漏极端子。信号SC1可被断言以接通晶体管Toxide，从而使晶体管Tdrive的漏极端子和栅极端子短接。栅极端子和漏极端子短接的晶体管构型有时称为被“二极管连接”。
数据加载晶体管Tdata可具有耦接到数据线210的源极端子、被配置为经由扫描线214-2接收扫描控制信号SC2的栅极端子和耦接到节点1的漏极端子。以这种方式配置，信号SC2可被断言以接通晶体管Tdata，这将允许来自数据线210的数据电压被加载到节点1上。晶体管Tar可具有耦接到节点4的源极端子、被配置为经由扫描线214-3接收扫描控制信号SC3的栅极端子和耦接到初始化线209的漏极端子。以这种方式配置，扫描控制信号SC3可被断言以接通晶体管Tar，这将节点4驱动到阳极重置电压电平Var。如果需要，线209上的阳极重置电压Var可在像素22的操作期间动态地偏置到不同电平。
图3为根据一个实施方案的可包括在显示器像素22内的例示性薄膜晶体管电路的横截面侧视图。如图3所示，显示器层叠结构可包括衬底层诸如衬底302，该衬底层可包括一个或多个半导体层、一个或多个绝缘层、半导体层和绝缘层的组合、一个或多个缓冲层等。在一些实施方案中，衬底302可由玻璃、金属、塑料、陶瓷、蓝宝石或其他合适的衬底材料形成。例如，衬底302可以是由聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)或聚萘二甲酸乙二醇酯(PEN)形成的有机衬底。衬底302的表面可任选地覆盖有一个或多个缓冲层(例如，无机缓冲层，诸如氧化硅层、氮化硅层等)。
多晶硅层(例如，LTPS层)可以被形成在衬底302上，被图案化和蚀刻，以形成LTPS区352。LTPS区406的两个相对端可任选地被掺杂(例如，n掺杂或p掺杂)，以形成硅晶体管350的源极-漏极区。图3的横截面中的薄膜硅晶体管350可一般性地表示像素22内的任何LTPS晶体管。
栅极绝缘体层304可形成在衬底302上以及在硅区352上方。第一金属层(例如，第一栅极金属层“GE1”)可以形成在栅极绝缘体层304上方。第一金属层可以被图案化和蚀刻，以形成晶体管350的栅极导体。在图3的示例中，第一金属层也可被图案化和蚀刻以形成存储电容器Cst的第一端子(例如，GE1也可用于形成存储电容器的底板)。像素22内的任何附加电容器结构(在图3中未示出，以便不使本实施方案模糊)也可具有形成在GE1金属层中的其电容器端子中的一者。
第一层间介电(ILD1)层306可在第一栅极金属层GE1和硅晶体管350上方形成。介电层306可(例如)由氮化硅、氧化硅和其他合适的绝缘材料形成。第二金属层(例如，第二栅极金属层“GE2”)可形成在ILD1层306上。第二金属层可被图案化并蚀刻以形成存储电容器Cst的第二端子(例如，GEe可用于形成存储电容器的顶板)。如果需要，像素22内的任何附加电容器结构(在图3中未示出，以便不使本实施方案模糊)也可具有形成在GE2金属层中的其电容器端子中的一者。
第二层间介电(ILD2)层308可形成在第二栅极金属层GE2上方以及电容器Cst上方。介电层308可由氮化硅、氧化硅和其他合适的绝缘材料形成。一个或多个缓冲层诸如缓冲层310(例如，无机缓冲层诸如氧化硅层、氮化硅层等)可形成在介电层308上方。
半导体氧化物层(例如，IGZO层)可形成在缓冲层310上方，该缓冲层有时称为氧化物缓冲层。半导体氧化物层可被图案化并蚀刻以形成半导体氧化物区362。绝缘层诸如栅极绝缘体层311可形成在IGZO区362上。氧化物(第三)栅极金属层“OGE”可形成在栅极绝缘体层311上以用作半导体氧化物晶体管360的栅极导体。氧化物区362的源极-漏极区可通过氢化、离子注入或其他合适的掺杂方法进行n掺杂或p掺杂。另一层间介电(OILD)层312可形成在缓冲层310上和晶体管360上方。图3的横截面中的薄膜半导体氧化物晶体管360可一般性地表示像素22内的任何半导体氧化物晶体管。在像素22不包括任何半导体氧化物晶体管的其他合适的布置中，在制造像素22时，可以不形成层中的一者或多者，诸如氧化物缓冲层310、半导体氧化物区362、栅极衬里311、OGE层和/或氧化物ILD层312。
硅晶体管350上方和半导体氧化物晶体管360上方的第一互连层可形成在介电层312上。形成在第一互连层中的导电路由结构可向下耦接到像素22中每个下面晶体管的源极-漏极区，并且因此有时可被称为第一源极-漏极金属层“SD1”。在图3的示例中，硅区352的源极-漏极端子可通过导电通孔370(例如，穿过层304、306、308、310和312的触点370)耦接到对应的SD1导体。半导体氧化物区362的源极-漏极端子也可通过导电通孔372(例如，穿过层312的触点372)耦接到对应的SD1导体。
栅极金属导体也可耦接到SD1路由导体。例如，硅晶体管350的GE1栅极导体可通过导电通孔371耦接到对应的SD1导体。任选的半导体氧化物晶体管360的OGE栅极导体可通过导电通孔373耦接至对应的SD1导体。电容器的GE2顶板端子也可通过导电通孔375耦接到对应的SD1导体。
第一平面化(PLN1)层诸如层314可形成在SD1金属路由层上方。第二互连层还可形成在第一平面化层314上。形成在第二互连层中的导电路由结构可向下耦接到SD1导体，并且因此有时可被称为第二源极-漏极金属层“SD2”。
可在平面化层314上和SD2路由金属线上方形成第二平面化(PLN2)层诸如层316。平面化层314和316可由有机介电材料(诸如聚合物)形成。相比之下，有机平面化层下方的层诸如层304、306、308、310和312通常由无机介电材料诸如氮化硅、氧化硅等形成。
阳极318(例如，图2B的有机发光二极管204的阳极端子)可形成在第二平面化层316上方。可在阳极318上方形成附加结构。例如，像素界定层、发光二极管发射材料、阴极和其他像素结构也可包含在显示器像素22的层叠结构中。然而，为了简洁起见，省略了这些附加结构。
显示器像素硅晶体管的GE1栅极导体、显示器像素电容器的GE2电容器端子以及显示器像素半导体氧化物晶体管的OGE栅极导体通常使用高电阻材料(诸如钼、钛、高电阻材料的某种组合或其他合适的金属)形成。由于在制造硅晶体管的工艺中使用的LTPS工艺的要求，需要使用此类高电阻率材料来形成这些栅极金属导体。
图4是例示性SD1或SD2路由导体的横截面侧视图。如图4所示，SD1/SD2路由导体可包括任选地夹在两个高电阻衬里402之间的低电阻材料404。衬里402可使用钼、钛、高电阻率材料的某种组合或其他合适的金属形成。相比之下，SD1/SD2导体的本体可包括由铝、铜、银、金、锌、黄铜、低电阻率材料的某种组合、和具有高电导率的其他合适金属形成的材料404。以这种方式形成时，SD1/SD2导体可表现出比GE1/GE2/OGE导体显著更高的导电性和更小的电阻。例如，“低”电阻SD1/SD2金属路由结构可表现出约0.05Ω/□、0.01-0.05Ω/□、0.05-0.1Ω/□或小于0.01Ω/□的薄层电阻。“高”电阻GE1/GE2/OGE金属结构可以表现出约0.5Ω/□、0.1-0.5Ω/□、0.5-1.0Ω/□或大于1.0Ω/□的薄层电阻。一般来讲，GE1/GE2/OGE金属结构的电阻率可为SD1/SD2金属结构的电阻率的至少5倍、至少10倍、至少100倍。
在传统显示器中，可以使用由高电阻金属形成的扫描线跨显示器的面路由扫描控制信号。例如，对硅晶体管的栅极端子馈电的扫描线在GE1金属层中路由，并且对半导体氧化物晶体管的栅极端子馈电的扫描线在OGE金属层中路由。与电容器相关联的互连也在GE2金属层中路由。以这种方式使用高电阻率材料对扫描线或栅极线进行路由对于具有较小显示器的设备是可接受的。然而，对于具有以高刷新率(例如，120Hz、60Hz以上或120Hz以上的刷新率等)操作的大面板显示器的设备，高电阻扫描线上的负载的量可被提高使得栅极线信号的所得的上升时间和下降时间被增加到数据不再能被正确采样到显示器像素上的点。
根据一个实施方案，栅极线信号诸如扫描控制信号、发射控制信号、重置信号、初始化信号、参考信号、启用信号、电源信号(例如，正电源电压或接地电源电压)、和/或其他行控制信号可使用低电阻材料诸如SD1金属路由层(参见例如图5)跨显示器的面路由。图5是像素22的顶部平面(布局)图，示出了栅极导体如何耦接到形成在SD1金属路由层中的路由线。如图5所示，耦接到像素22中的GE1金属导体的第一行控制线、耦接到像素22中的GE2金属导体的第二行控制线、以及耦接到像素22中的OGE金属导体的第三行控制线全部使用低电阻SD1路由层跨显示器的面路由(例如，控制线沿给定像素行路由通过至少两个像素22、至少10个像素22、至少100个像素或任何合适数量的像素)。如果需要，也可使用SD1金属来路由与显示器像素22相关联的其他行控制信号。在图5的例子中，数据线(DL)、正电源(VDD)线和接地电源(VSS)线可使用形成在SD2金属路由层中的路由线在列方向上路由(例如，SD2路由线可跨像素列中的至少两个像素、至少10个像素、至少100个像素或任何合适数量的像素路由)。SD2路由线可垂直于SD1路由线。一般来讲，根据显示器的取向，术语“行”和“列”可互换使用。如果需要，SD1路由线也可与SD1路由线平行路由。
以这种方式配置和操作时，跨显示面板路由的栅极线的电阻将大幅减小(例如，减小至少5倍、至少10倍或更多倍)，这可减小栅极线信号的上升时间和下降时间，使得数据信号可被适当地加载到以高刷新率操作的大显示面板中。通过减小栅极线上的负载，也可改善显示器的亮度均匀性。
其中行控制信号使用SD1金属线路由并且列控制信号使用SD2金属线路由的图6的例子仅仅是示例性的，并非旨在限制本公开的实施方案的范围。图6示出了另一种合适的布置，其中行控制信号(例如，栅极线、扫描信号、发射信号、重置信号、初始化信号等)使用SD2金属线路由，并且列控制信号(例如，数据信号、电源信号等)使用SD1金属线路由。尽管SD1和SD2被图示为彼此垂直，但它们也可以彼此平行路由(如果需要)。
图7是根据一个实施方案的显示器14的顶部平面(布局)图，示出了多个接地电源线可如何跨显示器的面路由。如图7所示，显示器14可具有周边边缘702、沿周边的底部边缘形成的电源电路704(当在显示器的与XY平面平行的面处沿方向Z观察显示器14时)。电源电路704可被配置为将接地电源电压VSS提供到接地线706上，该接地线沿显示器14的整个周边边缘702路由。根据一个实施方案，附加接地线诸如接地线708可在垂直于显示器的底部周边边缘的方向Y上跨显示器14的面路由，沿着该底部周边边缘形成电源电路704。例如，接地线708可在每个像素列中、在每隔一个像素列中、在每2-10个像素列中或以其他合适的间隔形成。
以这种方式配置，接地线708可有助于为更远离显示器边缘的像素提供较低电阻电流路径，使得在电源端子处经历最高电流-电阻(“IR”或电压)降的像素定位在显示器14的中心，如点710所示。在没有以这种方式形成接地线708的情况下，最高IR降的点可能不期望地朝向显示器的上周边边缘偏移，这将减小显示器中心附近的像素的驱动裕度，同时增大总体功率消耗。
与VSS线的路由不同，VDD线的路由可能影响显示器的亮度。例如，如果VDD电流路径上的电阻高，则具有更多黑色像素的像素列的总亮度可能高于具有更少黑色像素的像素列的亮度。为了帮助减轻亮度的这种偏移，多个正电源(VDD)线可跨显示器的面路由(参见例如图8)。如图8所示，显示器14可具有周边边缘702、沿周边的底部边缘形成的电源电路704(当在显示器的与XY平面平行的面处沿方向Z观察显示器14时)。电源电路704可被配置为将正电源电压VDD提供到沿显示器14的周边边缘702路由的电源线806上。
根据一个实施方案，附加电源线诸如正电源线808可在平行于显示器的底部周边边缘的方向X上跨显示器14的面路由，电源电路704沿该底部周边边缘形成。例如，VDD线808可在每个像素行中、在每隔一个像素行中、每2-10个像素行中或以其他合适的间隔形成。以这种方式配置，电源线808可有助于为更远离显示器边缘的像素提供较低电阻电流路径，使得无论每列中较暗像素的数量如何，显示器亮度都将保持相同。
根据一个实施方案，提供了一种显示器，所述显示器包括：显示驱动器电路，所述显示驱动器电路被配置为生成显示驱动器信号；在有效区域中的衬底上形成的多个像素，所述多个像素中的每个像素包括形成在所述衬底上的硅晶体管，所述硅晶体管包括形成在第一栅极金属层中的栅极导体，并且所述硅晶体管的所述栅极导体具有第一电阻，和形成在所述硅晶体管的所述栅极导体上方的控制线，所述控制线被配置为向所述有效区域中所述多个像素中的至少两个像素中的所述硅晶体管的所述栅极导体提供从所述显示驱动器电路生成的所述显示驱动器信号，并且所述控制线是利用具有小于所述第一电阻的第二电阻的材料在第一源极-漏极层中形成。
根据另一实施方案，所述多个像素中的每个像素包括电容器，所述电容器具有形成在所述第一栅极金属层中的第一端子。
根据另一实施方案，所述电容器包括在所述第一栅极金属层上方的第二栅极金属层中形成的第二端子。
根据另一实施方案，所述显示器包括附加控制线，所述附加控制线被路由到所述有效区域中所述多个像素中所述至少两个像素中的所述电容器的所述第二端子，所述附加控制线是利用具有所述第二电阻的所述材料形成在所述第一源极-漏极层中。
根据另一实施方案，所述多个像素中的每个像素包括形成在所述硅晶体管上方的半导体氧化物晶体管，所述半导体氧化物晶体管包括形成在第三栅极金属层中的栅极导体，并且所述半导体氧化物晶体管的所述栅极导体具有高于所述第二电阻的第三电阻，以及形成在所述半导体氧化物晶体管的所述栅极导体上方的附加控制线，所述附加控制线被配置为向所述多个像素中所述至少两个像素中的所述半导体氧化物晶体管的所述栅极导体提供从所述显示驱动器电路生成的所述显示驱动器信号，并且所述附加控制线是利用具有所述第二电阻的所述材料形成在所述第一源极-漏极层中。
根据另一实施方案，所述控制线和所述附加控制线包括被配置为载送扫描信号的栅极线。
根据另一实施方案，所述显示器包括形成在所述硅晶体管上方的第一平面化层、形成在所述第一平面化层上的第二源极-漏极层中的附加导电线、以及形成在所述附加路由线上方的第二平面化层。
根据另一实施方案，所述附加导电线被配置为将数据信号路由到所述有效区域中所述多个像素中的至少两个像素。
根据另一实施方案，所述附加导电线被配置为将正电源信号路由到所述有效区域中所述多个像素中的至少两个像素。
根据另一实施方案，所述附加导电线被配置为将接地电源信号路由到所述有效区域中所述多个像素中的至少两个像素。
根据另一实施方案，所述附加导电线垂直于所述控制线。
根据另一实施方案，所述第一电阻比所述第二电阻大至少五倍。
根据另一实施方案，所述第一电阻比所述第二电阻大至少十倍。
根据另一实施方案，所述硅晶体管的所述栅极导体是利用钼形成。
根据另一实施方案，所述第一源极-漏极层中的材料是利用选自由铝、铜、银和金构成的组的金属来形成。
根据一个实施方案，提供了一种显示器，所述显示器包括周边、形成在所述周边内的有效区域中的多个像素、沿所述周边的边缘形成的电源电路、沿所述显示器的整个周边形成的接地电源线、和形成通过所述有效区域中的所述多个像素的附加接地电源线，所述附加接地电源线被配置为确保与所述接地电源线相关联的最高电压降的点定位在所述显示器的中心处。
根据另一实施方案，所述附加接地电源线垂直于所述周边的沿其形成所述电源电路的所述边缘。
根据另一实施方案，所述多个像素中的每个像素列耦接到所述附加接地电源线中的一者。
根据一个实施方案，提供了一种显示器，所述显示器包括周边、形成在所述周边内的有效区域中的多个像素、沿所述周边的边缘形成的电源电路、沿所述显示器的整个周边形成的正电源线、和形成通过所述有效区域中所述多个像素的附加正电源线，所述附加正电源线被配置为减轻所述显示器上的亮度差异。
根据另一实施方案，所述附加正电源线平行于所述周边的沿其形成所述电源电路的所述边缘。
前文仅为例示性的，并且在不脱离所述实施方案的范围和实质的情况下，本领域的技术人员可作出各种修改。前述实施方案可独立实施或可以任意组合实施。

Claims (20)

1.一种显示器，包括：
显示驱动器电路，所述显示驱动器电路被配置为生成显示驱动器信号；
多个像素，所述多个像素形成在有效区域中的衬底上，其中所述多个像素中的每个像素包括形成在所述衬底上的硅晶体管，其中所述硅晶体管包括形成在第一栅极金属层中的栅极导体，并且其中所述硅晶体管的所述栅极导体具有第一电阻；以及
控制线，所述控制线形成在所述硅晶体管的所述栅极导体上方，其中所述控制线被配置为将从所述显示驱动器电路生成的所述显示驱动器信号提供给所述有效区域中的所述多个像素中的至少两个像素中的所述硅晶体管的所述栅极导体，并且其中所述控制线是利用具有小于所述第一电阻的第二电阻的材料在第一源极-漏极层中形成的。
2.根据权利要求1所述的显示器，其中所述多个像素中的每个像素还包括：
电容器，所述电容器具有形成在所述第一栅极金属层中的第一端子。
3.根据权利要求2所述的显示器，其中所述电容器还包括：
第二端子，所述第二端子在所述第一栅极金属层上方的第二栅极金属层中形成。
4.根据权利要求3所述的显示器，还包括：
附加控制线，所述附加控制线被路由到所述有效区域中所述多个像素中的所述至少两个像素中的所述电容器的所述第二端子，其中所述附加控制线是利用具有所述第二电阻的所述材料在所述第一源极-漏极层中形成的。
5.根据权利要求3所述的显示器，其中所述多个像素中的每个像素还包括：
半导体氧化物晶体管，所述半导体氧化物晶体管形成在所述硅晶体管上方，其中所述半导体氧化物晶体管包括形成在第三栅极金属层中的栅极导体，并且其中所述半导体氧化物晶体管的所述栅极导体具有高于所述第二电阻的第三电阻；以及
附加控制线，所述附加控制线形成在所述半导体氧化物晶体管的所述栅极导体上方，其中所述附加控制线被配置为将从所述显示驱动器电路生成的所述显示驱动器信号提供给所述多个像素中的所述至少两个像素中的所述半导体氧化物晶体管的所述栅极导体，并且其中所述附加控制线是利用具有所述第二电阻的所述材料在所述第一源极-漏极层中形成的。
6.根据权利要求5所述的显示器，其中所述控制线和所述附加控制线包括被配置为载送扫描信号的栅极线。
7.根据权利要求1所述的显示器，还包括：
第一平面化层，所述第一平面化层形成在所述硅晶体管上方；
附加导电线，所述附加导电线在所述第一平面化层上的第二源极-漏极层中形成；以及
第二平面化层，所述第二平面化层形成在所述附加路由线上方。
8.根据权利要求7所述的显示器，其中所述附加导电线被配置为将数据信号路由到所述有效区域中的所述多个像素中的至少两个像素。
9.根据权利要求8所述的显示器，其中所述附加导电线被配置为将正电源信号路由到所述有效区域中的所述多个像素中的至少两个像素。
10.根据权利要求7所述的显示器，其中所述附加导电线被配置为将接地电源信号路由到所述有效区域中的所述多个像素中的至少两个像素。
11.根据权利要求7所述的显示器，其中所述附加导电线垂直于所述控制线。
12.根据权利要求1所述的显示器，其中所述第一电阻是所述第二电阻的至少五倍。
13.根据权利要求1所述的显示器，其中所述第一电阻是所述第二电阻的至少十倍。
14.根据权利要求1所述的显示器，其中所述硅晶体管的所述栅极导体是利用钼形成的。
15.根据权利要求1所述的显示器，其中所述第一源极-漏极层中的所述材料是利用选自由铝、铜、银和金构成的组的金属来形成的。
16.一种显示器，包括：
周边；
多个像素，所述多个像素在所述周边内的有效区域中形成；
电源电路，所述电源电路沿所述周边的边缘形成；
接地电源线，所述接地电源线沿所述显示器的整个周边形成；以及
附加接地电源线，所述附加接地电源线穿过所述有效区域中的所述多个像素形成，其中所述附加接地电源线被配置为确保与所述接地电源线相关联的最高电压降的点定位在所述显示器的中心处。
17.根据权利要求16所述的显示器，其中所述附加接地电源线垂直于所述周边的沿其形成所述电源电路的所述边缘。
18.根据权利要求16所述的显示器，其中所述多个像素中的每个像素列耦接到所述附加接地电源线中的一者。
19.一种显示器，包括：
周边；
多个像素，所述多个像素在所述周边内的有效区域中形成；
电源电路，所述电源电路沿所述周边的边缘形成；
正电源线，所述正电源线沿所述显示器的整个周边形成；以及
附加正电源线，所述附加正电源线穿过所述有效区域中的所述多个像素形成，其中所述附加正电源线被配置为减轻所述显示器上的亮度差异。
20.根据权利要求19所述的显示器，其中所述附加正电源线平行于所述周边的沿其形成所述电源电路的所述边缘。
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