CN113432724B

CN113432724B - Uncooled tuned infrared detector

Info

Publication number: CN113432724B
Application number: CN202110711252.5A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2023-03-24
Anticipated expiration: 2041-06-25
Also published as: CN113432724A

Abstract

The utility model relates to an uncooled tuned infrared detector, CMOS measurement circuitry and CMOS infrared sensing structure in the infrared detector all use CMOS technology to prepare, directly prepare CMOS infrared sensing structure on CMOS measurement circuitry, are provided with at least one deck patterning metal interconnection layer between reflection stratum and the unsettled microbridge structure, and patterning metal interconnection layer is used for adjusting the resonant mode of infrared detector between patterning metal interconnection layer and the reflection stratum electrical insulation. Through the technical scheme, the problems of low performance, low pixel scale, low yield, poor consistency and the like of the traditional MEMS (micro-electromechanical system) process infrared detector are solved, the infrared absorption rate of the infrared detector is effectively improved, the infrared absorption spectrum of the infrared detector is widened, and the infrared absorption spectrum of the infrared detector is increased.

Description

Uncooled tuned infrared detector

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an uncooled tuned infrared detector.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are predicted every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) The infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the disclosure provides an uncooled tuned infrared detector, which solves the problems of low performance, low pixel scale, low yield, poor consistency and the like of the infrared detector in the traditional MEMS process, effectively improves the infrared absorption rate of the infrared detector, widens the infrared absorption spectrum of the infrared detector, and increases the infrared absorption spectrum of the infrared detector.

The present disclosure provides an uncooled tuned infrared detector, including:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measuring circuit system comprises at least one layer of closed release isolation layer above the CMOS measuring circuit system, and the closed release isolation layer is used for protecting the CMOS measuring circuit system from being influenced by a process in the release etching process for manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes, the metal interconnection layers at least comprise a reflecting layer and an electrode layer, and the dielectric layers at least comprise a sacrificial layer and a heat-sensitive dielectric layer; the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system;

the CMOS infrared sensing structure comprises a resonant cavity formed by the reflecting layer and the heat sensitive medium layer, a suspended micro-bridge structure for controlling heat transfer and a columnar structure with electric connection and support functions, wherein the suspended micro-bridge structure comprises an absorption plate and a plurality of beam structures, and the columnar structure is connected with the beam structures and the CMOS measuring circuit system by adopting the metal interconnection process and the through hole process;

at least one patterned metal interconnection layer is arranged between the reflection layer and the suspended micro-bridge structure, the patterned metal interconnection layer is electrically insulated from the reflection layer, and the patterned metal interconnection layer is used for adjusting the resonance mode of the infrared detector;

the CMOS measuring circuit system is used for measuring and processing an array resistance value formed by one or more CMOS infrared sensing structures and converting an infrared signal into an image electric signal; the CMOS measuring circuit system comprises a bias voltage generating circuit, a column-level analog front-end circuit and a row-level circuit, wherein the input end of the bias voltage generating circuit is connected with the output end of the row-level circuit, the input end of the column-level analog front-end circuit is connected with the output end of the bias voltage generating circuit, the row-level circuit comprises row-level mirror image pixels and row selection switches, and the column-level analog front-end circuit comprises blind pixels; the row-level circuit is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the time sequence generating circuit, and outputs a current signal to the column-level analog front-end circuit under the action of the bias voltage generating circuit so as to perform current-voltage conversion and output;

the column-level analog front-end circuit obtains two paths of currents according to the first bias voltage and the second bias voltage, performs transimpedance amplification on the difference between the two paths of generated currents and outputs the amplified current as an output voltage.

Optionally, the CMOS infrared sensing structure is fabricated on an upper layer or a same layer of a metal interconnection layer of the CMOS measurement circuitry.

Optionally, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process.

Optionally, the patterned metal interconnection layer includes a plurality of metal repeating units arranged in an array, and each metal repeating unit includes at least one of two diagonally arranged L-shaped patterned structures, a circular structure, a fan-shaped structure, an elliptical structure, a circular ring structure, an open ring structure, or a polygonal structure.

Optionally, the patterned metal interconnection layer includes a plurality of patterned hollow structures arranged in an array, and the patterned hollow structures include at least one of a circular hollow structure, an open ring-shaped hollow structure, or a polygonal hollow structure.

Optionally, a plurality of patterned metal interconnection layers are disposed between the reflective layer and the suspended microbridge structure, and different patterned metal interconnection layers have the same or different patterns.

Optionally, the hermetic release barrier is located at an interface between the CMOS measurement circuitry and the CMOS infrared sensing structure and/or in the CMOS infrared sensing structure.

Optionally, the hermetic release isolation layer is disposed between the reflective layer and the suspended microbridge structure, and at least one patterned metal interconnection layer is located on a side of the hermetic release isolation layer away from the CMOS measurement circuitry and/or at least one patterned metal interconnection layer is located on a side of the hermetic release isolation layer close to the CMOS measurement circuitry.

Optionally, the infrared detector further comprises a reinforcing structure, the reinforcing structure is arranged corresponding to the position of the columnar structure, and the reinforcing structure is used for enhancing the connection stability between the columnar structure and the suspended micro-bridge structure;

at least one hole-shaped structure is formed on the absorption plate, and the hole-shaped structure at least penetrates through the medium layer in the absorption plate; and/or at least one hole-like structure is formed on the beam structure.

Optionally, the infrared detector is based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process;

the metal connecting wire material forming the metal interconnection layer comprises at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium or cobalt.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

the CMOS measurement circuit system and the CMOS infrared sensing structure are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production. In addition, the tuning mode of the infrared detector is adjusted by utilizing the at least one patterned metal interconnection layer which is positioned between the reflecting layer and the suspended micro-bridge structure and is electrically insulated from the reflecting layer, so that the infrared absorption rate of the infrared detector is effectively improved, the infrared absorption spectrum of the infrared detector is widened, and the infrared absorption spectrum of the infrared detector is increased.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective structure diagram of an infrared detector pixel provided in an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of an infrared detector pixel provided in an embodiment of the present disclosure;

fig. 3 is a schematic top view of a patterned metal interconnect layer according to an embodiment of the disclosure;

fig. 4 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 5 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 6 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 7 is a schematic top view of another patterned metal interconnect layer provided in accordance with an embodiment of the present disclosure;

fig. 8 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 9 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 10 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 11 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

fig. 12 is a schematic top view of another patterned metal interconnect layer provided in the embodiments of the present disclosure;

FIG. 13 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiments of the present disclosure;

FIG. 14 is a schematic cross-sectional structure diagram of another infrared detector pixel provided by an embodiment of the disclosure;

FIG. 15 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiments of the present disclosure;

FIG. 16 is a schematic cross-sectional structure diagram of another infrared detector pixel provided by an embodiment of the present disclosure;

FIG. 17 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiments of the present disclosure;

FIG. 18 is a schematic cross-sectional structure diagram of another infrared detector pixel provided by an embodiment of the present disclosure;

FIG. 19 is a schematic cross-sectional structure diagram of another infrared detector pixel provided by an embodiment of the disclosure;

FIG. 20 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in this disclosure;

fig. 21 is a schematic structural diagram of a CMOS measurement circuitry provided in an embodiment of the present disclosure;

FIG. 22 is a schematic cross-sectional structure diagram of another infrared detector pixel provided by an embodiment of the present disclosure;

FIG. 23 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiments of the present disclosure;

FIG. 24 is a schematic cross-sectional view of another infrared detector pixel provided in an embodiment of the present disclosure;

FIG. 25 is a schematic cross-sectional view of another infrared detector pixel provided in an embodiment of the present disclosure;

FIG. 26 is a schematic cross-sectional view of another infrared detector pixel provided by an embodiment of the disclosure;

fig. 27 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared detector pixel provided in an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional structure diagram of an infrared detector pixel provided in an embodiment of the present disclosure. With reference to fig. 1 and 2, the CMOS process-based infrared detector includes a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are fabricated using a CMOS process, and the CMOS infrared sensing structure 2 is directly fabricated on the CMOS measurement circuit system 1.

Specifically, the CMOS infrared sensing structure 2 is used for converting an external infrared signal into an electric signal and transmitting the electric signal to the CMOS measuring circuit system 1, and the CMOS measuring circuit system 1 reflects temperature information of a corresponding infrared signal according to the received electric signal, so that the temperature detection function of the infrared detector is realized. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

Referring to fig. 1 and 2, the cmos infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 4 and a heat sensitive medium layer 12, a suspended micro-bridge structure 40 for controlling heat transfer, and a pillar structure 6 having electrical connection and support functions, the suspended micro-bridge structure 40 includes an absorption plate 10 and at least two beam structures 11, and fig. 1 exemplarily sets the suspended micro-bridge structure 40 to include the two beam structures 11. Specifically, the CMOS infrared sensing structure 2 includes a reflective layer 4, a suspended micro-bridge structure 40 and a columnar structure 6 which are located on the CMOS measurement circuit system 1, the columnar structure 6 is located between the reflective layer 4 and the suspended micro-bridge structure 40, the reflective layer 4 includes a reflective plate 41 and a supporting base 42, and the suspended micro-bridge structure 40 is electrically connected with the CMOS measurement circuit system 1 through the columnar structure 6 and the supporting base 42.

Specifically, the columnar structure 6 is located between the reflective layer 4 and the suspended micro-bridge structure 40, and is used for supporting the suspended micro-bridge structure 40 after a sacrificial layer on the CMOS measurement circuit system 1 is released, the sacrificial layer is located between the reflective layer 4 and the suspended micro-bridge structure 40, the suspended micro-bridge structure 40 transmits an electrical signal converted from an infrared signal to the CMOS measurement circuit system 1 through the corresponding columnar structure 6 and the corresponding supporting base 42, the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, and non-contact infrared temperature detection of the infrared detector is achieved. In addition, the absorption plate 10 at least comprises a heat sensitive medium layer 12 and an electrode layer 14, the heat sensitive medium layer 12 is used for converting infrared signals absorbed by the heat sensitive medium layer 12 into electric signals, the electrode layer 14 is used for adjusting the resistance of the heat sensitive medium layer 12 and transmitting the electric signals converted by the heat sensitive medium layer 12 to the CMOS measurement circuit system 1 through a corresponding beam structure 11, the beam structure 11 at least comprises the electrode layer 14, and the beam structure 11 is a structure for performing electric transmission and heat conduction.

The CMOS infrared sensing structure 2 outputs positive electric signals and grounding electric signals through different electrode structures, the positive electric signals and the grounding electric signals are transmitted to a supporting base 42 electrically connected with the columnar structures 6 through different columnar structures 6, fig. 1 schematically shows the direction parallel to the CMOS measuring circuit system 1 exemplarily, the CMOS infrared sensing structure 2 comprises four columnar structures 6, the four columnar structures 6 can be used for respectively transmitting the positive electric signals and the grounding electric signals in a group, the infrared detector comprises a plurality of infrared detector pixels arranged in an array mode, the four columnar structures 6 can also select two of the columnar structures 6 to respectively transmit the positive electric signals and the grounding electric signals, and the other two columnar structures 6 are used for transmitting electric signals for the adjacent infrared detector pixels. The CMOS infrared sensing structure 2 may also be configured to include two pillar structures 6, where the two pillar structures 6 are diagonally arranged, and one of the pillar structures 6 may be configured to transmit a positive electrical signal, and the other pillar structure 6 may be configured to transmit a ground electrical signal. In addition, the reflection layer 4 includes a reflection plate 41 and a supporting base 42, a part of the reflection layer 4 is used as a dielectric medium electrically connected to the column structure 6 and the CMOS measurement circuit system 1, that is, the supporting base 42, the reflection plate 41 is used for reflecting infrared rays to the suspended microbridge structure 40, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflection layer 4 and the suspended microbridge structure 40, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

Referring to fig. 1 and 2, at least one patterned metal interconnection layer 7 is disposed between the reflective layer 4 and the suspended micro-bridge structure 40, fig. 2 exemplarily sets one patterned metal interconnection layer 7 between the reflective layer 4 and the suspended micro-bridge structure 40, the patterned metal interconnection layer 7 is electrically insulated from the reflective layer 4, for example, at least one insulating dielectric layer 71 may be disposed between the patterned metal interconnection layer 7 and the reflective layer 4, fig. 2 exemplarily sets one insulating dielectric layer 71 between the patterned metal interconnection layer 7 and the reflective layer 4, and the patterned metal interconnection layer 7 is used for adjusting a resonance mode of the infrared detector. Specifically, a Bragg reflector (Bragg reflector) is an optical device for enhancing reflection of light with different wavelengths by utilizing constructive interference of reflected light with different interfaces, and is composed of a plurality of 1/4 wavelength reflectors to realize efficient reflection of incident light with a plurality of wavelengths, in the embodiment of the disclosure, at least one patterned metal interconnection layer 7 is arranged between a reflection layer 4 and a suspended micro-bridge structure 40, at least one patterned metal interconnection layer 7, the reflection layer 4 and an absorption plate 10 form a structure similar to the Bragg reflector, and the arrangement of at least one patterned metal interconnection layer 7 is equivalent to changing the thickness of an integral resonant cavity medium formed by the reflection layer 4 and a heat-sensitive medium layer in the absorption plate 10, so that infrared detector pixels can form a plurality of resonant cavities with different medium thicknesses, the infrared detector pixels can select light with different wavelengths to perform enhanced reflection adjustment, and further at least one patterned metal interconnection layer 7 is utilized to adjust a resonant mode of an infrared detector, thereby increasing the infrared absorption rate of the infrared detector, the absorption spectrum section of the infrared detector, and increasing the absorption spectrum section of the infrared detector.

Illustratively, the patterned metal interconnection layer 7 may include a plurality of metal repeating units arranged in an array, and each metal repeating unit may include at least one of two diagonally arranged L-shaped patterned structures, a circular structure, a fan-shaped structure, an elliptical structure, a circular ring structure, an open ring structure, or a polygonal structure. Fig. 3 is a schematic top view of a patterned metal interconnection layer according to an embodiment of the disclosure. As shown in fig. 3, the patterned metal interconnection layer 7 may be configured to include a plurality of metal repeating units 72 arranged in an array, each metal repeating unit 72 includes two diagonally arranged L-shaped patterned structures, as shown in fig. 4, each metal repeating unit 72 may be configured to include a circular structure, i.e., the patterned metal interconnection layer 72 includes a plurality of circular structures, as shown in fig. 5, each metal repeating unit 72 may include a fan-shaped structure, i.e., the patterned metal interconnection layer 72 includes a plurality of fan-shaped structures, as shown in fig. 6, each metal repeating unit 72 may include an elliptical structure, i.e., the patterned metal interconnection layer 72 includes a plurality of elliptical structures, as shown in fig. 7, each metal repeating unit 72 may include a circular ring structure, i.e., the patterned metal interconnection layer 72 includes a plurality of circular ring structures, as shown in fig. 8, i.e., the patterned metal interconnection layer 72 includes a plurality of open ring structures, as shown in fig. 8, as an example, each metal repeating unit 72 includes a polygonal structures, as shown in fig. 9, and as an example, the patterned metal repeating unit 72 includes a polygonal structure, and as an example, the polygonal structure is not limited to the disclosure. Thus, the patterned metal interconnection layer 7 can adjust the resonance mode of the infrared detector by using the metal repeating units 72 arranged repeatedly, so as to improve the infrared absorption rate of the infrared detector, widen the infrared absorption spectrum of the infrared detector, and increase the infrared absorption spectrum of the infrared detector.

Illustratively, the patterned metal interconnection layer 7 may also include a plurality of patterned hollow structures arranged in an array, and the patterned hollow structures may include at least one of circular hollow structures, open ring-shaped hollow structures, or polygonal hollow structures. Fig. 10 is a schematic top view of another patterned metal interconnect layer according to an embodiment of the disclosure. As shown in fig. 10, the patterned metal interconnection layer 7 may be configured to include a plurality of patterned hollow structures 73 arranged in an array, each patterned hollow structure 73 includes a circular hollow structure, that is, the patterned metal interconnection layer 7 includes a plurality of circular hollow structures, or as shown in fig. 11, the patterned metal interconnection layer 7 may include a plurality of patterned hollow structures 73 arranged in an array, each patterned hollow structure 73 includes an open-ring hollow structure, that is, each patterned metal interconnection layer 7 includes a plurality of open-ring hollow structures, fig. 11 exemplarily sets the patterned metal interconnection layer 7 to include a plurality of open-ring hollow structures, or as shown in fig. 12, each patterned metal interconnection layer 7 may include a plurality of patterned hollow structures 73 arranged in an array, each patterned hollow structure 73 includes a polygonal hollow structure, that is, each patterned metal interconnection layer 7 includes a plurality of polygonal hollow structures, and fig. 12 exemplarily sets the polygonal hollow structures to be hexagonal hollow structures, and the number of sides of the polygonal hollow structures is not specifically limited in the embodiment of the present disclosure. Therefore, the resonant mode of the infrared detector can be adjusted by the patterned metal interconnection layer 7 by using the repeatedly arranged patterned hollow structures 73, so that the infrared absorption rate of the infrared detector is improved, the infrared absorption spectrum band of the infrared detector is widened, and the infrared absorption spectrum band of the infrared detector is increased.

Illustratively, when a plurality of patterned metal interconnection layers 7 are disposed between the reflective layer 4 and the suspended microbridge structure 40, patterns included in different patterned metal interconnection layers 7 may be the same, for example, a metal repeating unit 72 formed by two diagonally disposed L-shaped patterned structures may be disposed in a pattern included in each patterned metal interconnection layer 7, and patterns included in different patterned metal interconnection layers 7 may also be different, for example, a metal repeating unit 72 formed by two diagonally disposed L-shaped patterned structures may be disposed in a pattern included in one patterned metal interconnection layer 7, and a metal repeating unit 72 formed by a circular structure may be disposed in a pattern included in the other patterned metal interconnection layer 7. In addition, the same patterned metal interconnection layer 7 may have different patterns, and for example, the same patterned metal interconnection layer 7 may have a pattern including metal repeating units 72 having two diagonally arranged L-shaped patterned structures and metal repeating units 72 having a circular structure.

Alternatively, the columnar structure 6 may include at least one layer of solid columnar structure and/or at least one layer of hollow columnar structure, that is, the columnar structure 6 may include at least one layer of solid columnar structure, at least one layer of hollow columnar structure, or at least one layer of solid columnar structure and at least one layer of hollow columnar structure. Fig. 2 exemplarily sets up that columnar structure 6 includes a layer of hollow columnar structure, namely forms hollow structure at the position of columnar structure 6, and hollow columnar structure is favorable to reducing the thermal conductance of columnar structure 6, and then reduces the influence of the thermal conductance that columnar structure 6 produced to the signal of telecommunication that unsettled microbridge structure 40 generated, is favorable to promoting infrared detector pixel and the infrared detection performance of the infrared detector including this infrared detector pixel.

Fig. 13 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present disclosure. Fig. 13 exemplarily shows that the columnar structure 6 includes a solid columnar structure, that is, a solid metal structure is formed at the position of the columnar structure 6, and the mechanical stability of the solid columnar structure is better, so that the supporting connection stability between the columnar structure 6 and the suspended microbridge structure 40 is improved, and further, the structural stability of the infrared sensor pixel and the infrared detector including the infrared detector pixel is improved. In addition, the resistance of the metal solid columnar structure is small, signal loss in the process of electric signal transmission between the suspended micro-bridge structure 40 and the CMOS measuring circuit system 1 is reduced, the infrared detection performance of the infrared detector is improved, the size of the metal solid columnar structure is easier to control accurately, namely the solid columnar structure can realize a columnar structure with a smaller size, the requirement on the size of a smaller chip is met, and the infrared detector is miniaturized.

Fig. 14 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the disclosure. Fig. 14 exemplarily shows that the pillar structures include a multi-layer solid pillar structure, for example, two layers of solid pillar structures, that is, a solid pillar structure 61 and a solid pillar structure 62, so as to have the advantages of the solid pillar structures described in the above embodiments. It is also possible to provide the columnar structure including a multi-layer hollow columnar structure similarly to fig. 14 to have the advantages of the hollow columnar structure described in the above embodiment. In addition, the columnar structure comprises a multi-layer hollow columnar structure or a multi-layer solid columnar structure, so that the types of the stand columns in the same columnar structure can be reduced, and the preparation process of the columnar structure is facilitated to be simplified.

Fig. 15 is a schematic cross-sectional structure view of another infrared detector pixel provided in the embodiment of the present disclosure, and fig. 16 is a schematic cross-sectional structure view of another infrared detector pixel provided in the embodiment of the present disclosure. Fig. 15 exemplarily shows that the pillar-shaped structure 6 includes a layer of solid pillar-shaped structure 63 and a layer of hollow pillar-shaped structure 64, and the solid pillar-shaped structure 63 is located on a side of the hollow pillar-shaped structure 64 adjacent to the CMOS measurement circuitry, and fig. 16 exemplarily shows that the pillar-shaped structure 6 includes a layer of solid pillar-shaped structure 65 and a layer of hollow pillar-shaped structure 66, and the solid pillar-shaped structure 65 is located on a side of the hollow pillar-shaped structure 66 away from the CMOS measurement circuitry. Thus, the pillar structure 6 formed by superimposing the solid pillar structure and the hollow pillar structure connects the suspended micro-bridge structure 40 and the supporting base 42, so that the pillar structure 6 has the advantages of both the hollow pillar structure and the solid pillar structure described in the above embodiments.

For example, the pillars in the same layer in the columnar structure 6 may be the same type of pillars, that is, the pillars in the same layer in the columnar structure 6 may be all solid columnar structures or all hollow columnar structures, so that the pillars in the same layer may be formed by the same process steps, which is beneficial to simplifying the manufacturing process of the columnar structure 6. In addition, the same columnar structure 6 may further include different types of columns, and the same layer may also be provided with different types of columns, and the types of columns may be specifically set based on specific requirements of the infrared detector, which is not specifically limited in the embodiment of the present disclosure. From this, include the multilayer stand through setting up columnar structure 6, be favorable to reducing the height of each layer stand in the columnar structure 6, the height of stand is lower more, its straightness that steeps is better, consequently, easily form the better stand of straightness that steeps, thereby optimize the holistic straightness of 6 of columnar structure, the whole size of columnar structure 6 also can be accomplished littleer, be favorable to reducing 6 shared spaces of columnar structure, thereby increase the effective area of CMOS infrared sensing structure, and then improve the duty cycle, improve infrared detector's infrared detection sensitivity. In addition, the column structure 6 may further include more layers of columns, for example, three or more layers of columns, and each column may be a solid column structure or a hollow column structure.

With reference to fig. 1 to 16, the suspended microbridge structure includes an absorption plate 10 and a plurality of beam structures 11, the absorption plate 10 is used to convert an infrared signal into an electrical signal and is electrically connected to the corresponding pillar structures 6 through the corresponding beam structures 11, and at least one hole structure may be formed on the absorption plate 10, where the hole structure at least penetrates through a dielectric layer in the absorption plate 10; and/or, at least one hole-shaped structure is formed on the beam structure 11, that is, only the absorption plate 10, only the beam structure 11, or both the absorption plate 10 and the beam structure 11 may be provided with the hole-shaped structure. For example, whether the hole structures on the absorption plate 10 or the beam structure 11 are hole structures, the hole structures may be circular hole structures, square hole structures, polygonal hole structures, or irregular pattern hole structures, the shape of the hole structures on the absorption plate 10 and the beam structure 11 is not specifically limited by the embodiments of the present disclosure, and the number of the hole structures on the absorption plate 10 and the beam structure 11 is not specifically limited by the embodiments of the present disclosure.

Therefore, at least one hole-shaped structure is formed on the absorption plate 10, the hole-shaped structure at least penetrates through the dielectric layer in the absorption plate 10, and since a sacrificial layer which needs to be finally released is arranged between the reflection layer 4 and the absorption plate 10, and the sacrificial layer needs to be corroded by a chemical reagent at the end of the infrared detector manufacturing process when the sacrificial layer is released, the hole-shaped structure on the absorption plate 10 is beneficial to increasing the contact area between the chemical reagent for releasing and the sacrificial layer, and the release rate of the sacrificial layer is accelerated. In addition, the area of the absorption plate 10 is larger than that of the beam structure 11, the hole-shaped structure on the absorption plate 10 is beneficial to releasing the internal stress of the absorption plate 10, optimizing the planarization degree of the absorption plate 10, and being beneficial to improving the structural stability of the absorption plate 10, so that the structural stability of the whole infrared detector is improved. In addition, at least one hole-shaped structure is formed on the beam structure 11, which is beneficial to further reducing the thermal conductance of the beam structure 11 and improving the infrared detection sensitivity of the infrared detector.

Fig. 17 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure. As shown in fig. 17, at least one layer of hermetic release isolation layer 3 may be included above the CMOS measurement circuitry 1, and the hermetic release isolation layer 3 is used to protect the CMOS measurement circuitry 1 from the process during the release etching process for fabricating the CMOS infrared sensing structure 2. Optionally, the close release isolation layer 3 is located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, that is, the close release isolation layer 3 may be located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2, or the close release isolation layer 3 is located in the CMOS infrared sensing structure 2, or the close release isolation layer 3 is located at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 and is provided with the close release isolation layer 3, and the close release isolation layer 3 is used for protecting the CMOS measurement circuit system 1 from erosion when a sacrificial layer is released by a corrosion process, and the close release isolation layer 3 at least includes a dielectric layer, and a dielectric material constituting the close release isolation layer 3 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon, silicon germanium, silicon, germanium, silicon germanium alloy, amorphous carbon, or aluminum oxide.

Fig. 17 exemplarily sets the hermetic release barrier layer 3 in the CMOS infrared sensing structure 2, the hermetic release barrier layer 3 may be, for example, a dielectric layer or multiple dielectric layers above the metal interconnection layer of the reflective layer 4, here, the hermetic release barrier layer 3 is exemplarily shown to be a dielectric layer, and the material constituting the hermetic release barrier layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon-germanium alloy, amorphous carbon or aluminum oxide, and the thickness of the hermetic release barrier layer 3 is smaller than that of the sacrificial layer. The resonant cavity of the infrared detector is realized by releasing a vacuum cavity after a silicon oxide sacrificial layer is released, the reflecting layer 4 is used as a reflecting layer of the resonant cavity, the sacrificial layer is positioned between the reflecting layer 4 and the suspended microbridge structure 40, and when at least one layer of closed release isolating layer 3 positioned on the reflecting layer 4 is arranged to select silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium alloy, amorphous carbon or aluminum oxide and other materials as a part of the resonant cavity, the reflecting effect of the reflecting layer 4 is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrificial layer is further reduced, and the release difficulty of the sacrificial layer formed by silicon oxide is reduced. In addition, the sealing release isolation layer 3 and the columnar structure 6 are arranged to form a sealing structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the protection of the CMOS measurement circuit system 1 is realized.

Fig. 18 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the disclosure. On the basis of the above embodiment, fig. 18 also provides that the hermetic release isolation layer 3 is located in the CMOS infrared sensing structure 2, the hermetic release isolation layer 3 may be, for example, one or more dielectric layers located above the metal interconnection layer of the reflective layer 4, here, the hermetic release isolation layer 3 is exemplarily shown to be one dielectric layer, and the hermetic release isolation layer 3 covers the columnar structure 6, at this time, the material constituting the hermetic release isolation layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium alloy, amorphous carbon or aluminum oxide, and the thickness of the hermetic release isolation layer 3 is also smaller than that of the sacrificial layer. Through setting up airtight release insulating layer 3 cladding columnar structure 6, can utilize airtight release insulating layer 3 as the support of columnar structure 6 department on the one hand, improve columnar structure 6's stability, guarantee columnar structure 6 and unsettled microbridge structure 40 and support base 42's electricity and be connected. On the other hand, the airtight release insulating layer 3 coating the columnar structure 6 can reduce the contact between the columnar structure 6 and the external environment, reduce the contact resistance between the columnar structure 6 and the external environment, further reduce the noise of the pixel of the infrared detector, improve the detection sensitivity of the infrared detection sensor, and simultaneously prevent the electrical breakdown of the exposed metal of the columnar structure 6. Similarly, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrifice layer, the reflecting layer 4 is used as the reflecting layer of the resonant cavity, the sacrifice layer is positioned between the reflecting layer 4 and the suspended microbridge structure 40, and when at least one layer of closed release isolating layer 3 positioned on the reflecting layer 4 is arranged to select silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium alloy, amorphous carbon or aluminum oxide and other materials as a part of the resonant cavity, the reflecting effect of the reflecting layer 4 is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrifice layer is further reduced, and the release difficulty of the sacrifice layer formed by silicon oxide is reduced. In addition, the sealing release isolation layer 3 and the columnar structure 6 are arranged to form a sealing structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the protection of the CMOS measurement circuit system 1 is realized.

Fig. 19 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the disclosure. Unlike the infrared detector having the structure shown in the above-described embodiment, in the infrared detector having the structure shown in fig. 19, the close release isolation layer 3 is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the close release isolation layer 3 is located between the reflective layer 4 and the CMOS measurement circuitry 1, that is, the close release isolation layer 3 is located below the metal interconnection layer of the reflective layer 4, and the support base 42 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating through the close release isolation layer 3. Specifically, since the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, since silicon oxide is a most commonly used dielectric material in the CMOS process, and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, and in order to ensure that the silicon oxide medium on the CMOS measurement circuit system is not corroded when the silicon oxide of a sacrificial layer is released, a closed release insulating layer 3 is provided at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 according to the embodiment of the present disclosure. After the CMOS measuring circuit system 1 is prepared and formed, a closed release isolation layer 3 is prepared and formed on the CMOS measuring circuit system 1, the CMOS measuring circuit system 1 is protected by the closed release isolation layer 3, in order to ensure the electric connection between the support base 42 and the CMOS measuring circuit system 1, after the closed release isolation layer 3 is prepared and formed, a through hole is formed in the area of the closed release isolation layer 3 corresponding to the support base 42 by adopting an etching process, and the support base 42 is electrically connected with the CMOS measuring circuit system 1 through the through hole. In addition, the closed release isolation layer 3 and the support base 42 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Illustratively, the material constituting hermetic release barrier layer 3 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, a silicon germanium alloy, amorphous carbon, or aluminum oxide. Specifically, silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, a silicon germanium alloy, amorphous carbon, or aluminum oxide are all CMOS process corrosion-resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 3 can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer 3 covers the CMOS measurement circuit system 1, and the closed release isolation layer 3 can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the release etching process for manufacturing the CMOS infrared sensing structure 2. In addition, when being provided with at least one deck airtight release insulating layer 3 on reflection stratum 4, the material that sets up to constitute airtight release insulating layer 3 includes silicon, germanium, silicon germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, carborundum, aluminium oxide, at least one in silicon nitride or the silicon carbonitride, when setting up airtight release insulating layer 3 and improving the stability of columnar structure 6, airtight release insulating layer 3 can hardly influence the reflection course in the resonant cavity, can avoid airtight release insulating layer 3 to influence the reflection course of resonant cavity, and then avoid airtight release insulating layer 3 to infrared detector detection sensitivity's influence.

Illustratively, with reference to fig. 17 and fig. 18, when the close release isolation layer 3 is disposed between the reflective layer 4 and the suspended micro-bridge structure 40, at least one patterned metal interconnection layer 7 may be disposed on one side of the close release isolation layer 3 away from the CMOS measurement circuit system 1 and/or at least one patterned metal interconnection layer 7 may be disposed on one side of the close release isolation layer 3 close to the CMOS measurement circuit system 1, that is, at least one patterned metal interconnection layer 7 may be disposed on one side of the close release isolation layer 3 away from the CMOS measurement circuit system 1, at least one patterned metal interconnection layer 7 may be disposed on one side of the close release isolation layer 3 close to the CMOS measurement circuit system 1, and at least one patterned metal interconnection layer 7 may be disposed on both one side of the close release isolation layer 3 away from the CMOS measurement circuit system 1 and one side of the close release isolation layer 3 close to the CMOS measurement circuit system 1.

Fig. 17 exemplarily sets the side of the hermetic release barrier 3 away from the CMOS measurement circuitry 1 to be provided with a patterned metal interconnection layer 7, and when the material constituting the hermetic release barrier 3 is an insulating material, the patterned metal interconnection layer 7 may be set as shown in fig. 17 to be located at the side of the hermetic release barrier 3 away from the CMOS measurement circuitry 1 and to be disposed in contact with the hermetic release barrier 3, with the hermetic release barrier 3 serving as an electrical insulating layer between the patterned metal interconnection layer 7 and the reflective layer 4. When the material constituting the hermetic release barrier layer 3 is a conductive material, the patterned metal interconnection layer 7 may be disposed on the side of the hermetic release barrier layer 3 away from the CMOS measurement circuit system 1 and at least one electrical insulation layer is disposed between the patterned metal interconnection layer 7 and the hermetic release barrier layer 3 as shown in fig. 20, and fig. 20 exemplarily provides one electrical insulation layer 74 disposed between the patterned metal interconnection layer 7 and the hermetic release barrier layer 3, so as to achieve electrical insulation between the patterned metal interconnection layer 7 and the reflective layer 4 by using the electrical insulation layer 74. In addition, when the side of the hermetic release barrier layer 3 away from the CMOS measurement circuitry 1 is provided with a plurality of patterned metal interconnect layers 7, an electrically insulating layer may also be provided between adjacent patterned metal interconnect layers 7 to achieve electrical insulation between different patterned metal interconnect layers 7.

Fig. 18 exemplarily sets the side of the hermetic release barrier layer 3 adjacent to the CMOS measurement circuitry 1 to be provided with a patterned metal interconnection layer 7, may set the patterned metal interconnection layer 7 at the side of the reflective layer 4 away from the CMOS measurement circuitry with at least one electrical insulation layer disposed between the patterned metal interconnection layer 7 and the reflective layer 4, and fig. 18 exemplarily sets the patterned metal interconnection layer 7 and the reflective layer 4 to be provided with an electrical insulation layer 75 disposed therebetween to achieve electrical insulation between the patterned metal interconnection layer 7 and the reflective layer 4. In addition, when the side of the hermetic release barrier layer 3 adjacent to the CMOS measurement circuitry 1 is provided with a plurality of patterned metal interconnection layers 7, it is also possible to provide an electrically insulating layer between adjacent patterned metal interconnection layers 7 to achieve electrical insulation between different patterned metal interconnection layers 7. It should be noted that fig. 2, 13, 17, and 18 exemplarily set the patterned metal interconnection layer 7 to be distributed in the whole area where the infrared detector pixel is located, or set the patterned metal interconnection layer 7 to be distributed in a part of the area where the infrared detector pixel is located, so as to ensure that at least the area where the absorption plate 10 is located is correspondingly provided with the patterned metal interconnection layer 7, and the patterned metal interconnection layer 7 is electrically insulated from the reflection layer 4, which means that the patterned metal interconnection layer 7 is electrically insulated from the reflection plate 41 and the supporting base 42.

With reference to fig. 1 to 20, a CMOS fabrication process of the CMOS infrared sensing structure 2 includes a Metal interconnection process, a via process, an IMD (Inter Metal Dielectric) process, and an RDL (redistribution) process, where the CMOS infrared sensing structure 2 includes at least two Metal interconnection layers, at least two Dielectric layers, and a plurality of interconnection vias, the Dielectric layers include at least one sacrificial layer and one thermal sensitive Dielectric layer, the Metal interconnection layers include at least a reflective layer 4 and an electrode layer 14, the thermal sensitive Dielectric layer includes a thermal sensitive material having a resistance temperature coefficient greater than a predetermined value, for example, the resistance temperature coefficient may be greater than or equal to 0.015/K, the thermal sensitive material having a resistance temperature coefficient greater than the predetermined value forms the thermal sensitive Dielectric layer, and the thermal sensitive Dielectric layer is configured to convert a temperature change corresponding to infrared radiation absorbed by the thermal sensitive Dielectric layer into a resistance change, and further convert an infrared target signal into a signal capable of being electrically read through the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

Specifically, the metal interconnection process is used to achieve electrical connection between upper and lower metal interconnection layers, for example, to achieve electrical connection between an electrode layer in the pillar structure 6 and the support base 42, the via process is used to form an interconnection via for connecting the upper and lower metal interconnection layers, for example, to form an interconnection via for connecting the electrode layer in the pillar structure 6 and the support base, the IMD process is used to achieve isolation, that is, electrical insulation, between the upper and lower metal interconnection layers, for example, to achieve electrical insulation between the electrode layer in the absorber plate 10 and the beam structure 11 and the reflector plate 41, the RDL process is a redistribution layer process, that is, a process in which a layer of metal is re-laid above the top layer of metal of the circuit and is electrically connected to a metal column in the top layer of metal of the circuit, for example, a tungsten column, and the RDL process can be used to re-fabricate the reflective layer 4 in the infrared detector on the top layer of metal of the CMOS measurement circuit system 1, and the support base 42 on the reflective layer 4 is electrically connected to the top layer of metal of the CMOS measurement circuit system 1. In addition, as shown in fig. 2, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, which are arranged at intervals, and the upper and lower metal interconnection layers 101 are electrically connected through vias 104.

With reference to fig. 1 to 20, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 4 and a heat sensitive dielectric layer, a suspended microbridge structure 40 for controlling heat transfer, and a columnar structure 6 having electrical connection and support functions, the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2 and convert an infrared signal into an image electrical signal, the infrared detector includes a plurality of infrared detector pixels arranged in an array, and each infrared detector pixel includes one CMOS infrared sensing structure 2. Specifically, the resonant cavity may be formed by a cavity between the reflective layer 4 and the heat-sensitive medium layer in the absorption plate 10, for example, the infrared light is reflected back and forth in the resonant cavity through the absorption plate 10 to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structure 6, the beam structure 11 and the absorption plate 10 form a suspended micro-bridge structure 40 for controlling the heat transfer, and the columnar structure 6 is electrically connected to the supporting base 42 and the corresponding beam structure 11 and is used for supporting the suspended micro-bridge structure 40 on the columnar structure 6.

Fig. 21 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. With reference to fig. 1 to fig. 21, the cmos measurement circuit system 1 includes a bias generation circuit 70, a column-level analog front-end circuit 80 and a row-level circuit 90, an input end of the bias generation circuit 70 is connected to an output end of the row-level circuit 90, an input end of the column-level analog front-end circuit 80 is connected to an output end of the bias generation circuit 70, the row-level circuit 90 includes row-level mirror image elements Rsm and row selection switches K1, and the column-level analog front-end circuit 80 includes blind image elements RD; the row-level circuit 90 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing generation circuit, and outputs a current signal to the column-level analog front-end circuit 80 under the action of the bias generation circuit 70 to perform current-voltage conversion and output; the row stage circuit 90 outputs a third bias voltage VRsm to the bias generation circuit 70 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 70 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front end circuit 80 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, and performs transimpedance amplification on the difference between the two generated currents to output as an output voltage.

Specifically, the row-level circuit 90 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 90 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. Illustratively, the row-level image elements Rsm may be subjected to a shading process, so that the row-level image elements Rsm are subjected to a fixed radiation of a shading sheet having a temperature constantly equal to the substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 70, that is, the row-level circuit 90 outputs the third bias voltage VRsm to the bias generation circuit 70 when being controlled by the row selection switch K1 to be turned on. The bias voltage generating circuit 70 may include a first bias voltage generating circuit 710 and a second bias voltage generating circuit 720, the first bias voltage generating circuit 710 is configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 720 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 80 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed corresponding to the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed corresponding to the gate driving sub-circuits 722 in a one-to-one manner, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81. The column-level analog front-end circuit 80 includes an effective pixel RS and a blind pixel RD, the column control sub-circuit is configured to generate a first current I1 according to a first bias voltage V1 and the blind pixel RD, generate a second current I2 according to a second bias voltage V2 and the effective pixel RS, perform transimpedance amplification on a difference between the first current I1 and the second current I2, and output the amplified difference, and the row-level image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 10 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorbing plates 10 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measuring circuit system 1, so that the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated by the row selection switch K1, the resistance value of both the row-level mirror image element Rsm and the effective pixel RS changes due to joule heat, but when the row-level mirror image element Rsm and the effective pixel RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective pixel RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective pixel RS are also the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective pixel RS at the same environmental temperature are the same, the changes of the row-level mirror image element Rsm and the effective pixel RS at the same environmental temperature are synchronized, the characteristic that the temperature drift amounts of the row-level mirror image element Rsm and the effective pixel RS at the same environmental temperature are the utilized is favorable for effectively compensating the resistance value changes of the row-level mirror image element Rsm and the effective pixel RS due to the self-heating effect, and realizing the stable output of the CMOS measurement circuit system 1.

In addition, by arranging the second bias generating circuit 720 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is used to control the gate driving sub-circuits 722 to generate the corresponding second bias voltages V2 respectively according to the row control signals, so that each row of pixels has one path to drive the whole row of pixels of the row separately, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 70 is improved, which is beneficial to driving a larger-scale infrared detector pixel array by using the CMOS measuring circuit system 1. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on a metal interconnect layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 1 to 20, the CMOS infrared sensing structure 2 may be fabricated on the top metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 42 on the top metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit the electrical signal converted by the infrared signal to the CMOS measurement circuitry 1.

Fig. 22 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure. As shown in fig. 22, the CMOS infrared sensing structure 2 may also be prepared on the same layer as the metal interconnection layer of the CMOS measurement circuitry 1, that is, the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, for example, as shown in fig. 22, the CMOS infrared sensing structure 2 may be arranged on one side of the CMOS measurement circuitry 1, and the top of the CMOS measurement circuitry 1 may also be provided with a hermetic release isolation layer 3 to protect the CMOS measurement circuitry 1.

Optionally, in conjunction with fig. 1 to 22, the sacrificial layer is used to form the CMOS infrared sensing structure 2 into a hollow structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process. For example, the post-CMOS process may etch the sacrificial layer using at least one of gases having corrosive properties to silicon oxide, such as gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane. Specifically, a sacrificial layer (not shown in fig. 1 to 22) is provided between the reflective layer 4 and the suspended microbridge structure 40, and when the hermetic release isolation layer 3 is provided on the reflective layer 4, the sacrificial layer is provided between the hermetic release isolation layer 3 and the suspended microbridge structure 40, and the material constituting the sacrificial layer is silicon oxide, so as to be compatible with a CMOS process, a post-CMOS process may be adopted, that is, the post-CMOS process corrodes the sacrificial layer to release the sacrificial layer in the final infrared detection chip product.

Optionally, the absorption plate 10 is used for absorbing the infrared target signal and converting the infrared target signal into an electrical signal, the absorption plate 10 includes a metal interconnection layer and at least one thermal sensitive medium layer, the metal interconnection layer in the absorption plate 10 is an electrode layer 14 in the absorption plate 10 for transmitting the electrical signal converted from the infrared signal. The beam structures 11 and the columnar structures 6 are used for transmitting electrical signals and for supporting and connecting the absorption plates 10, the electrode layers 14 in the absorption plates 10 comprise two patterned electrode structures, the two patterned electrode structures output positive electrical signals and grounding electrical signals respectively, and the positive electrical signals and the grounding electrical signals are transmitted to the supporting base 42 electrically connected with the columnar structures 6 through the different beam structures 11 and the different columnar structures 6 and then transmitted to the CMOS measurement circuit system 1. The beam structure 11 comprises at least a metal interconnection layer, the metal interconnection layer in the beam structure 11 is an electrode layer 14 in the beam structure 11, and the electrode layer 14 in the beam structure 11 and the electrode layer 14 in the absorber plate 10 are electrically connected. The beam structure 11 and the CMOS measurement circuit system 1 are connected by the columnar structure 6 through a metal interconnection process and a through hole process, the upper side of the columnar structure 6 is electrically connected to the electrode layer 14 in the beam structure 11 through a through hole penetrating through the sacrificial layer, the lower side of the columnar structure 6 is electrically connected to the corresponding support base 42 through a through hole penetrating through the dielectric layer on the support base 42, and the electrode layer 14 in the beam structure 11 is electrically connected to the corresponding support base 42 through the corresponding columnar structure 6. The reflective plate 41 is used for reflecting infrared signals and forming a resonant cavity with the heat-sensitive medium layer 12, that is, the reflective plate 41 is used for reflecting infrared signals and forming a resonant cavity with the heat-sensitive medium layer 12, and the reflective layer 4 includes at least one metal interconnection layer which is used for forming a supporting base 42 and is also used for forming the reflective plate 41.

Optionally, the beam structure 11 may include a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, the absorber plate 10 includes the first dielectric layer 13 and the electrode layer 14, or the absorber plate 10 includes the electrode layer 14 and the second dielectric layer 15, or the absorber plate 10 includes the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15, or the absorber plate 10 includes the support layer, the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15, or the absorber plate 10 includes the first dielectric layer 13, the electrode layer 14, the second dielectric layer 15, and the passivation layer, or the absorber plate 10 includes the support layer, the first dielectric layer 13, the electrode layer 14, the second dielectric layer 15, and the passivation layer; the material forming the first dielectric layer 13 includes at least one of materials with a temperature coefficient of resistance greater than a set value, which are prepared from amorphous silicon, amorphous germanium, amorphous silicon germanium or amorphous carbon, and the material forming the second dielectric layer 15 includes at least one of materials with a temperature coefficient of resistance greater than a set value, which are prepared from amorphous silicon, amorphous germanium, amorphous silicon germanium or amorphous carbon, and the set value may be 0.015/K, for example.

Specifically, with reference to fig. 13, 18, and 22, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, and the absorber plate 10 sequentially includes the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15, that is, the same and same film layers formed by the beam structure 11 and the absorber plate 10 may be simultaneously manufactured, the material forming the first dielectric layer 13 includes at least one of materials having a temperature coefficient of resistance greater than a set value and prepared from amorphous silicon, amorphous germanium silicon, or amorphous carbon, and the material forming the second dielectric layer 15 includes at least one of materials having a temperature coefficient of resistance greater than a set value and prepared from amorphous silicon, amorphous germanium silicon, or amorphous carbon, that is, the first dielectric layer 13 serves as a support layer and also serves as a thermally sensitive dielectric layer, and the second dielectric layer 15 serves as a passivation layer and also serves as a thermally sensitive dielectric layer, which is beneficial to reducing the thickness of the absorber plate 10, reducing the thermal conductivity of the beam structure 11, and simplifying the manufacturing process of the infrared detector.

Specifically, the supporting layer is used for supporting an upper film layer in the suspended micro-bridge structure 40 after the sacrificial layer is released, the heat sensitive medium layer is used for converting infrared temperature detection signals into infrared detection electric signals, the electrode layer 14 is used for transmitting the infrared detection electric signals converted by the heat sensitive medium layer to the CMOS measurement circuit system 1 through the beam structures 11 on the left side and the right side, the two beam structures 11 respectively transmit positive and negative signals of the infrared detection electric signals, a reading circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and the passivation layer is used for protecting the electrode layer 14 from oxidation or corrosion. Corresponding to the absorption plate 10 and the beam structure 11, the electrode layer 14 is located in a closed space formed by the first dielectric layer 13, namely the support layer, and the second dielectric layer 15, namely the passivation layer, so that the protection of the electrode layer 14 in the absorption plate 10 and the beam structure 11 is realized.

Exemplarily, on the premise that the material constituting the first dielectric layer 13 includes at least one of the materials with the temperature coefficient of resistance greater than the set value, which are made of amorphous silicon, amorphous germanium-silicon or amorphous carbon, and the material constituting the second dielectric layer 15 includes at least one of the materials with the temperature coefficient of resistance greater than the set value, which are made of amorphous silicon, amorphous germanium-silicon or amorphous carbon, the film layers in the beam structure 11 and the absorber plate 10 may further satisfy the following conditions: in the first case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, and the absorber plate 10 sequentially includes the first dielectric layer 13 and the electrode layer 14; in the second case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, and the absorber plate 10 sequentially includes the electrode layer 14 and the second dielectric layer 15; in a third case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, the absorber plate 10 sequentially includes a supporting layer, a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, or the absorber plate 10 sequentially includes a supporting layer, an electrode layer 14, a first dielectric layer 13, and a second dielectric layer 15, or the absorber plate 10 sequentially includes a supporting layer, a first dielectric layer 13, a second dielectric layer 15, and an electrode layer 14; in a fourth situation, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, and the absorber plate 10 sequentially includes the first dielectric layer 13, the electrode layer 14, the second dielectric layer 15, and a passivation layer, or the absorber plate 10 sequentially includes the electrode layer 14, the first dielectric layer 13, the second dielectric layer 15, and the passivation layer, or the absorber plate 10 sequentially includes the first dielectric layer 13, the second dielectric layer 15, the electrode layer 14, and the passivation layer; in a fifth case, it may be set that, in a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15, and the absorber plate 10 sequentially includes a support layer, a first dielectric layer 13, an electrode layer 14, a second dielectric layer 15, and a passivation layer, or the absorber plate 10 sequentially includes a support layer, an electrode layer 14, a first dielectric layer 13, a second dielectric layer 15, and a passivation layer, or the absorber plate 10 sequentially includes a support layer, a first dielectric layer 13, a second dielectric layer 15, an electrode layer 14, and a passivation layer. In the five cases, the first dielectric layer and the second dielectric layer can both serve as heat-sensitive dielectric layers, the dielectric layer located at the lowermost portion of the suspended microbridge structure 40 can also serve as a supporting layer, and the dielectric layer located at the uppermost portion of the suspended microbridge structure 40 can also serve as a passivation layer.

Optionally, the beam structure 11 includes an electrode layer 14, or the beam structure 11 includes a first dielectric layer 13 and an electrode layer 14, or the beam structure 11 includes an electrode layer 14 and a second dielectric layer 15, or the beam structure 11 includes an electrode layer 14 and a heat sensitive dielectric layer 12, or the beam structure 11 includes a first dielectric layer 13, an electrode layer 14 and a second dielectric layer 15, or the beam structure 11 includes a first dielectric layer 13, an electrode layer 14 and a heat sensitive dielectric layer 12, or the beam structure 11 includes an electrode layer 14, a heat sensitive dielectric layer 12 and a second dielectric layer 15, or the beam structure 11 includes a first dielectric layer 13, an electrode layer 14, a heat sensitive dielectric layer 12 and a second dielectric layer 15, and the absorption plate 10 includes an electrode layer 14 and a heat sensitive dielectric layer 12, or the absorption plate 10 includes a first dielectric layer 13, an electrode layer 14 and a heat sensitive dielectric layer 12, or the absorption plate 10 includes an electrode layer 14, a heat sensitive dielectric layer 12 and a second dielectric layer 15, or the absorption plate 10 includes a first dielectric layer 13, an electrode layer 14, a heat sensitive dielectric layer 12 and a second dielectric layer 15; the material forming the first dielectric layer 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide or amorphous carbon, the material forming the second dielectric layer 15 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide or amorphous carbon, the material forming the thermally sensitive dielectric layer 12 includes at least one of materials having a temperature coefficient of resistance greater than a set value, which is prepared from titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, germanium silicon oxide, graphene, a barium strontium titanate film, copper or platinum, and the set value may be, for example, 0.015/K.

Fig. 23 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the disclosure. With reference to fig. 2, 17, 20, and 23, the beam structure 11 may sequentially include a first dielectric layer 13, an electrode layer 14, and a second dielectric layer 15 along a direction away from the CMOS measurement circuit system 1, the absorber plate 10 sequentially includes the first dielectric layer 13, the electrode layer 14, the heat sensitive dielectric layer 12, and the second dielectric layer 15, where the first dielectric layer 13 serves as a supporting layer, the second dielectric layer 15 serves as a passivation layer, and the heat sensitive dielectric layer 12 converts an infrared signal into an electrical signal. Corresponding to the absorption plate 10 and the beam structure 11, the electrode layer 14 is located in a closed space formed by the first dielectric layer 13, namely the support layer, and the second dielectric layer 15, namely the passivation layer, so that the protection of the electrode layer 14 in the absorption plate 10 and the beam structure 11 is realized.

Illustratively, on the premise that the material constituting the first dielectric layer 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide or amorphous carbon, and the material constituting the second dielectric layer 15 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide or amorphous carbon, the beam structure 11 and the film layer in the absorber plate 10 may also satisfy the following conditions: in the first case, the beam structure 11 may be provided with an electrode layer 14, and the absorber plate 10 sequentially includes the electrode layer 14 and the heat-sensitive medium layer 12 or the absorber plate 10 sequentially includes the heat-sensitive medium layer 12 and the electrode layer 14 along the direction away from the CMOS measurement circuit system 1; in a second case, the beam structure 11 may include an electrode layer 14, and the absorption plate 10 sequentially includes a first dielectric layer 13, an electrode layer 14 and a heat-sensitive dielectric layer 12 or the absorption plate 10 sequentially includes a first dielectric layer 13, a heat-sensitive dielectric layer 12 and an electrode layer 14 along a direction away from the CMOS measurement circuit system 1; in a third case, the beam structure 11 may include an electrode layer 14, and along a direction away from the CMOS measurement circuit system 1, the absorption plate 10 sequentially includes the electrode layer 14, the thermal sensitive medium layer 12, and the second medium layer 15, or the absorption plate 10 sequentially includes the thermal sensitive medium layer 12, the electrode layer 14, and the second medium layer 15; a fourth case may be that the beam structure 11 comprises an electrode layer 14, and the absorber plate 10 comprises a first dielectric layer 13, an electrode layer 14, a thermally sensitive dielectric layer 12 and a second dielectric layer 15 in that order, or the absorber plate 10 comprises a first dielectric layer 13, a thermally sensitive dielectric layer 12, an electrode layer 14 and a second dielectric layer 15 in that order, in a direction away from the CMOS measurement circuitry 1.

A fifth case may be set along a direction away from the CMOS measurement circuit system 1, where the beam structure 11 sequentially includes the first dielectric layer 13 and the electrode layer 14 or the beam structure 11 sequentially includes the electrode layer 14 and the second dielectric layer 15, and the absorption plate 10 sequentially includes the electrode layer 14 and the heat-sensitive dielectric layer 12 or the absorption plate 10 sequentially includes the heat-sensitive dielectric layer 12 and the electrode layer 14; in a sixth case, the beam structure 11 sequentially includes a first dielectric layer 13 and an electrode layer 14 or the beam structure 11 sequentially includes an electrode layer 14 and a second dielectric layer 15, and the absorption plate 10 sequentially includes a first dielectric layer 13, an electrode layer 14 and a heat-sensitive dielectric layer 12 or the absorption plate 10 sequentially includes a first dielectric layer 13, a heat-sensitive dielectric layer 12 and an electrode layer 14; in a seventh case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and sequentially includes the first dielectric layer 13 and the electrode layer 14, or the beam structure 11 sequentially includes the electrode layer 14 and the second dielectric layer 15, and the absorption plate 10 sequentially includes the electrode layer 14, the heat-sensitive dielectric layer 12, and the second dielectric layer 15, or the absorption plate 10 sequentially includes the heat-sensitive dielectric layer 12, the electrode layer 14, and the second dielectric layer 15; in an eighth case, it may be set that in a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes a first dielectric layer 13 and an electrode layer 14 or the beam structure 11 sequentially includes an electrode layer 14 and a second dielectric layer 15, and the absorber plate 10 sequentially includes a first dielectric layer 13, an electrode layer 14, a heat-sensitive dielectric layer 12 and a second dielectric layer 15 or the absorber plate 10 sequentially includes a first dielectric layer 13, a heat-sensitive dielectric layer 12, an electrode layer 14 and a second dielectric layer 15.

A ninth case may be that the beam structure 11 sequentially includes an electrode layer 14 and a thermal sensitive medium layer 12 and the absorption plate 10 sequentially includes the electrode layer 14 and the thermal sensitive medium layer 12, or the beam structure 11 sequentially includes the thermal sensitive medium layer 12 and the electrode layer 14 and the absorption plate 10 sequentially includes the thermal sensitive medium layer 12 and the electrode layer 14; in a tenth case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and the beam structure 11 sequentially includes the electrode layer 14 and the heat sensitive medium layer 12, and the absorption plate 10 sequentially includes the first medium layer 13, the electrode layer 14, and the heat sensitive medium layer 12, or the beam structure 11 sequentially includes the heat sensitive medium layer 12 and the electrode layer 14, and the absorption plate 10 sequentially includes the first medium layer 13, the heat sensitive medium layer 12, and the electrode layer 14; in an eleventh case, the beam structure 11 may be arranged along a direction away from the CMOS measurement circuit system 1, and the beam structure 11 sequentially includes the electrode layer 14 and the heat sensitive medium layer 12, and the absorption plate 10 sequentially includes the electrode layer 14, the heat sensitive medium layer 12, and the second medium layer 15, or the beam structure 11 sequentially includes the heat sensitive medium layer 12 and the electrode layer 14, and the absorption plate 10 sequentially includes the heat sensitive medium layer 12, the electrode layer 14, and the second medium layer 15; a twelfth case may be that, along a direction away from the CMOS measurement circuit system 1, the beam structure 11 sequentially includes the electrode layer 14 and the heat sensitive medium layer 12, and the absorption plate 10 sequentially includes the first medium layer 13, the electrode layer 14, the heat sensitive medium layer 12, and the second medium layer 15, or the beam structure 11 sequentially includes the heat sensitive medium layer 12 and the electrode layer 14, and the absorption plate 10 sequentially includes the first medium layer 13, the heat sensitive medium layer 12, the electrode layer 14, and the second medium layer 15.

Referring to the above discussion logics of different cases, when the material forming the first dielectric layer 13 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon, and the material forming the second dielectric layer 15 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon, there may be a plurality of combinations of the case of selecting one film layer for the beam structure 11 and the case of selecting one film layer for the absorber plate 10, that is, the case of selecting one film layer for the beam structure 11 and the case of selecting one film layer for the absorber plate 10 may be combined arbitrarily to form an infrared detector with a plurality of structures, which is not described herein again. It should be noted that, whatever the above-mentioned film layer arrangement scheme of the beam structure 11 and the absorption plate 10, it is necessary to ensure that at least the electrode layer 14 is in the beam structure 11, and at least the electrode layer 14 is in the absorption plate 12, and the dielectric layer is used as a heat sensitive dielectric layer.

Illustratively, the material constituting the electrode layer 14 may be configured to include at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, nickel silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper, wherein when the material of the electrode layer 14 is at least one of titanium, titanium nitride, tantalum, or tantalum nitride, the electrode layer 14 is preferably configured to be coated with the first dielectric layer 13 and the second dielectric layer 15, so as to prevent the electrode layer 14 from being affected by the etching process. In addition, in the above embodiment, at least one hole structure may be formed on the absorption plate 10, the hole structure at least penetrates through the dielectric layer in the absorption plate 10, the beam structure 11 at least forms one hole structure, when the beam structure 11 only includes the electrode layer 14, the hole structure on the beam structure 11 penetrates through the electrode layer 14 in the beam structure 11, when the beam structure 11 includes the dielectric layer, the hole structure at least penetrates through the dielectric layer in the beam structure 11, taking the infrared detector of the structures shown in fig. 13, fig. 18, and fig. 22 as an example, at this time, the hole structure on the absorption plate 10 may penetrate through the first dielectric layer 13 and the second dielectric layer 15 in the absorption plate 10, the hole structure on the absorption plate 10 may also penetrate through the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15 in the absorption plate 10, the hole structure on the beam structure 11 may penetrate through the first dielectric layer 13 and the second dielectric layer 15 in the beam structure 11 where the electrode layer 14 is not provided, or the hole structure on the beam structure 11 penetrates through the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15 in the beam structure 11. Taking the infrared detector with the structure shown in fig. 2, fig. 17, fig. 20, and fig. 23 as an example, at this time, the hole structure on the absorption plate 10 may penetrate through the first dielectric layer 13 and the second dielectric layer 15 in the absorption plate 10, the hole structure on the absorption plate 10 may penetrate through the first dielectric layer 13, the electrode layer 14, the heat sensitive dielectric layer 12, and the second dielectric layer 15 in the absorption plate 10, the hole structure on the beam structure 11 may penetrate through the first dielectric layer 13 and the second dielectric layer 15 in the beam structure 11 where the electrode layer 14 is not provided, or the hole structure on the beam structure 11 penetrates through the first dielectric layer 13, the electrode layer 14, and the second dielectric layer 15 in the beam structure 11.

Optionally, the infrared detector may further include a metamaterial structure and/or a polarization structure, and the metamaterial structure or the polarization structure is at least one metal interconnection layer. For example, the metal interconnection layer constituting the metamaterial structure may include a plurality of metal repeating units arranged in an array, each metal repeating unit includes two diagonally arranged L-shaped patterned structures, and an infrared absorption spectrum of the infrared detector is in a 3-30 μm band. A plurality of patterned hollow structures arranged in an array can be arranged on the metal interconnection layer forming the metamaterial structure, the patterned hollow structures are in an open ring shape, and the infrared absorption spectrum band of the infrared detector is 3-30 micrometers. The metal interconnection layer forming the metamaterial structure can also be provided with a plurality of linear strip structures and a plurality of inflection strip structures, the linear strip structures and the inflection strip structures are alternately arranged along the direction perpendicular to the linear strip structures, and the infrared absorption spectrum band of the infrared detector is 8-24 microns. A plurality of patterned hollow structures arranged in an array can be arranged on the metal interconnection layer forming the metamaterial structure, the patterned hollow structures are in a regular hexagon shape, and the infrared absorption spectrum band of the infrared detector is 3-30 micrometers. It should be noted that, in the embodiments of the present disclosure, specific patterns on the metal interconnection layer constituting the metamaterial structure are not limited, and it is sufficient to ensure that the repeated patterns can realize the functions of the metamaterial structure or the polarization structure.

Therefore, the metamaterial structure formed by the patterned structure is combined with the infrared detector structure, the infrared electromagnetic wave absorbed by the metamaterial structure can enhance the infrared electromagnetic wave signal absorbed by the infrared detector, the infrared electromagnetic wave absorbed by the metamaterial structure is superposed with the infrared electromagnetic wave absorbed by the microbridge detector structure, the infrared electromagnetic wave absorbed by the metamaterial structure is coupled with the incident infrared electromagnetic wave component, namely, the intensity of the absorbed infrared electromagnetic wave signal is increased due to the arrangement of the metamaterial structure, and the absorption rate of the infrared detector to the incident infrared electromagnetic wave is improved.

The polarization structure can comprise a plurality of gratings which are arranged in sequence, the interval between every two adjacent gratings is 10nm to 500nm, the gratings can be linear or bent, the gratings in the polarization structure can rotate or be combined at any angle, and the arrangement of the polarization structure can enable the CMOS sensing structure to absorb polarized light in a specific direction. Illustratively, the grating may be a structure formed by etching a metal thin film, i.e., a metal interconnection layer. According to the embodiment of the disclosure, the polarization structure and the uncooled infrared detector are monolithically integrated, so that not only can monolithic integration of the polarization-sensitive infrared detector be realized, but also the difficulty of optical design is greatly reduced, an optical system is simplified, optical elements are reduced, and the cost of the optical system is reduced. In addition, the image collected by the single-chip integrated polarization uncooled infrared detector is original infrared image information, the CMOS measuring circuit system 1 can obtain accurate image information only by processing signals detected by the infrared detector, image fusion of the existing detector is not needed, and authenticity and effectiveness of the image are greatly improved. In addition, the polarization structure can also be located above the absorption plate 10 and is not in contact with the absorption plate 10, namely the polarization structure can be a suspended structure located above the suspended microbridge structure 40, the polarization structure and the suspended microbridge structure 40 can adopt a column connection supporting mode or a bonding supporting mode, the polarization structure and the infrared detector pixel can be bonded in a one-to-one correspondence manner, and a whole chip bonding manner can also be adopted. Therefore, the independent suspended metal grating structure cannot cause deformation of the infrared sensitive micro-bridge structure and cannot influence the heat-sensitive characteristic of the sensitive film.

Exemplarily, referring to fig. 1 to 23, the meta-material structure and the polarization structure are disposed corresponding to the position of the absorption plate 10, the meta-material structure is at least one metal interconnection layer, the polarization structure is at least one metal interconnection layer, the meta-material structure or the polarization structure may be at least one metal interconnection layer on the side of the first dielectric layer 13 adjacent to the CMOS measurement circuit system 1, for example, the metal interconnection layer constituting the meta-material structure or the polarization structure may be disposed on the side of the first dielectric layer 13 adjacent to the CMOS measurement circuit system 1 and in contact with the first dielectric layer 13, that is, the metal interconnection layer is disposed at the lowest position of the suspension micro-bridge structure 40. For example, the meta-material structure or the polarization structure may also be at least one metal interconnection layer on the side of the second dielectric layer 15 away from the CMOS measurement circuitry 1, and for example, the metal interconnection layer constituting the meta-material structure or the polarization structure may be located on the side of the second dielectric layer 15 away from the CMOS measurement circuitry 1 and in contact with the second dielectric layer 15, that is, the metal interconnection layer is located at the uppermost portion of the suspended microbridge structure 40. Illustratively, the metamaterial structure or the polarization structure may also be at least one metal interconnection layer located between the first dielectric layer 13 and the second dielectric layer 15 and electrically insulated from the electrode layer 14, for example, the metal interconnection layer constituting the metamaterial structure or the polarization structure may be located between the first dielectric layer 13 and the electrode layer 14 and electrically insulated from the electrode layer 14 or located between the second dielectric layer 15 and the electrode layer 14 and electrically insulated from the electrode layer 14. For example, the electrode layer 14 may also be disposed as a metamaterial structure layer or a polarization structure layer, that is, the patterned structure described in the above embodiments may be formed on the electrode layer 14.

Optionally, the columnar structure 6 may include at least one layer of solid columnar structure, the solid columnar structure includes the solid structure 601, as shown in fig. 13, a sidewall of the solid structure 601 may be disposed in contact with a sacrificial layer (not shown in fig. 13), a material constituting the solid structure 601 includes at least one of tungsten, copper, or aluminum, that is, the columnar structure 6 only includes a solid tungsten column, or a copper column, or an aluminum column, and the sidewall of the solid structure 601 is disposed in contact with the sacrificial layer, so that a manufacturing process of the columnar structure 6 is relatively simple and easy to implement, and is beneficial to reducing difficulty in manufacturing the entire infrared detector.

Fig. 24 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure. Unlike the infrared detector with the structure shown in fig. 13, the infrared detector with the structure shown in fig. 24 is provided with at least one dielectric layer 602 wrapped on the sidewall of the solid structure 601, and the solid structure 601 is disposed in contact with one dielectric layer 602, fig. 24 exemplarily provides that the sidewall of the solid structure 601 is wrapped with one dielectric layer 602 and the solid structure 601 is disposed in contact with the dielectric layer 602, the material constituting the solid structure 601 includes at least one of tungsten, copper or aluminum, and the material constituting the dielectric layer 602 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, graphene, copper or platinum.

Specifically, at least one dielectric layer 602 coating the solid structure 601 can play a role of electrical insulation, and when the dielectric layer 602 is used to protect the solid structure 601 from being corroded by external materials, the dielectric layer 602 can be used as an auxiliary supporting structure of the columnar structure 6, and supports the suspended micro-bridge structure 40 together with the solid structure 601, which is beneficial to improving the mechanical stability of the columnar structure 6, so that the structural stability of the infrared sensor is improved. In addition, the material forming the dielectric layer 602 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, graphene, copper, or platinum, and none of the foregoing materials is corroded by gaseous hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, so that the dielectric layer 602 covering the solid structure 601 is not corroded when the sacrificial layer is corroded by gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane in the subsequent process steps. For example, as shown in fig. 24, the dielectric layer 602 covering the solid structure 601 may be set as the first dielectric layer 13 in the suspended microbridge structure 40, and the dielectric layer covering the solid structure 601 may be a separately manufactured dielectric layer, or the dielectric layer covering the solid structure 601 may also be set as the second dielectric layer 15 or the heat-sensitive dielectric layer 12 in the suspended microbridge structure 40.

Fig. 25 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure. Unlike the infrared detector having the structure shown in fig. 13 and 24, the infrared detector having the structure shown in fig. 25 includes a sidewall of the solid structure 601 and a surface of the solid structure 601 adjacent to the CMOS measurement circuit system 1, which is covered with at least one adhesion layer 603, fig. 25 exemplarily includes a sidewall of the solid structure 601 and a surface of the solid structure 601 adjacent to the CMOS measurement circuit system 1, which is covered with one adhesion layer 603, a sidewall of the outermost periphery of the columnar structure 6, which is away from the solid structure 601, is covered with a dielectric layer 604, a material constituting the solid structure 601 includes at least one of tungsten, copper, or aluminum, a material constituting the adhesion layer 603 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride, and a material constituting the dielectric layer 604 includes at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium, germanium oxide, graphene, copper, or platinum.

Specifically, adhesion layer 603 is used for reinforcing the connectivity between columnar structure 6 and the support base 42, including intensifier mechanical connection performance, promote structural stability, also include intensifier electricity connectivity performance, reduce contact resistance, reduce the loss among the signal of telecommunication transmission process, infrared detector's infrared detection performance has been promoted, and still surround the side of solid structure 601 through setting up adhesion layer 603, can increase adhesion layer 603 and solid structure 601's area of contact, be equivalent to the transmission path of widening the signal of telecommunication, columnar structure 6's transmission resistance has been reduced, thereby further reduced the signal of telecommunication transmission loss, infrared detector's infrared detection performance has been promoted. In addition, the material forming the adhesion layer 603 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride, and the adhesion layer 603 is formed by using at least one of the four conductive materials, so that the requirement of enhancing the mechanical and electrical connection performance between the supporting base 42 and the columnar structure 6 by using the adhesion layer 603 can be met, and the requirement of preparing the adhesion layer 603 by using a CMOS process, that is, the requirement of integrating the CMOS process, can be met.

The side wall of the adhesion layer 603 on the outermost periphery in the columnar structure 6, which is far away from the solid structure 601, is further coated with the dielectric layer 604, the adhesion layer 603 is utilized to enhance the connection performance between the columnar structure 6 and the supporting base 42, and meanwhile, the dielectric layer 604 coating the side wall of the adhesion layer 603 plays a role in insulation protection, and the dielectric layer 604 can be utilized to play a role in auxiliary support of the columnar structure 6, so that the structural stability and the infrared detection performance of the infrared detector are improved. Similarly, the material forming the dielectric layer 604 may include at least one of silicon oxide, silicon nitride, silicon carbide, amorphous carbon, aluminum oxide, titanium oxide, vanadium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, graphene, copper, or platinum, which are not corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, and thus the dielectric layer 604 covering the adhesion layer 603 is not corroded when the sacrificial layer is corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane in the subsequent process steps. For example, as shown in fig. 25, the adhesion layer 603 covering the solid structure 601 may be provided as the electrode layer 14 in the suspended microbridge structure 40, the dielectric layer 604 covering the adhesion layer 603 is the first dielectric layer 13 in the suspended microbridge structure 40, and the adhesion layer 603 covering the solid structure 601 and/or the dielectric layer 604 covering the adhesion layer 603 may also be a separately manufactured film layer, or the dielectric layer covering the adhesion layer 603 may also be provided as the second dielectric layer 15 or the heat-sensitive dielectric layer 12 in the suspended microbridge structure 40.

Optionally, in combination with fig. 2, 13, 23, 24 and 25, the infrared detector may further include a reinforcing structure 16, where the reinforcing structure 16 is disposed corresponding to the position of the pillar structure 61, the reinforcing structure 16 is used to enhance the connection stability between the pillar structure 6 and the suspended micro-bridge structure 40, especially the beam structure 11, and the reinforcing structure 16 includes a weighted block structure. Specifically, the arrangement of the reinforcing structure 16 can effectively enhance the mechanical stability between the columnar structure 6 and the beam structure 11, thereby improving the structural stability of the infrared detector pixel and the infrared detector comprising the infrared detector pixel.

Illustratively, as shown in fig. 23, when the columnar structure 6 includes a solid columnar structure, a weighted block structure may be provided on a side of the beam structure 11 away from the CMOS measurement circuitry 1 and disposed in contact with the beam structure 11. Specifically, the reinforcing structure 16 is arranged, that is, the weighting block structure is located on one side of the beam structure 11 far away from the CMOS measurement circuit system 1 and is in contact with the beam structure 11, which is equivalent to adding a cover plate at a position of the beam structure 11 corresponding to the columnar structure 6, and the beam structure is pressed by using the self weight of the reinforcing structure 16, so that the mechanical strength between the beam structure 11 and the columnar structure 6 is enhanced, and the structural stability of the infrared detector is improved.

Exemplarily, in combination with fig. 13, 24 and 25, when the pillar structure 6 includes a solid pillar structure, the beam structure 11 may also be provided with a through hole formed at a position corresponding to the pillar structure 6, the through hole exposes at least a portion of the pillar structure 6, the weighted block structure includes a first portion filling the through hole and a second portion located outside the through hole, and an orthographic projection of the second portion covers an orthographic projection of the first portion. Specifically, a hollow-out area is formed at a position of the beam structure 11 corresponding to the columnar structure 6, that is, a through hole is formed, a second part of the weighting block structure outside the through hole and a first part of the weighting block structure inside the through hole are integrally formed, the first part is filled or embedded into the through hole and is in contact with the columnar structure 6, an orthographic projection of the second part covers an orthographic projection of the first part, that is, the area of the second part is larger than that of the first part. In the infrared detector pixel, the reinforcing structure 16 is equivalent to a rivet structure formed by a first part and a second part, the bottom surface of the first part is contacted with the top surface of the columnar structure, the side surface of the first part is also contacted with the side surface of a hollow area formed by the beam structure, and the lower surface of the second part is contacted with the outer surface of the through hole. Therefore, when the self gravity of the reinforcing structure 16 is utilized to press the beam structure 11, the contact area between the reinforcing structure 16 and the columnar structure 6 and the beam structure 11 is increased, the mechanical strength between the beam structure 11 and the columnar structure 6 is further increased, and the structural stability of the infrared detector is improved.

Illustratively, the material that may be provided to form the weighting block structure includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy. Specifically, the reinforcing structure 16 may be a single-layer structure formed by depositing a medium or a metal, or may be a multi-layer structure formed by stacking two, three, or more single-layer structures, where amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nichrome, nickel platinum alloy, and nickel silicon alloy are not corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, and therefore, the reinforcing structure 16 is not affected in a subsequent process of corroding a sacrificial layer by using gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane to release the sacrificial layer, so as to ensure that the mechanical strength at the joint between the beam structure 11 and the columnar structure 6 can be enhanced by the reinforcing structure 16, and prevent the beam structure 11 and the columnar structure 6 from falling off due to loose connection, thereby enhancing the structural stability of the infrared detector. In addition, when the material constituting the reinforcing structure 16 includes silicon oxide, since silicon oxide may be corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, it is preferable that the reinforcing structure 16 is disposed in a closed space surrounded by the first dielectric layer 13 and the second dielectric layer 15.

Optionally, in combination with fig. 2, 17, 18, 20 and 22, the pillar structure 6 may be configured to include at least one layer of hollow pillar structure, and fig. 2, 17, 18, 20 and 22 exemplarily configure that the pillar structure 6 includes one layer of hollow pillar structure, at least one electrode layer 14 is disposed in the hollow pillar structure, and the electrode layer 14 in the hollow pillar structure is electrically connected to the electrode layer 14 in the suspended microbridge structure 40 and the supporting base 42, so as to ensure that the electrical signal generated by the suspended microbridge structure 40 is transmitted to the CMOS measurement circuit system 1. Fig. 2, 17, 18, 20, and 22 exemplarily set up that the electrode layer 14 and the dielectric layers respectively located at two sides of the electrode layer 14 are disposed in the hollow columnar structure, the dielectric layers at two sides achieve effective protection of the electrode layer 14, prevent the electrode layer 14 from being oxidized or corroded, optimize the electrical transmission characteristics of the infrared detector, exemplarily, the dielectric layer located below the electrode layer 14 in the columnar structure 6 may be, for example, the first dielectric layer 13, the dielectric layer located above the electrode layer 14 may be, for example, the second dielectric layer 15, and the dielectric layers at two sides of the electrode layer 14 may also be separately fabricated film layers. In addition, the columnar structure 6 may be provided, and no dielectric layer is arranged above and/or below the electrode layer 14, that is, only a dielectric layer is arranged below the electrode layer 14 in the hollow columnar structure, or only a dielectric layer is arranged above the electrode layer 14, or only the electrode layer 14 is arranged in the hollow columnar structure, and no dielectric layer is wrapped outside the electrode layer 14.

Optionally, with reference to fig. 2, 17 and 20, the infrared detector with a hollow columnar structure may further include a reinforcing structure 16, where the reinforcing structure 16 is disposed corresponding to the position of the columnar structure 6, and the reinforcing structure 16 is used to enhance the connection stability between the columnar structure 6 and the suspended microbridge structure 40 and between the columnar structure 6 and the reflective layer 4, that is, enhance the connection stability between the columnar structure 6 and the supporting base 42. Illustratively, the reinforcing structure 16 may be located on a side of the electrode layer 14 away from the CMOS measurement circuitry 1, and when the electrode layer 14 is not covered by a dielectric layer, the reinforcing structure 16 is located above the electrode layer 14 and is in contact with the electrode layer 14, and at this time, the reinforcing structure 16 may form a hollow structure or a solid structure in the hollow columnar structure. When a dielectric layer is covered on the electrode layer 14, for example, the second dielectric layer 15 is covered on the electrode layer 14 in fig. 2, 17 and 20, the reinforcing structure 16 may be located above the second dielectric layer 15 and disposed in contact with the second dielectric layer 15 as shown in fig. 2, 17 and 20, at this time, the reinforcing structure 16 may form a hollow structure in the hollow columnar structure as shown in fig. 2, and the reinforcing structure 16 may also form a solid structure in the hollow columnar structure, that is, the reinforcing structure 16 may also fill an inner space surrounded by the second dielectric layer 15. Alternatively, as shown in fig. 26, the reinforcing structure 16 may be disposed above the electrode layer 14 and the reinforcing structure 16 may be disposed in contact with the electrode layer 14, that is, the reinforcing structure 16 is located between the electrode layer 14 and the second dielectric layer 15, where the reinforcing structure 16 forms a hollow structure within the hollow columnar structure. Fig. 27 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in the embodiment of the present disclosure. In the infrared detector having the structure shown in fig. 27, the reinforcing structure 16 may also be disposed on a side of the electrode layer 14 adjacent to the CMOS measurement circuit system 1, and when a dielectric layer is disposed below the electrode layer 14, for example, the first dielectric layer 13, the reinforcing structure 16 may be disposed between the electrode layer 14 and the first dielectric layer 13 and the reinforcing structure 16 is disposed in contact with the electrode layer 14.

With reference to fig. 2, 17, 20, 26 and 27, no matter the reinforcing structure 16 is located on one side of the electrode layer 14 away from the CMOS measurement circuit system 1, or the reinforcing structure 16 is located on one side of the electrode layer 14 close to the CMOS measurement circuit system 1, the reinforcing structure 16 covers the connection position of the pillar structure 6 and the suspended microbridge structure 40, which is equivalent to that a negative weight is added at the connection position of the pillar structure 6 and the suspended microbridge structure 40, so that the connection stability between the pillar structure 6 and the suspended microbridge structure 40 is enhanced by the reinforcing structure 16. In addition, the reinforcing structure 16 also covers at least part of the connecting position of the columnar structure 6 and the supporting base 42, which is equivalent to that a negative weight is added at the connecting position of the columnar structure 6 and the supporting base 42, so that the connecting stability between the columnar structure 6 and the supporting base 42 is enhanced by using the reinforcing structure 16, the electrical connection characteristic of the whole infrared detector is optimized, and the infrared detection performance of the infrared detector is optimized. For example, the reinforcing structure 16 described in the above embodiments may be a metal structure or a non-metal structure, which is not specifically limited in this embodiment of the disclosure, and it is sufficient to ensure that the arrangement of the reinforcing structure 16 does not affect the electrical connection relationship in the infrared detector.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit. Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer 4 may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, the radial side length of the columnar structure 6 can be more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 11, namely the width of a single line in the beam structure 11 is less than or equal to 0.3um, and the height of the resonant cavity is less than or equal to 2.5um.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An uncooled tuned infrared detector, comprising:

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the release etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes, the two metal interconnection layers comprise a reflecting layer and an electrode layer, and the two dielectric layers comprise a sacrificial layer and a heat-sensitive dielectric layer; the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system;

the closed release isolation layer is positioned above the metal interconnection layer of the reflection layer, covers the columnar structure, is used for protecting the CMOS measurement circuit system from being corroded when a sacrificial layer is released by a corrosion process, is used for supporting the columnar structure, reduces the contact resistance between the columnar structure and the external environment, prevents the columnar structure from being electrically broken down and reduces the thickness of the sacrificial layer; the CMOS technology corrosion-resistant material adopted by the closed release isolation layer comprises at least one of silicon, germanium, silicon-germanium alloy, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride;

2. The uncooled tuned infrared detector of claim 1, wherein the CMOS infrared sensing structure is fabricated on top of or at the same level as a metal interconnect layer of the CMOS measurement circuitry.

3. The uncooled tuned infrared detector of claim 1, wherein the sacrificial layer is configured to form the CMOS infrared sensing structure as a hollow structure, the material of the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process.

4. The uncooled tuned infrared detector of claim 1, wherein the patterned metal interconnection layer includes a plurality of metal repeating units arranged in an array, each of the metal repeating units including at least one of two diagonally arranged L-shaped patterned structures, a circular structure, a fan-shaped structure, an elliptical structure, a circular structure, an open ring structure, or a polygonal structure.

5. The uncooled tuned infrared detector of claim 1, wherein the patterned metal interconnection layer comprises a plurality of patterned hollow structures arranged in an array, and the patterned hollow structures comprise at least one of circular hollow structures, open ring hollow structures, or polygonal hollow structures.

6. The uncooled tuned infrared detector of claim 4 or 5, wherein a plurality of patterned metal interconnection layers are disposed between the reflective layer and the suspended microbridge structure, and different patterned metal interconnection layers comprise the same or different patterns.

7. The uncooled tuned infrared detector of claim 1, wherein at least one of the patterned metal interconnect layers is on a side of the hermetic release barrier away from the CMOS measurement circuitry and/or at least one of the patterned metal interconnect layers is on a side of the hermetic release barrier adjacent to the CMOS measurement circuitry.

8. The uncooled tuned infrared detector of claim 1, further comprising a reinforcing structure, wherein the reinforcing structure is disposed corresponding to the position of the columnar structure, and the reinforcing structure is configured to enhance the connection stability between the columnar structure and the suspended micro-bridge structure;

9. The uncooled tuned infrared detector of claim 1, wherein the infrared detector is based on 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process;