CN113410362B - LED chip and manufacturing method and application thereof - Google Patents
LED chip and manufacturing method and application thereof Download PDFInfo
- Publication number
- CN113410362B CN113410362B CN202110573499.5A CN202110573499A CN113410362B CN 113410362 B CN113410362 B CN 113410362B CN 202110573499 A CN202110573499 A CN 202110573499A CN 113410362 B CN113410362 B CN 113410362B
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- led chip
- transparent conductive
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 229910006404 SnO 2 Inorganic materials 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims description 44
- 238000000151 deposition Methods 0.000 claims description 42
- 238000000059 patterning Methods 0.000 claims description 32
- 238000001704 evaporation Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000137 annealing Methods 0.000 claims description 25
- 230000008021 deposition Effects 0.000 claims description 24
- 239000012298 atmosphere Substances 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 79
- 239000000243 solution Substances 0.000 description 33
- 229920002120 photoresistant polymer Polymers 0.000 description 28
- 238000005530 etching Methods 0.000 description 23
- 238000001259 photo etching Methods 0.000 description 21
- 238000001312 dry etching Methods 0.000 description 14
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 12
- 238000009616 inductively coupled plasma Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 11
- 239000000969 carrier Substances 0.000 description 8
- 239000012459 cleaning agent Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 239000011259 mixed solution Substances 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 238000005406 washing Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000004506 ultrasonic cleaning Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 108091006149 Electron carriers Proteins 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical class [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910001432 tin ion Inorganic materials 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses an LED chip and a manufacturing method and application thereof, wherein the LED chip comprises a bottom layer, and an N-type semiconductor layer (3) is arranged on the surface of the bottom layer; the N-type semiconductor layer (3) is divided into a first region and a second region; an intermediate layer is arranged on the surface of the first area; the surface of the intermediate layer is provided with a P-type transparent conductive layer; the surfaces of the P-type transparent conducting layer and the second area are provided with a top layer; wherein the P-type transparent conductive layer is made of SnO 2 Composite material and Cu 2 One of the O composite materials; the SnO 2 The composite material comprises SnO 2 With In 2 O 3 The method comprises the steps of carrying out a first treatment on the surface of the The Cu is 2 The O composite material comprises Cu 2 O and NiO. According to the invention, the P-type transparent conducting layer is deposited on the surface of the epitaxial wafer, so that the injection efficiency of a cavity in the P-type transparent conducting layer into the epitaxial wafer is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
Description
Technical Field
The invention relates to the technical field of photoelectrons, in particular to an LED chip and a manufacturing method and application thereof.
Background
A Light-Emitting Diode (LED) is a semiconductor electronic device that converts electrical energy into Light energy. With the vigorous development of the third-generation semiconductor technology, the semiconductor illumination has the advantages of energy conservation, environmental protection, high brightness, long service life and the like, becomes the focus of social development, and also drives the rapid development of the upstream industry and the downstream industry in the whole industry.
III-V compound semiconductor materials are currently the predominant semiconductor materials used to fabricate LED chips, with gallium nitride-based materials and AlGaInP-based materials being the most common. In order to make current uniformly injected into the light-emitting layer, a transparent conductive layer is added on the P-type III-V compound semiconductor material layer.
ITO (Indium Tin Oxides) film has high transmittance and low resistivity, and is widely applied to the field of LEDs and used as a transparent conductive layer in the LED chip process. ITO is an N-type oxide semiconductor, and as shown in FIG. 1, free carriers are mainly derived from high-valence tin ions (Sn 4+ ) For indium (In) 3+ ) Substitution and oxygen vacancy of Sn in the crystal lattice 4+ Substitution of In 3+ Free electrons are provided after the position of (c), while oxygen vacancies also serve as donors to provide free electrons. The ITO transparent conductive layer is deposited on the surface of the P-type semiconductor layer, the ITO transparent conductive layer (N-type oxide semiconductor) and the P-type semiconductor layer are tightly connected together to form a P-N junction, the P-N junction ITO transparent conductive layer (N-type oxide semiconductor) is connected with the positive electrode, the P-type semiconductor is connected with the negative electrode, the space charge area of the P-N junction is widened, the internal electric field is enhanced, the diffusion movement of majority carriers is restrained, the drift of few carriers is enhanced, but the quantity of minority carriers is limited, and only small reverse current can be formed, as shown in figure 2. The P-N junction resistance is large, resulting in a high LED drive voltage.
The general structure of the LED chip is as follows from bottom to top: the semiconductor device comprises a substrate, a buffer layer, an N-type semiconductor layer, a quantum well layer, a P-type semiconductor layer, a transparent conductive layer, a passivation layer, a P electrode and an N electrode. The majority carriers of the P-type semiconductor are holes and the majority carriers of the N-type semiconductor are electrons. The working principle of the LED chip in the related art is shown in fig. 3, and it is known from fig. 3 that the P electrode is connected with the positive electrode of the power supply, the N region is connected with the negative electrode of the power supply, the internal electric field is weakened, and the diffusion of the multiple elements is strengthened, so that a larger diffusion current can be formed. Hole carriers and electron carriers are injected into a P-N junction (quantum well layer) under the action of a forward electric field, and redundant energy is released in a light form when the holes and the electrons are combined, so that electric energy is directly converted into light energy.
Therefore, a new LED chip and a method for manufacturing the same are needed, which has high luminous efficiency and high brightness.
Disclosure of Invention
The first technical problem to be solved by the invention is that: an LED chip has high luminous efficiency and high brightness.
The second technical problem to be solved by the invention is that: the manufacturing method of the LED chip.
The third technical problem to be solved by the invention is that: the LED chip is applied.
In order to solve the first technical problem, the technical scheme provided by the invention is as follows: an LED chip comprises a bottom layer,
the surface of the bottom layer is provided with an N-type semiconductor layer (3);
the N-type semiconductor layer (3) is divided into a first region and a second region;
an intermediate layer is arranged on the surface of the first area;
the surface of the intermediate layer is provided with a P-type transparent conductive layer;
the surfaces of the P-type transparent conductive layer and the second area are provided with a top layer;
the surfaces of the P-type transparent conductive layer and the rest part area of the epitaxial wafer are grown with top layers;
wherein the P-type transparent conductive layer is made of SnO 2 Composite material and Cu 2 At least one of the O composite materials;
the SnO 2 The composite material comprises SnO 2 With In 2 O 3 ；
The Cu is 2 The O composite material comprises Cu 2 O and NiO.
ITO is an N-type semiconductor, is deposited on the surface of a P-type semiconductor layer, and is tightly connected with the P-type semiconductor layer to form a P-N junction, wherein the P-N junction ITO (N-type oxide semiconductor) is connected with a positive electrode, the P-type semiconductor is connected with a negative electrode, a space charge area of the P-N junction is widened, an internal electric field is enhanced, diffusion movement of majority carriers is restrained, minority carrier drift is enhanced, the minority carrier quantity is limited, and only a small reverse current can be formed. The P-N junction resistance is large, resulting in a high LED drive voltage. And a P-type transparent conductive layer is deposited on the surface of the P-type semiconductor layer, so that the problems are solved.
According to some embodiments of the invention, the SnO 2 SnO in composite materials 2 With In 2 O 3 The mass ratio of (2) is 1-19:1.
The doping proportion is used for ensuring that the doped material is a P-type semiconductor. In (In) 2 O 3 Composite material as In 2 O 3 High ratio of SnO 2 With In 2 O 3 The composite material is converted from a P-type semiconductor to an N-type semiconductor.
According to some embodiments of the invention, the SnO 2 SnO in composite materials 2 With In 2 O 3 The mass ratio of (2) is 1.5-4:1.
According to some embodiments of the invention, the Cu 2 Cu in O composite material 2 The mass ratio of O to NiO is 1-5:1.
The doping ratio is to ensure the conductivity of the doped material. NiO and Cu are mixed when the ratio of NiO in the NiO composite material is high 2 The solid solution of O is poor and the conductivity is poor.
According to some embodiments of the invention, the Cu 2 Cu in O composite material 2 The mass ratio of O to NiO is 1-3:1.
According to some embodiments of the invention, the P-type transparent conductive layer has a thickness of 50nm to 350nm.
According to some embodiments of the invention, the bottom layer comprises the following layers in order from bottom to top: a substrate (1) and a buffer layer (2).
According to some embodiments of the invention, the intermediate layer comprises the following layers in order from bottom to top: a quantum well layer (4) and a P-type semiconductor layer (5).
According to some embodiments of the invention, the substrate (1) comprises a sapphire substrate.
According to some embodiments of the invention, the buffer layer (2) comprises a buffer GaN layer.
According to some embodiments of the invention, the N-type semiconductor layer (3) comprises an N-GaN layer.
According to some embodiments of the invention, the quantum well layer (4) comprises an InGaN/GaN multiple quantum well layer.
According to some embodiments of the invention, the P-type semiconductor layer (5) comprises a P-GaN layer.
According to some embodiments of the invention, the top layer consists of the following layers: a passivation layer (7), a P-type electrode (8) and an N-type electrode (9); the passivation layer is etched with a P region electrode groove extending to the P type transparent conductive layer, and the passivation layer is etched with an N region electrode groove extending to the N type semiconductor layer.
According to some embodiments of the invention, the passivation layer (7) comprises SiO 2 And a passivation layer.
According to some embodiments of the invention, the LED chip is divided into a P-region (i) and an N-region (ii).
According to some embodiments of the invention, the P-type electrode is connected to the P-type transparent conductive layer.
According to some embodiments of the invention, the N-type electrode is connected to the N-type semiconductor layer (3).
According to some embodiments of the invention, the P-type electrode is at least one of Cr, ni, al, ti, ag, pt and Au.
According to some embodiments of the invention, the N-type electrode is at least one of Cr, ni, al, ti, ag, pt and Au.
According to the embodiment of the invention, the LED chip has at least the following beneficial effects: according to the invention, the P-type transparent conducting layer (current diffusion layer) is deposited on the surface of the epitaxial wafer, so that the injection efficiency of holes in the P-type transparent conducting layer into the epitaxial wafer is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
In order to solve the second technical problem, the technical scheme provided by the invention is that the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer layer, an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer;
s2, depositing a P-type transparent conductive layer on the surface of the epitaxial wafer;
s3, surface patterning;
s4, depositing a passivation layer;
s5, evaporating the P-type electrode and the N-type electrode;
s6, annealing;
s7, tabletting: and thinning, cutting and checking to obtain the LED chip.
According to some embodiments of the invention, the epitaxial wafer is cleaned.
According to some embodiments of the invention, the cleaning is ultrasonic cleaning.
Removing organic impurities and metal ions on the surface by an ultrasonic cleaning technology.
According to some embodiments of the invention, the ultrasonic cleaning agent is H 2 SO 4 Solution, H 2 O 2 At least one of a solution, a hydrofluoric acid solution, hydrochloric acid and ammonia water.
According to some embodiments of the invention, the ultrasonic cleaning agent is H 2 SO 4 Solution, H 2 O 2 Solution and H 2 A mixed solution of O; preferably, the H 2 SO 4 The mass concentration of the solution is about 98%; preferably, the H 2 O 2 The mass concentration of the solution is 30% -40%; preferably, the H 2 SO 4 Solution, H 2 O 2 Solution and H 2 The volume ratio of O is 2-10:1:1.
According to some embodiments of the invention, the P-type transparent conductive layer is deposited by at least one of electron gun evaporation and magnetron sputtering.
According to some embodiments of the invention, the chamber pressure during the deposition of the P-type transparent conductive layer is 2.0X10 -6 Torr～7.5×10 -6 Torr。
According to some embodiments of the invention, the deposition rate of the P-type transparent conductive layer is 0.02 nm/s-0.12 nm/s during the deposition process.
According to some embodiments of the invention, the deposition temperature of the P-type transparent conductive layer is 200 ℃ to 400 ℃.
According to some embodiments of the invention, the deposition thickness of the P-type transparent conductive layer is 50 nm-350 nm.
The thickness is used for ensuring the conductivity and the light transmittance of the P-type transparent conductive layer; when the thickness is too large, the light transmittance becomes poor; if the thickness is too small, the conductivity becomes poor.
According to some embodiments of the invention, the surface patterning process comprises the following operations:
(1) Patterning the P-type transparent conducting layer: removing the P-type transparent conductive layer in a partial area through photoetching, etching and photoresist removing processes;
(2) And (3) N area patterning: and completely removing the P-GaN layer and the quantum well layer of the N region through photoetching, etching and photoresist removing processes, and then partially removing the N-GaN layer to expose the N-GaN layer of the N region.
According to some embodiments of the invention, the etching in the patterning process of the P-type transparent conductive layer is wet etching.
According to some embodiments of the invention, the etching in the N-region patterning process is dry etching.
According to some embodiments of the invention, the dry etching is at least one of reactive ion etching and inductively coupled plasma etching.
According to some embodiments of the invention, the process of depositing a passivation layer comprises the following operations:
(1) Depositing the passivation layer on the upper surfaces of the P-type transparent conducting layer and the N-GaN layer in the N region by a plasma enhanced chemical vapor deposition method;
(2) And carrying out photoetching, etching and photoresist removing processes on the passivation layer, and removing the passivation layer of the P area electrode groove and the N area electrode groove.
According to some embodiments of the invention, the pressure of the cavity during the evaporation process is 2.0X10 -6 Torr～7.5×10 -6 Torr。
According to some embodiments of the invention, the deposition rate during evaporation is 0.2nm/s to 1.2nm/s.
According to some embodiments of the invention, the electrode patterning process is: and stripping and photoresist removing to leave the P-type electrode of the P-region electrode groove and the N-type electrode of the N-region electrode groove.
According to some embodiments of the invention, a rapid annealing furnace or a high temperature furnace tube is used in the annealing process.
According to some embodiments of the invention, the annealing temperature in step S6 is 400 ℃ to 600 ℃.
According to some embodiments of the invention, the annealing atmosphere in the step S6 is N 2 And (3) air.
According to some embodiments of the invention, the annealing time in the step S6 is 1min to 3min.
The manufacturing method of the LED chip provided by the embodiment of the invention has at least the following beneficial effects: the manufacturing method of the invention is simple and convenient to operate and is suitable for large-scale industrial application.
In order to solve the third technical problem, the technical scheme provided by the invention is as follows: the LED chip is applied to a light-emitting device.
The application according to the embodiment of the invention has at least the following effective effects: the luminous device manufactured by the LED chip has high luminous intensity.
Drawings
FIG. 1 is a diagram showing a crystal structure of ITO in the related art;
FIG. 2 is a schematic diagram showing the problems of the ITO thin film in the related art during operation;
FIG. 3 is a schematic diagram of the operation of an LED chip according to the related art;
fig. 4 is a schematic diagram of a structure of an LED chip according to an embodiment of the present invention.
Description of the reference numerals:
1. a substrate; 2. a buffer layer; 3. an N-type semiconductor layer; 4. a quantum well layer; 5. a P-type semiconductor layer; 6. a P-type transparent conductive layer; 7. a passivation layer; 8. a P-type electrode; 9. an N-type electrode; i and P regions; II, N area.
Detailed Description
In order to describe the technical contents, the achieved objects and effects of the present invention in detail, the following description will be made with reference to the embodiments in conjunction with the accompanying drawings. The test methods used in the examples are conventional methods unless otherwise specified; the materials, reagents and the like used, unless otherwise specified, are those commercially available.
The structure of the LED chip in the embodiment of the present invention is as shown in fig. 4: the LED chip is divided into a P region I and an N region II; the P region I sequentially comprises a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, a quantum well layer 4, a P-type semiconductor layer 5, a P-type transparent conductive layer 6 and a part of passivation layer 7 from bottom to top; the P-type electrode 8 is positioned in a P-region electrode groove of the passivation layer; the N region II comprises a substrate 1, a buffer layer 2, an N-type semiconductor layer 3 and another part of passivation layer 7 from bottom to top in sequence; the N-type electrode 9 is positioned in an N-region electrode groove of the passivation layer.
The first embodiment of the invention is as follows: an LED chip is divided into a P region I and an N region II; wherein the P region I comprises a substrate (sapphire substrate), a buffer layer (buffer GaN layer), an N-type semiconductor layer (N-GaN layer), a quantum well layer (InGaN/GaN multiple quantum well layer), a P-type semiconductor layer (P-GaN layer), a P-type transparent conductive layer and a partial passivation layer (SiO) from bottom to top 2 A passivation layer); the P-type electrode is positioned in the P-region electrode groove of the passivation layer; the N region II comprises a substrate (sapphire substrate), a buffer layer (buffer GaN layer), an N-type semiconductor layer (N-GaN layer) and another part of passivation layer (SiO) 2 A passivation layer); the N-type electrode is positioned in the N-region electrode groove of the passivation layer.
The manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer; the substrate is a sapphire substrate, and the quantum well layer is an InGaN/GaN multiple quantum well layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing a P-type transparent conductive layer on the P-GaN layer: evaporating P-type transparent conductive layer by electron gun, evaporating In source 2 O 3 With SnO 2 The mass ratio of (2) is 3:7, the deposition temperature is 300 ℃, and the chamber pressure is 5 multiplied by 10 -6 Torr, deposition rate was 0.07nm/s, and film thickness was 200nm.
S4, patterning the P-type transparent conducting layer: optimizing pattern photoetching, etching and photoresist removing processes through the P-type transparent conductive layer, and removing the P-type transparent conductive layer at the edges of the N region and the P-GaN layer; the P-type transparent conductive layer is etched by a wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is reactive ion etching.
S6, depositing SiO on the P-type transparent conductive layer and the N-region N-GaN layer by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P region electrode groove and an N region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P region electrode groove exposes the P-type transparent conductive layer, and the N region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 0.7nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Pt/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: annealing in a rapid annealing furnace, wherein the annealing temperature is 500 ℃ and the atmosphere is N 2 The annealing time was 2min.
S11, completing the working procedures to obtain an LED wafer, and thinning, cutting and checking the wafer to manufacture the LED chip.
The second embodiment of the invention is as follows: the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing a P-type transparent conductive layer on the P-GaN layer; wherein, vapor deposition source In 2 O 3 With SnO 2 The mass ratio of (2) is 1:4, the deposition temperature is 350 ℃, and the chamber pressure is 7.5X10 -6 Torr, deposition rate was 0.12nm/s, and film thickness was 100nm.
S4, patterning the P-type transparent conducting layer: optimizing pattern photoetching, etching and photoresist removing processes through the P-type transparent conductive layer, and removing the P-type transparent conductive layer at the edges of the N region and the P-GaN layer; the P-type transparent conductive layer is etched by a wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the P-type transparent conductive layer and the N-region N-GaN layer by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P region electrode groove and an N region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P region electrode groove exposes the P-type transparent conductive layer, and the N region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 1nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Ni/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: at a temperature of 400 ℃, N 2 And (5) atmosphere and annealing for 3min.
S11, finishing the working procedures to obtain the LED wafer, and thinning, cutting and checking the wafer to obtain the P-type transparent conducting layer modified LED chip.
The third embodiment of the invention is as follows: the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing a P-type transparent conductive layer on the P-GaN layer; wherein, vapor deposition sources NiO and Cu 2 O mass ratio of 3:7, deposition temperature of 400 ℃ and chamber pressure of 2.0X10 -6 Torr, deposition rate was 0.02nm/s, and film thickness was 300nm.
S4, patterning the P-type transparent conducting layer: optimizing pattern photoetching, etching and photoresist removing processes through the P-type transparent conductive layer, and removing the P-type transparent conductive layer at the edges of the N region and the P-GaN layer; the P-type transparent conductive layer is etched by a wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the P-type transparent conductive layer and the N-region N-GaN layer by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P region electrode groove and an N region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P region electrode groove exposes the P-type transparent conductive layer, and the N region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 1nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Al/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: at a temperature of 400 ℃, N 2 And (5) atmosphere and annealing for 3min.
S11, finishing the working procedures to obtain the LED wafer, and thinning, cutting and checking the wafer to obtain the P-type transparent conducting layer modified LED chip.
The fourth embodiment of the invention is as follows: the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing a P-type transparent conductive layer on the P-GaN layer; wherein, vapor deposition sources NiO and Cu 2 O mass ratio of 1:3, deposition temperature of 300 ℃ and chamber pressure of 2.0X10 -6 Torr, deposition rate was 0.12nm/s, and film thickness was 100nm.
S4, patterning the P-type transparent conducting layer: optimizing pattern photoetching, etching and photoresist removing processes through the P-type transparent conductive layer, and removing the P-type transparent conductive layer at the edges of the N region and the P-GaN layer; the P-type transparent conductive layer is etched by a wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the P-type transparent conductive layer and the N-region N-GaN layer by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P region electrode groove and an N region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P region electrode groove exposes the P-type transparent conductive layer, and the N region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 1nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Ti/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: temperature 600 ℃, N 2 And (5) atmosphere and annealing for 1min.
S11, finishing the working procedures to obtain the LED wafer, and thinning, cutting and checking the wafer to obtain the P-type transparent conducting layer modified LED chip.
The first comparative example of the present invention is: the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer from bottom to top, the substrate is a sapphire substrate, and the quantum well layer is an InGaN/GaN multiple quantum well layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing an ITO transparent conductive layer on the P-GaN layer: evaporating by adopting an electron gun; wherein, vapor deposition source In 2 O 3 With SnO 2 The mass ratio of (2) is 95:5, the deposition temperature is 300 ℃, and the chamber pressure is 5 multiplied by 10 -6 Torr, deposition rate was 0.07nm/s, and film thickness was 200nm.
S4, patterning the ITO transparent conducting layer: optimizing pattern photoetching, etching and photoresist removing processes through the ITO transparent conductive layer, and removing the ITO transparent conductive layer at the edges of the N region and the P-GaN layer; the ITO transparent conductive layer is etched by a wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the ITO transparent conductive layer and the N-GaN layer by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P-region electrode groove and an N-region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P-region electrode groove exposes the ITO transparent conductive layer, and the N-region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 0.7nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Pt/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: at 500 ℃, N 2 And (5) atmosphere and annealing for 2min.
S11, completing the working procedures to obtain an LED wafer, and thinning, cutting and checking the wafer to manufacture the LED chip.
The second comparative example of the present invention is: the manufacturing method of the LED chip comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises a substrate, a buffer GaN layer, an N-GaN layer, a quantum well layer and a P-GaN layer from bottom to top, the substrate is a sapphire substrate, and the quantum well layer is an InGaN/GaN multiple quantum well layer.
S2, cleaning an epitaxial wafer: washing the epitaxial wafer by ultrasonic waves; wherein the method comprises the steps ofThe cleaning agent is H 2 SO 4 Solution (mass fraction 98%), H 2 O 2 Solution (mass fraction 35%) and H 2 Mixed solution of O (sulfuric acid solution, H 2 O 2 The volume ratio of the solution to the water is 6:1:1).
S3, depositing a transparent conductive layer on the P-GaN layer: evaporating by adopting an electron gun; wherein, vapor deposition sources NiO and Cu 2 O mass ratio of 2:1, deposition temperature of 300 ℃ and chamber pressure of 5.0X10 -6 Torr, deposition rate was 0.1nm/s, and film thickness was 200nm.
S4, patterning the transparent conducting layer: the transparent conductive layer at the edges of the N region and the P-GaN layer is removed through the optimized pattern photoetching, etching and photoresist removing processes of the transparent conductive layer; wherein, the transparent conductive layer is etched by wet method.
S5, patterning the N region: removing the P-GaN layer, the quantum well layer and the upper part of the N-GaN layer of the N region through ICP optimized pattern photoetching, dry etching and photoresist removal, and exposing the N-GaN layer of the N region; wherein the dry etching is inductively coupled plasma etching.
S6, depositing SiO on the transparent conductive layer and the N-GaN layer in the N area by a plasma enhanced chemical vapor deposition method 2 And a passivation layer.
S7, patterning the passivation layer: and manufacturing a P-region electrode groove and an N-region electrode groove through optimized pattern photoetching, etching and photoresist removal of the passivation layer, wherein the P-region electrode groove exposes the transparent conductive layer, and the N-region electrode groove exposes the N-GaN layer.
S8, evaporating the P-type electrode and the N-type electrode layer: evaporating metal electrodes by electron gun, evaporating metal layers of each electrode sequentially, and keeping the cavity pressure at 5×10 -6 Torr, deposition rate is 0.7nm/s; wherein, the P-type electrode and the N-type electrode are Cr/Pt/Au (the thickness of each layer is 10nm/25nm/1000nm respectively).
S9, electrode patterning: and stripping and photoresist stripping to leave a P-type electrode and an N-type electrode.
S10, annealing: at 500 ℃, N 2 And (5) atmosphere and annealing for 2min.
S11, completing the working procedures to obtain an LED wafer, and thinning, cutting and checking the wafer to manufacture the LED chip.
LED chips were fabricated according to the methods of examples one to four and comparative example on the same machine, and samples were ground and cut into 6mil by 8mil chip particles under the same conditions, and then the examples and comparative examples were each die-picked in the same location and packaged into LEDs under the same packaging process. The same drive current was used to test the opto-electronic properties of the samples using an electrical property analyzer and a spectroscopic analyzer. The results of the photoelectric performance test are shown in Table 1.
Table 1 comparative table of the photoelectric parameters of examples and comparative examples of the present invention
| Detecting items | Chip size (mil) 2 ) | Dominant wavelength (nm) | Forward voltage (V) | Light intensity (mcd) |
| Example 1 | 6*8 | 456.2 | 2.50 | 64.7 |
| Example two | 6*8 | 456.2 | 2.49 | 64.6 |
| |
6*8 | 456.2 | 2.49 | 64.6 |
| |
6*8 | 456.2 | 2.49 | 64.6 |
| Comparative example one | 6*8 | 456.2 | 2.66 | 59.4 |
| Comparative example two | 6*8 | 456.2 | 2.78 | 57.8 |
As can be seen from the comparison of the data in Table 1, the forward voltage of the first embodiment of the present invention was reduced from 2.66V to 2.78V to 2.50V, and the light intensity was increased from 59.4mcd to 57.8mcd to 64.7mcd, compared with the first to second embodiments of the present invention. In the second example, compared with the first and second comparative examples, the forward voltage was reduced from 2.66V to 2.78V to 2.49V, and the light intensity was increased from 59.4mcd to 57.8mcd to 64.6mcd. Compared with the first to second comparative examples, the forward voltage is reduced from 2.66V to 2.78V to 2.49V, and the light intensity is improved from 59.4mcd to 57.8mcd to 64.6mcd. In the fourth example, compared with the first to second comparative examples, the forward voltage was reduced from 2.66V to 2.78V to 2.49V, and the light intensity was increased from 59.4mcd to 57.8mcd to 64.6mcd. This illustrates that the LED chips fabricated in the first to fourth embodiments have a reduced forward voltage and significantly improved light intensity.
In summary, according to the manufacturing method of the LED chip provided by the invention, the P-type transparent conductive layer is used for replacing the ITO transparent conductive layer, so that the hole injection efficiency of P-GaN is improved, the forward voltage of the LED chip is reduced, and the brightness of the LED chip is improved.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent changes made by the specification and drawings of the present invention, or direct or indirect application in the relevant art, are included in the scope of the present invention.
Claims (10)
1. An LED chip, characterized in that: comprises a bottom layer and a bottom layer,
the surface of the bottom layer is provided with an N-type semiconductor layer (3);
the N-type semiconductor layer (3) is divided into a first region and a second region;
the surface of the first area is provided with an intermediate layer;
the surface of the intermediate layer is provided with a P-type transparent conductive layer;
the surfaces of the P-type transparent conductive layer and the second area are provided with a top layer;
wherein the P-type transparent conductive layer is made of SnO 2 Composite material and Cu 2 At least one of the O composite materials;
the SnO 2 The composite material comprises SnO 2 With In 2 O 3 ；
The Cu is 2 The O composite material comprises Cu 2 O and NiO;
the SnO 2 SnO in composite materials 2 With In 2 O 3 The mass ratio of (2) is 1-19:1.
2. An LED chip as recited in claim 1, wherein: the SnO 2 SnO in composite materials 2 With In 2 O 3 The mass ratio of (2) is 1.5-4:1.
3. A kind of according to claim 1LED chip, its characterized in that: the Cu is 2 Cu in O composite material 2 The mass ratio of O to NiO is 1-5:1.
4. An LED chip as recited in claim 1, wherein: the thickness of the P-type transparent conductive layer is 50 nm-350 nm.
5. An LED chip as recited in claim 1, wherein: the bottom layer sequentially comprises the following layers from bottom to top: a substrate (1) and a buffer layer (2).
6. An LED chip as recited in claim 5, wherein: the top layer is composed of the following layers: a passivation layer (7), a P-type electrode (8) and an N-type electrode (9); the passivation layer is etched with a P region electrode groove extending to the P type transparent conductive layer, and the passivation layer is etched with an N region electrode groove extending to the N type semiconductor layer.
7. A method of making the LED chip of claim 6, wherein: the method comprises the following steps:
s1, taking an epitaxial wafer, wherein the epitaxial wafer sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, a buffer layer, an N-type semiconductor layer, a quantum well layer and a P-type semiconductor layer;
s2, depositing a P-type transparent conductive layer on the surface of the epitaxial wafer;
s3, surface patterning;
s4, depositing a passivation layer;
s5, evaporating the P-type electrode and the N-type electrode;
s6, annealing;
s7, tabletting: and thinning, cutting and checking to obtain the LED chip.
8. The method according to claim 7, wherein: the surface deposition temperature in step S2 is 200-400 ℃.
9. The method according to claim 7The method is characterized in that: the annealing temperature in the step S6 is 400-600 ℃; the atmosphere of the annealing in step S6 includes N 2 The method comprises the steps of carrying out a first treatment on the surface of the And the annealing time in the step S6 is 1-3 min.
10. Use of the LED chip according to any one of claims 1 to 6 in a light emitting device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110573499.5A CN113410362B (en) | 2021-05-25 | 2021-05-25 | LED chip and manufacturing method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110573499.5A CN113410362B (en) | 2021-05-25 | 2021-05-25 | LED chip and manufacturing method and application thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113410362A CN113410362A (en) | 2021-09-17 |
| CN113410362B true CN113410362B (en) | 2023-05-09 |
Family
ID=77674928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110573499.5A Active CN113410362B (en) | 2021-05-25 | 2021-05-25 | LED chip and manufacturing method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113410362B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078064A (en) * | 1998-05-04 | 2000-06-20 | Epistar Co. | Indium gallium nitride light emitting diode |
| JP2007329468A (en) * | 2006-05-10 | 2007-12-20 | Kumamoto Univ | Light-emitting element, and manufacturing method thereof |
| CN103730558B (en) * | 2013-12-31 | 2017-07-14 | 中国科学院半导体研究所 | Light emitting diode using composite transparent conductive layer and preparation method thereof |
| CN105140368B (en) * | 2015-08-05 | 2017-11-17 | 湘能华磊光电股份有限公司 | A kind of high performance lED chip and preparation method thereof |
| CN107731969A (en) * | 2017-10-18 | 2018-02-23 | 湘能华磊光电股份有限公司 | The preparation method of LED chip |
| CN112750933B (en) * | 2021-01-26 | 2022-08-26 | 长沙壹纳光电材料有限公司 | LED chip and manufacturing method thereof |
| CN112750929A (en) * | 2021-01-26 | 2021-05-04 | 长沙壹纳光电材料有限公司 | P-GAN layer modified LED chip and manufacturing method thereof |
-
2021
- 2021-05-25 CN CN202110573499.5A patent/CN113410362B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113410362A (en) | 2021-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101969089B (en) | Method for manufacturing gallium nitride-based light-emitting diode with current barrier layer | |
| CN101789478B (en) | Light-emitting diode chip and manufacturing method thereof | |
| CN102157640A (en) | Method for manufacturing gallium nitride (GaN)-based light-emitting diode (LED) chip with p-GaN layer subjected to surface roughening | |
| CN103219352B (en) | LED combination chip of array architecture and preparation method thereof | |
| CN105140368A (en) | High-performance light-emitting diode (LED) chip and fabrication method thereof | |
| CN105720155B (en) | A kind of Light-emitting diode LED and preparation method thereof | |
| CN105514230A (en) | GaN-base LED vertical chip structure and manufacture method thereof | |
| CN102651438B (en) | Substrate, preparation method thereof and chip with substrate | |
| CN107123705B (en) | A kind of preparation method of light emitting diode | |
| CN103647010B (en) | A kind of preparation method of high-power LED chip | |
| CN113410362B (en) | LED chip and manufacturing method and application thereof | |
| US7541205B2 (en) | Fabrication method of transparent electrode on visible light-emitting diode | |
| CN105742449B (en) | The electrode preparation method of light emitting diode | |
| KR101239852B1 (en) | GaN compound semiconductor light emitting element | |
| US20130075779A1 (en) | Light emitting diode with multiple transparent conductive layers and method for manufacturing the same | |
| CN112750933B (en) | LED chip and manufacturing method thereof | |
| CN105720150A (en) | Zinc oxide-base transparent electrode structure GaN-base LED chip and manufacturing method thereof | |
| CN112750929A (en) | P-GAN layer modified LED chip and manufacturing method thereof | |
| CN214336736U (en) | LED chip structure of double-layer ITO film | |
| KR100873187B1 (en) | Manufacturing method of light emitting diode | |
| KR20090001231A (en) | Vertical light emitting diode, method for manufacturing the same and light emitting diode having the same | |
| KR20060112064A (en) | Light emitting device | |
| KR101202731B1 (en) | Method for manufacturing vertical light emitting diode | |
| CN100442560C (en) | Method for producing light-emitting diodes | |
| CN108336191B (en) | A kind of light-emitting diode chip for backlight unit and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |