CN113410200B - Chip packaging frame and chip packaging structure - Google Patents
Chip packaging frame and chip packaging structure Download PDFInfo
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- CN113410200B CN113410200B CN202010182721.4A CN202010182721A CN113410200B CN 113410200 B CN113410200 B CN 113410200B CN 202010182721 A CN202010182721 A CN 202010182721A CN 113410200 B CN113410200 B CN 113410200B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 27
- 238000010586 diagram Methods 0.000 description 22
- 229910002601 GaN Inorganic materials 0.000 description 8
- 229910002704 AlGaN Inorganic materials 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip packaging frame and a chip packaging structure. Wherein the chip package frame comprises: packaging a base; the substrate is arranged on the packaging base and is divided into at least one chip area, and the chip area comprises a first conductive layer and an insulating layer which are stacked; the at least one second conductive layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and is arranged in one-to-one correspondence with the chip area, wherein the at least one second conductive layer comprises a first sub-conductive layer, a first conductive through hole is arranged on the insulating layer, and the first sub-conductive layer is electrically connected with the first conductive layer through the first conductive through hole; the at least one electrode pin is positioned on at least one side of the package base and comprises a first electrode pin, and the first electrode pin is electrically connected with the first conductive layer. The invention solves the problems that the prior packaging structure has larger parasitic parameters and affects the performance and stability of the packaged chip, and reduces the parasitic parameters of the packaging structure.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip packaging, in particular to a chip packaging frame and a chip packaging structure.
Background
In the aspect of semiconductor electronic devices, an AlGaN/GaN high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a wide-bandgap semiconductor device with high-concentration Two-dimensional electron gas (Two-Dimensional Electron Gas,2 DEG), has the characteristics of high output power density, high temperature resistance, high stability and high breakdown voltage, and has great application potential in the field of power electronic devices.
AlGaN/GaN high electron mobility transistors generally operate under high frequency and high power conditions, and have higher requirements on parasitic parameters and heat dissipation capability of the package structure. The packaging forms commonly used at present are mainly single-side pin packaging and multi-side pin packaging. Due to the pin layout and the structure of the chip package frame, the single-sided pin package has high heat dissipation capability but large parasitic parameters, while the multi-sided pin package has lower parasitic parameters but poor heat dissipation capability. Although the multi-side pin package has lower parasitic parameters than the single-side pin package, the package structure still has larger parasitic parameters, which affect the performance and stability of the packaged chip. Therefore, how to further reduce the parasitic parameters of the package structure becomes one of the research directions of the chip package structure.
Disclosure of Invention
In view of the above, the present invention provides a chip package frame and a chip package structure for reducing parasitic parameters of the package structure.
In order to achieve the above purpose, the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a chip package frame, including:
packaging a base;
the substrate is arranged on the packaging base and is divided into at least one chip area, and the chip area comprises a first conductive layer and an insulating layer which are stacked;
the at least one second conductive layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and corresponds to the chip area one by one, wherein the at least one second conductive layer comprises a first sub-conductive layer, a first conductive through hole is arranged on the insulating layer, and the first sub-conductive layer is electrically connected with the first conductive layer through the first conductive through hole;
and the at least one electrode pin is positioned on at least one side of the packaging base and comprises a first electrode pin, and the first electrode pin is electrically connected with the first conductive layer.
Optionally, the at least one second conductive layer further comprises a second sub-conductive layer, the second sub-conductive layer being insulated from the first sub-conductive layer.
Optionally, the chip package frame further includes a third conductive layer, where the third conductive layer is disposed on the upper surface of the insulating layer and is located outside the chip area, and a second conductive through hole is disposed on the insulating layer, and the third conductive layer is electrically connected with the first conductive layer through the second conductive through hole.
Optionally, the chip package frame further includes a fourth conductive layer, which is located outside the chip region and insulated from the first sub-conductive layer.
On the other hand, the embodiment of the invention also provides a chip packaging structure, which comprises at least one chip and the chip packaging frame provided by the embodiment of the invention;
the at least one chip is attached to the chip packaging frame, and chip electrodes of the at least one chip are respectively and electrically connected with corresponding electrode pins;
the at least one chip comprises a first chip, the first chip is attached to the first sub-conductive layer, and at least one surface electrode of the first chip is electrically connected with the first sub-conductive layer.
Optionally, the at least one surface electrode includes a first surface electrode disposed on a lower surface of the first chip, and the first surface electrode is in electrical contact with the first sub-conductive layer;
optionally, the area of the first sub-conductive layer is larger than the area occupied by the first chip, the at least one surface electrode includes a second surface electrode disposed on the upper surface of the first chip, and the second surface electrode is electrically connected with a portion of the first sub-conductive layer located outside the area where the first chip is located through a first bonding wire.
Optionally, the at least one second conductive layer further comprises a second sub-conductive layer, the second sub-conductive layer being insulated from the first sub-conductive layer;
the at least one chip further comprises a second chip, the second chip is mounted on the second sub-conducting layer, the second chip comprises a third surface electrode arranged on the lower surface of the second chip, and the third surface electrode is in electrical contact with the second sub-conducting layer.
Optionally, the chip packaging frame further includes a third conductive layer, where the third conductive layer is disposed on the upper surface of the insulating layer and is located outside the chip area, and a second conductive through hole is disposed on the insulating layer, and the third conductive layer is electrically connected with the first conductive layer through the second conductive through hole;
the second chip further comprises a fourth surface electrode arranged on the upper surface of the second chip, and the fourth surface electrode is electrically connected with the third conductive layer through a second bonding wire.
Optionally, the chip package frame further includes a fourth conductive layer, which is located outside the chip region and insulated from the first sub-conductive layer;
the fourth conductive layer comprises a third sub-conductive layer, the at least one electrode pin further comprises a second electrode pin, the at least one surface electrode further comprises a fifth surface electrode arranged on the upper surface of the first chip, the fifth surface electrode is electrically connected with the third sub-conductive layer through a third bonding wire, and the third sub-conductive layer is electrically connected with the second electrode pin through a fourth bonding wire; and/or the fourth conductive layer comprises a fourth sub-conductive layer, the at least one electrode pin further comprises a third electrode pin, the second chip further comprises a sixth surface electrode arranged on the upper surface of the second chip, the sixth surface electrode is electrically connected with the fourth sub-conductive layer through a fifth bonding wire, and the fourth sub-conductive layer is electrically connected with the third electrode pin through a sixth bonding wire.
Optionally, a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer.
Optionally, the first chip and the second chip form a cascode.
The beneficial effects of the invention are as follows: according to the chip packaging frame and the chip packaging structure, the substrate is arranged on the packaging base and comprises the first conductive layer and the insulating layer which are stacked, the first conductive layer is electrically connected with the first electrode pin of the packaging frame, the at least one second conductive layer is arranged on the upper surface of the insulating layer and is positioned in the chip area of the substrate, meanwhile, the first sub-conductive layer in the second conductive layer is electrically connected with the first conductive layer through the first conductive through hole on the insulating layer, and therefore at least one surface electrode of a chip arranged on the first sub-conductive layer is electrically connected with the first sub-conductive layer, the surface electrode can be electrically connected with the first electrode pin, the surface electrode is prevented from being directly electrically connected with the first electrode pin through the bonding wire, the length of the bonding wire in the chip packaging structure can be shortened, parasitic parameters led by the bonding wire are reduced, and parasitic parameters of the chip packaging structure are reduced.
Drawings
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic structural diagram of a chip package frame according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along AA' of FIG. 1;
fig. 3 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of the structure along BB' in FIG. 3;
FIG. 5 is a schematic diagram of another chip package frame according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of the structure along CC' of FIG. 5;
fig. 7 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view taken along DD' in FIG. 7;
FIG. 9 is a schematic diagram of another chip package frame according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of the structure along EE' in FIG. 9;
FIG. 11 is a schematic diagram of another chip package structure according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view taken along FF' of FIG. 11;
FIG. 13 is a schematic view of another chip package frame according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
FIG. 15 is a schematic diagram of another chip package structure according to an embodiment of the present invention;
fig. 16 is an equivalent circuit diagram of a chip package structure according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of another chip package structure according to an embodiment of the present invention;
FIG. 18 is an equivalent circuit diagram of another chip package structure provided by an embodiment of the present invention;
fig. 19 is an equivalent circuit diagram of another chip package structure according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The chip packaging frame provided by the embodiment of the invention can be used for single chip packaging or multi-chip packaging, wherein the multi-chip packaging can comprise cascade chip packaging, and is suitable for reducing parasitic parameters of a packaging structure. Fig. 1 is a schematic structural diagram of a chip package frame according to an embodiment of the present invention; fig. 2 is a schematic cross-sectional view along AA' in fig. 1. As shown in fig. 1 and 2, the chip package frame provided in this embodiment includes:
a package base 1;
a substrate 2 disposed on the package base 1 and divided into at least one chip area including a first conductive layer 21 and an insulating layer 22 stacked;
the at least one second conductive layer 5 is arranged on the upper surface of the insulating layer 22, is positioned in the chip area and is arranged in one-to-one correspondence with the chip area, wherein the at least one second conductive layer 5 comprises a first sub-conductive layer 51, a first conductive through hole 23 is arranged on the insulating layer 22, and the first sub-conductive layer 51 is electrically connected with the first conductive layer 21 through the first conductive through hole 23;
at least one electrode pin 4 is located on at least one side of the package base 1, and includes a first electrode pin 41, and the first electrode pin 41 is electrically connected with the first conductive layer 21.
In this embodiment, the package base 1 mainly plays a role of bearing chips and other components to be packaged, and may be a conductive base, such as a metal base, and the specific material may be copper or aluminum, or may be other metals or alloys with better heat conductivity. This embodiment is not limited thereto, and may be applied as the case may be. The first conductive via 23 of the substrate 2 may be filled with a conductive material such that the second conductive layer 5 is electrically connected to the first conductive layer 21 through the first conductive via 23.
In this embodiment, the substrate 2 may play a role in transferring heat, the substrate 2 may be made of a high heat conduction insulating material, and specifically, the substrate 2 may be made of polyethylene or other polymer materials doped with a heat conduction filler, so that heat generated by the chip 3 can be guaranteed to be quickly transferred to the package base 1. Further, the breakdown voltage of the substrate 2 may be greater than 50V, and preferably, the breakdown voltage is 100V. On the basis of ensuring that the breakdown voltage of the substrate 2 meets the conditions, the thickness of the substrate 2 is as thin as possible, preferably, the thickness of the substrate 2 is smaller than 0.5 micrometers, so that heat generated by the chip 3 can be further ensured to be transferred to the package base 1 as much as possible, and good heat dissipation of the chip 3 is realized.
The chip that can be packaged by the chip packaging frame provided in this embodiment may include multiple types of chips, which may be chips such as diodes or triodes, and the chip packaging structure may only package one or more chips of the same type, or may also package chips of other types at the same time. The chip areas can be divided according to the actual layout of the chips to be packaged, each chip area is provided with a second conductive layer 5, and the chips to be packaged are attached to the second conductive layers 5. At least one electrode pin 4 is used for leading out the electrode of the chip, and realizes the electrical connection with an external circuit.
According to the chip package frame provided by the embodiment, the substrate 2 is arranged on the package base 1, the substrate 2 comprises the stacked first conductive layer 21 and the insulating layer 22, the first conductive layer 21 is electrically connected with at least one first electrode pin 41 of the chip package frame, at least one second conductive layer 5 is arranged on the upper surface of the insulating layer 22 and is positioned in the chip area of the substrate 2, meanwhile, the first sub-conductive layer 51 in the second conductive layer 5 is electrically connected with the first conductive layer 21 through the first conductive through hole 23 on the insulating layer 22, and therefore at least one surface electrode of a chip arranged on the first sub-conductive layer 51 can be electrically connected with the first sub-conductive layer 51, and the surface electrode can be electrically connected with any one first electrode pin 41 of the at least one electrode pin 4, so that the surface electrode is prevented from being directly electrically connected with the first electrode pin 41 through a bonding wire, and the length of the bonding wire in the chip package structure can be shortened, parasitic parameters introduced by the bonding wire are reduced, and parasitic parameters of the chip package structure are reduced.
Alternatively, the first conductive layer 21 of the present invention may be electrically connected to at least one electrode lead 4 of the chip package frame by providing the first electrode lead 41 in direct electrical contact with the first conductive layer 21, or may be electrically connected to the package base 1 by the first conductive layer 21 and then electrically connecting the package base 1 to the first electrode lead 41 of the chip package frame.
Correspondingly, the embodiment of the invention also provides a chip packaging structure, and fig. 3 is a schematic structural diagram of the chip packaging structure provided by the embodiment of the invention; fig. 4 is a schematic sectional view of the structure along BB' in fig. 3. As shown in fig. 3 and 4, the chip package structure provided in this embodiment includes: at least one chip 3 and the chip package frame provided by the above embodiments;
at least one chip 3 is attached to the chip packaging frame, and chip electrodes of the at least one chip 3 are respectively and electrically connected with corresponding electrode pins 4;
the at least one chip 3 includes a first chip 31, the first chip 31 is mounted on the first sub-conductive layer 51, and at least one surface electrode of the first chip 31 is electrically connected to the first sub-conductive layer 51.
In this embodiment, referring to fig. 4, the at least one surface electrode may include a first surface electrode 310 disposed on the lower surface of the first chip 31, where the first surface electrode 310 is in electrical contact with the first sub-conductive layer 51, and in this embodiment, the first surface electrode 310 is preferably in direct contact with the first sub-conductive layer 51. Since the first sub-conductive layer 51 is electrically connected with the first conductive layer 21 through the first conductive via 23, the first conductive layer 21 is electrically connected with the first electrode pin 41, and therefore, by providing the first surface electrode 310 to be in electrical contact with the first sub-conductive layer 51, the electrical connection between the first surface electrode 310 and the first electrode pin 41 can be realized without providing a bonding wire for connecting the first surface electrode 310 and the first electrode pin 41, and the use of the bonding wire is avoided, thereby reducing parasitic parameters introduced by the bonding wire, and improving the performance and stability of the packaged chip. It should be understood that, in the present invention, at least one electrode pin 4 includes at least a first electrode pin 41, and the position of the first electrode pin 41 is arbitrary, and the drawing of the present invention is only an example, and is not limited, so long as the first electrode pin 41 is electrically connected to the first sub-conductive layer 51.
Alternatively, referring to fig. 3 and 4, the area of the first sub-conductive layer 51 is larger than the area occupied by the first chip 31, and at least one surface electrode includes a second surface electrode 311 disposed on the upper surface of the first chip 31, the second surface electrode 311 passing through the first bonding line L 1 Is electrically connected to a portion of the first sub-conductive layer 51 located outside the region where the first chip 31 is located. Thereby, the second surface electrode 311 passes through the first bonding line L 1 Is electrically connected with the first sub-conductive layer 51 of the chip region where the first chip 31 is located, so that the second surface electrode 311 is electrically connected with at least one electrode pin 4, and the distance between the second surface electrode 311 and the first sub-conductive layer 51 is smaller than the distance between the second surface electrode 311 and the first electrode pin 41, thus the first bonding line L 1 The length of the bonding wire L0 (see fig. 3) directly connecting the first surface electrode 310 and the first electrode lead 41 is smaller, and thus the length of the bonding wire for electrically connecting the second surface electrode 311 and the first electrode lead 41 is shortened, thereby reducing parasitic parameters introduced by the bonding wire, and thus reducing parasitic parameters of the chip package structure.
Considering the overall layout of each chip in the chip package structure, such as the insulation required between some chips or between chip electrodes of some chips, in another embodiment of the present invention, fig. 5 is a schematic structural diagram of another chip package frame provided in an embodiment of the present invention; fig. 6 is a schematic sectional structure along CC' in fig. 5. As shown in fig. 5 and 6, the at least one second conductive layer further includes a second sub-conductive layer 52, the second sub-conductive layer 52 being insulated from the first sub-conductive layer 51. Illustratively, the first sub-conductive layer 51 and the second sub-conductive layer 52 are located in different chip areas, the first sub-conductive layer 51 and the second sub-conductive layer 52 are disposed at intervals, the insulating layer 22 under the first sub-conductive layer 51 is provided with the first conductive via 23, the first sub-conductive layer 51 is electrically connected with the first conductive layer 21 through the first conductive via 23, and meanwhile, the insulating layer under the second sub-conductive layer 52 is not provided with the conductive via, at this time, the second sub-conductive layer 52 is insulated from the first conductive layer 21, thereby realizing insulation between the second sub-conductive layer 52 and the first sub-conductive layer 51.
Correspondingly, the embodiment also provides a chip packaging structure, and fig. 7 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the invention; fig. 8 is a schematic cross-sectional view of the DD' of fig. 7. As shown in fig. 7 and 8, according to the chip package structure provided in the above embodiment, at least one chip further includes a second chip 32, the second chip 32 is attached to the second sub-conductive layer 52, the second chip 32 includes a third surface electrode 320 disposed on a lower surface of the second chip 32, and the third surface electrode 320 is electrically contacted with the second sub-conductive layer 52.
The chip package structure provided in this embodiment is based on the chip package frame shown in fig. 5 and 6, and performs overall layout on the first chip 31 and the second chip 32, so that the first surface electrode 310 of the first chip 31 and the third surface electrode 320 of the second chip 32 can be electrically insulated. Meanwhile, when the third surface electrode 320 does not need to be electrically connected with the chip electrodes of other chips, the area of the second sub-conductive layer 52 can be the same as the area occupied by the second chip 32, and the third surface electrode 320 can serve as a buffer layer, so that the third surface electrode 320 can be conveniently attached; when the third surface electrode 320 needs to be electrically connected to the chip electrodes of the other chips, the area of the second sub-conductive layer 52 may be larger than the area occupied by the second chip 32, and the chip electrodes of the other chips may be electrically connected to the portion of the second sub-conductive layer 52 located outside the second chip 32, so as to electrically connect the chip electrodes of the other chips to the third surface electrode 320.
Optionally, based on the foregoing embodiment, in yet another embodiment of the present invention, fig. 9 is a schematic structural diagram of another chip package frame provided in the embodiment of the present invention; fig. 10 is a schematic sectional view of the structure along EE' in fig. 9. As shown in fig. 9 and 10, the chip package frame further includes a third conductive layer 6, where the third conductive layer 6 is disposed on the upper surface of the insulating layer 22, and is located outside the chip area, and a second conductive via 24 is disposed on the insulating layer 22, and the third conductive layer 6 is electrically connected to the first conductive layer 21 through the second conductive via 24.
In addition to the surface electrode of the chip (e.g., the first chip) located in the first sub-conductive layer 51 being electrically connected to the first electrode pin, the upper surface electrode of the chip in the other second conductive layer may need to be electrically connected to the first electrode pin, but the lower surface electrode of the chip (e.g., the third surface electrode of the second chip) needs to be insulated from the first surface electrode of the first chip, so that a layer of the third conductive layer 6 needs to be disposed outside the chip area and near the chip, and the third conductive layer 6 is electrically connected to the first conductive layer 21 through the second conductive via 24 on the insulating layer 22, so that the upper surface electrode of the chip is electrically connected to the third conductive layer 6. Therefore, the length of the bonding wire for realizing the electric connection between the upper surface electrode of the chip and the first electrode pin is shortened, parasitic parameters introduced by the bonding wire are further reduced, and the parasitic parameters of the chip packaging structure are reduced.
Correspondingly, the embodiment also provides a chip packaging structure, and fig. 11 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the invention; fig. 12 is a schematic sectional structure along FF' in fig. 11. As shown in fig. 11 and 12, based on the chip package structure provided in the above embodiment, in this embodiment, the second chip 32 further includes a fourth surface electrode 321 disposed on the upper surface of the second chip 32, and the fourth surface electrode 321 passes through the second bonding wire L 2 Electrically connected to the third conductive layer 6. Thereby, through the second bonding line L 2 The fourth surface electrode 321 and the first surface electrode 321 can be realized by directly electrically connecting the fourth surface electrode 321 and the third conductive layer 6The electrode leads are electrically connected, the second bonding wire L being compared with the bonding wire directly electrically connecting the fourth surface electrode 321 and the first electrode leads 2 The length of the chip package structure is greatly shortened, so that parasitic parameters introduced by the bonding wires are reduced, and the parasitic parameters of the chip package structure are reduced.
Alternatively, based on the above embodiment, in yet another embodiment of the present invention, fig. 13 is a schematic structural diagram of another chip package frame according to an embodiment of the present invention. As shown in fig. 13, the chip package frame further includes a fourth conductive layer, which is located outside the chip region and insulated from the first sub-conductive layer.
Considering that there is a surface electrode on the chip electrically connected to other electrode pins except the first electrode pin 41, at present, the surface electrode still needs to be directly electrically connected to the corresponding electrode pin through a bonding wire, especially for the case that the surface electrode is far away from the corresponding electrode pin due to the chip layout, the corresponding bonding wire has a long length, which can introduce a large parasitic parameter, and seriously affects the performance of the chip. Therefore, according to the embodiment, by arranging the fourth conductive layer, the fourth conductive layer can be extended from the vicinity of the corresponding surface electrode to the position close to the corresponding electrode pin on the insulating layer according to the actual layout of the chip, and the surface electrode is electrically connected with the fourth conductive layer and the fourth conductive layer is electrically connected with the corresponding electrode pin through the two sections of bonding wires, so that the electrical connection between the surface electrode and the corresponding electrode pin is realized. Therefore, the bonding positions of the bonding wires can be reasonably designed, so that the total length of the two sections of bonding wires is smaller than that of the bonding wires directly connecting the surface electrodes and the corresponding electrode pins, the length of the bonding wires is further shortened, and parasitic parameters of the chip packaging structure are reduced.
In this embodiment, the fourth conductive layers corresponding to different chips may be insulated from each other, for example, the surface electrodes of different chips are connected to different electrode pins, as shown in fig. 13, the fourth conductive layers may include a third sub-conductive layer 71 and a fourth sub-conductive layer 72, and the third sub-conductive layer 71 and the fourth sub-conductive layer 72 are insulated from each other; the fourth conductive layers corresponding to different chips can also be electrically connected, for example, the surface electrodes of different chips are connected with the same electrode pins. The present embodiment is not limited thereto, and the fourth conductive layer may be disposed according to the actual layout of the chip, so long as the total length of the bonding wire connecting the surface electrode and the fourth conductive layer and the bonding wire connecting the fourth conductive layer and the corresponding electrode pin is smaller than the length of the bonding wire directly connecting the surface electrode and the corresponding electrode pin.
Correspondingly, the embodiment also provides a chip packaging structure, and fig. 14 is a schematic structural diagram of another chip packaging structure provided by the embodiment of the invention. As shown in fig. 14, the fourth conductive layer includes a third sub-conductive layer 71, at least one electrode lead 4 further includes a second electrode lead 42, at least one surface electrode further includes a fifth surface electrode 312 disposed on the upper surface of the first chip 31, and the fifth surface electrode 312 passes through a third bonding wire L 3 Is electrically connected with the third sub-conductive layer 71, and the third sub-conductive layer 71 is connected with the third sub-conductive layer 71 via the fourth bonding wire L 4 Is electrically connected to the second electrode pin 42. At this time, the third bonding line L 3 And a fourth bonding line L 4 The sum of the lengths of the bonding wires directly electrically connecting the fifth surface electrode 312 and the second electrode lead 42 is smaller, thereby shortening the length of the bonding wires and reducing parasitic parameters of the chip package structure.
And/or the fourth conductive layer comprises a fourth sub-conductive layer 72, the at least one electrode lead 4 further comprises a third electrode lead 43, the second chip 32 further comprises a sixth surface electrode 322 disposed on the upper surface of the second chip 32, and the sixth surface electrode 322 passes through a fifth bonding wire L 5 Electrically connected to the fourth sub-conductive layer 72, the fourth sub-conductive layer 72 is connected to the fourth sub-conductive layer 72 via a sixth bonding wire L 6 Is electrically connected to the third electrode pin 43. At this time, the fifth bonding line L 5 And a sixth bonding line L 6 The sum of the lengths of the bonding wires directly electrically connecting the sixth surface electrode 322 and the third electrode lead 43 is smaller than the length of the bonding wires, thereby shortening the length of the bonding wires and reducing parasitic parameters of the chip package structure.
Alternatively, in the above embodiments, the first chip 31 and the second chip 32 may form a cascode chip. As shown in fig. 15, the first chip 31 includes a first gate electrode G1, a first source electrode S1, and a first drain electrode D1 on an upper surface of the first chip 31, and a substrate electrode (not shown) on a lower surface of the first chip 31, the second chip 32 includes a second gate electrode G2 and a second source electrode S2 on an upper surface of the second chip 32, and a second drain electrode (not shown) on a lower surface of the second chip 32,
specifically, referring to fig. 15 and 16, the first gate G1 of the first chip 31 is electrically connected to the second source S2 of the second chip 32, the first gate G1 of the first chip 31 and the second source S2 of the second chip 32 are electrically connected to the source pin S in the electrode pin 4, the first source S1 of the first chip 31 is electrically connected to the second drain D2 of the second chip 32, the second gate G2 of the second chip 32 is electrically connected to the gate pin G in the pin electrode 4, and the first drain D1 of the first chip 31 is electrically connected to the drain pin D in the pin electrode 4, thereby realizing a cascode cascade of the first chip 31 and the second chip 32.
In this embodiment, the substrate electrode of the first chip 31 is the first surface electrode in the above embodiment, the first gate electrode G1 is the second surface electrode in the above embodiment, and the first drain electrode D1 is the fifth surface electrode in the above embodiment; the second drain electrode of the second chip 32 is the third surface electrode in the above embodiment, the second source electrode S2 is the fourth surface electrode in the above embodiment, and the second gate electrode G2 is the sixth surface electrode in the above embodiment. Thus, according to the above embodiments, the first chip 31 and the second chip 32 are formed into a cascode chip, so that parasitic parameters of the cascode chip can be reduced.
Optionally, a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer. Thus, resistance matching or capacitance matching of the chip can be realized.
For example, referring to fig. 17, a resistor R is electrically connected between the third conductive layer 6 and the second sub-conductive layer 52, and an equivalent circuit diagram of the chip package structure is shown in fig. 18. The second drain electrode D2 of the second chip 32 is electrically connected with the second source electrode S2 through the resistor R, so that a leakage path is increased, the resistance matching of the second chip 32 is optimized, and the stability of the cascode chip is improved. Optionally, the resistance of the resistor R is 10 7 Omega or 10 8 Omega to ensure that its leakage capability is greater than the leakage between the drain and source of the second chip 32.
In addition, in still another embodiment of the present invention, referring to fig. 17, a capacitor C is electrically connected between the third conductive layer 6 and the second sub-conductive layer 52, and an equivalent circuit diagram of the chip package structure is shown in fig. 19. The capacitor C is used for capacitor matching of the cascode chip, and the voltage withstand performance of the cascode chip is improved. Optionally, the capacitance of the capacitor C is 100 pF-1000 pF, and the withstand voltage is greater than 50V.
Optionally, in the foregoing embodiments, the plurality of electrode pins may be located on the same side of the chip package frame, that is, form a single-side pin packaged chip package structure, so as to further improve the heat dissipation effect of the chip package structure while reducing parasitic parameters of the chip package structure.
In addition, since the AlGaN/GaN high electron mobility transistor is a wide band gap semiconductor device having a high concentration of two-dimensional electron gas in terms of semiconductor electronic devices, has characteristics of high output power density, high temperature resistance, high stability, and high breakdown voltage, and has great application potential in the field of power electronic devices, the first chip 31 may be the AlGaN/GaN high electron mobility transistor in the above embodiments. In the application of power electronic devices, in order to prevent the device from being turned on by mistake, the device is usually required to be a normally-off device, but the normally-off device of the AlGaN/GaN high-electron-mobility transistor is not easy to realize, and has the problem of gate drive compatibility, and a cascode cascade is formed by adopting a low-voltage silicon field effect transistor and a high-voltage normally-on AlGaN/GaN high-electron-mobility transistor at present, so that the enhancement type gallium nitride device is realized. Thus, in the embodiments described above in which the first chip 31 and the second chip 32 form a cascode, the first chip 31 may be a high-voltage depletion AlGaN/GaN high-electron mobility transistor and the second chip 32 may be a low-voltage enhancement-mode silicon field effect transistor. Therefore, the dynamic performance of the normally-off device can be ensured while the pressure resistance of the normally-off device is improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A chip package frame, comprising:
packaging a base;
the substrate is arranged on the packaging base and is divided into at least one chip area, and the chip area comprises a first conductive layer and an insulating layer which are stacked;
the second conductive layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and corresponds to the chip area one by one, wherein the second conductive layer comprises a first sub-conductive layer, a first conductive through hole is arranged on the insulating layer, and the first sub-conductive layer is electrically connected with the first conductive layer through the first conductive through hole;
at least one electrode pin located on at least one side of the package base and comprising a first electrode pin electrically connected with the first conductive layer;
the second conductive layer further comprises a second sub-conductive layer, and the second sub-conductive layer is insulated from the first sub-conductive layer;
the chip packaging frame further comprises a third conductive layer, the third conductive layer is arranged on the upper surface of the insulating layer and is positioned outside the chip area, a second conductive through hole is formed in the insulating layer, and the third conductive layer is electrically connected with the first conductive layer through the second conductive through hole; the third conductive layer is electrically connected with the upper surface electrode of the chip arranged on the second sub-conductive layer through a bonding wire.
2. The chip package frame of any of claims 1, further comprising a fourth conductive layer located outside the chip region and insulated from the first sub-conductive layer.
3. A chip package structure comprising at least one chip and the chip package frame according to any one of claims 1-2;
the at least one chip is attached to the chip packaging frame, and chip electrodes of the at least one chip are respectively and electrically connected with corresponding electrode pins;
the at least one chip comprises a first chip, the first chip is attached to the first sub-conductive layer, and at least one surface electrode of the first chip is electrically connected with the first sub-conductive layer.
4. The chip package structure of claim 3, wherein the at least one surface electrode comprises a first surface electrode disposed on a lower surface of the first chip, the first surface electrode being in electrical contact with the first sub-conductive layer.
5. The chip package structure of claim 3, wherein the area of the first sub-conductive layer is larger than the area occupied by the first chip, the at least one surface electrode includes a second surface electrode disposed on the upper surface of the first chip, and the second surface electrode is electrically connected to a portion of the first sub-conductive layer located outside the area of the first chip through a first bonding wire.
6. The chip package structure of claim 3, wherein the at least one second conductive layer further comprises a second sub-conductive layer, the second sub-conductive layer being insulated from the first sub-conductive layer;
the at least one chip further comprises a second chip, the second chip is mounted on the second sub-conducting layer, the second chip comprises a third surface electrode arranged on the lower surface of the second chip, and the third surface electrode is in electrical contact with the second sub-conducting layer.
7. The chip package structure according to claim 6, wherein the chip package frame further comprises a third conductive layer, the third conductive layer is disposed on the upper surface of the insulating layer, and is located outside the chip area, and a second conductive via is disposed on the insulating layer, and the third conductive layer is electrically connected to the first conductive layer through the second conductive via;
the second chip further comprises a fourth surface electrode arranged on the upper surface of the second chip, and the fourth surface electrode is electrically connected with the third conductive layer through a second bonding wire.
8. The chip package structure of claim 7, wherein the chip package frame further comprises a fourth conductive layer located outside the chip region and insulated from the first sub-conductive layer;
the fourth conductive layer comprises a third sub-conductive layer, the at least one electrode pin further comprises a second electrode pin, the at least one surface electrode further comprises a fifth surface electrode arranged on the upper surface of the first chip, the fifth surface electrode is electrically connected with the third sub-conductive layer through a third bonding wire, and the third sub-conductive layer is electrically connected with the second electrode pin through a fourth bonding wire; and/or the fourth conductive layer comprises a fourth sub-conductive layer, the at least one electrode pin further comprises a third electrode pin, the second chip further comprises a sixth surface electrode arranged on the upper surface of the second chip, the sixth surface electrode is electrically connected with the fourth sub-conductive layer through a fifth bonding wire, and the fourth sub-conductive layer is electrically connected with the third electrode pin through a sixth bonding wire.
9. The chip package structure according to claim 7, wherein a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer.
10. The chip package structure of claim 6, wherein the first chip and the second chip form a cascode.
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