CN113410135A - Method for manufacturing anti-radiation junction field effect transistor - Google Patents
Method for manufacturing anti-radiation junction field effect transistor Download PDFInfo
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- CN113410135A CN113410135A CN202110663133.7A CN202110663133A CN113410135A CN 113410135 A CN113410135 A CN 113410135A CN 202110663133 A CN202110663133 A CN 202110663133A CN 113410135 A CN113410135 A CN 113410135A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 230000005669 field effect Effects 0.000 title claims abstract description 30
- 230000003471 anti-radiation Effects 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 238000002513 implantation Methods 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 230000005855 radiation Effects 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 238000000151 deposition Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001727 in vivo Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a manufacturing method of an anti-radiation junction field effect transistor, which comprises the following processes of forming a P-type epitaxial layer on a P-type silicon substrate and forming a first dielectric layer on the P-type epitaxial layer; photoetching is carried out on the first dielectric layer to form a protective ring area; performing P-type injection on the protective ring region to form a P-type doped region; photoetching is carried out on the first medium layer of the P-type epitaxial layer to form a drift region, and N-type injection is carried out on the drift region to form an N-type doped region; forming a source drain region on the drift region by photoetching, and then performing N-type injection to form an N-type doped region; photoetching is carried out on the drift region to form a gate region; the gate region penetrates through the drift region and extends to the P-type epitaxial layer, and multiple times of P-type injection and annealing are carried out in the gate region to form a P-type doped region; forming a source electrode and a drain electrode in the drift region; forming a passivation layer on the surface; and forming a gate electrode on the back of the P-type silicon substrate to complete the anti-radiation junction field effect transistor.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing processes, and particularly belongs to a manufacturing method of an anti-radiation junction field effect transistor.
Background
The Junction Field Effect Transistor (JFET) adopts a PN junction as a grid of a device to control the opening and the closing of a channel, when negative bias of the PN junction is applied to the grid, two sides of the PN junction are exhausted, and when the channel is completely exhausted, the device is in a channel pinch-off state, and the device is closed. Otherwise, the device is on. The JFET has wide application due to the characteristics of large input impedance, high speed, low noise coefficient and the like.
In order to improve the radiation resistance of the JFET, high surface concentration of a gate region is required, but the too high surface concentration of the gate region can reduce the breakdown voltage and the pinch-off voltage of the device, and the normal operation of the device is influenced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a method for manufacturing an anti-radiation junction field effect transistor, so as to solve the problems.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for manufacturing an anti-radiation junction field effect transistor comprises the following steps,
and 8, forming a gate electrode on the back of the P-type silicon substrate, and then finishing the anti-radiation junction field effect transistor.
Preferably, in step 1, the resistivity of said P type silicon substrate is in the range of 0.0001 to 0.1 Ω & cm, and the resistivity of said P type epitaxial layer is in the range of 1 to 100 Ω & cm.
Preferably, in step 2, the P-type implantation is P + ion implantation, the impurity of the P + ion implantation is boron, the implantation energy ranges from 30keV to 120keV, and the implantation dose ranges from 1E14 to 1E17 per square centimeter.
Preferably, in step 3, the N-type implantation is N-ion implantation, the impurity of the N-ion implantation is phosphorus, the implantation energy ranges from 30keV to 120keV, and the implantation dose ranges from 1E11 to 1E14 per square centimeter.
Preferably, in step 4, the N-type implantation is N-ion implantation, the impurity of the N-ion implantation is phosphorus, the implantation energy ranges from 30keV to 120keV, and the implantation dose ranges from 1E14 to 1E17 per square centimeter.
Preferably, in step 5, the P-type implantation is P + ion implantation, the impurity of the P + ion implantation is boron, the single implantation energy ranges from 30keV to 120keV, and the single implantation dose ranges from 1E12 to 1E15 per square centimeter.
Preferably, in step 5, the number of P-type implants is 2-5.
Preferably, in step 6, the metal of the source electrode and the drain electrode is aluminum.
Preferably, in step 7, the passivation layer is made of polyimide or SiO2Or SiN, and the thickness of the passivation layer is 100 nm-5000 nm.
Preferably, in step 8, the metal of the gate electrode is one or more of Al, Ti, Ni, Ag and Au.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a manufacturing method of an anti-radiation junction field effect transistor, which forms a grid region by carrying out ion implantation and annealing for multiple times to form specific grid region surface concentration and in-vivo impurity concentration distribution, avoids the influence of overhigh grid region surface concentration on the normal work of a device, ensures high grid region surface concentration and maintains the constant grid region bulk concentration. Therefore, the breakdown voltage, the pinch-off voltage and the radiation resistance of the device can be achieved, the theory of the process method is simple and easy to understand through multiple gate injection and annealing, different process technicians can adjust according to different equipment and process conditions, the result meeting the process requirements can be obtained according to the method, and the application range is wide.
Drawings
FIG. 1 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 1 according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 2 according to the embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 3 according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 4 according to the embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 5 according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 6 according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 7 according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 8 according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 9 according to the embodiment of the present invention;
FIG. 10 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 10 according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of an anti-radiation junction field effect transistor in step 11 according to an embodiment of the present invention;
in the drawings: the transistor comprises a first dielectric layer 1, a protective ring region 2, a P-type doped region 3, a drift region 4, an N-type doped region 5, a second dielectric layer 6, a source-drain region 7, an N-type doped region 8, a third dielectric layer 9, a gate region 10, a P-type doped region 11, a source electrode 12, a drain electrode 13, a passivation layer 14 and a gate electrode 15
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
Examples
As shown in fig. 1 to 11, the process method of the radiation-resistant junction field effect transistor of the invention comprises the following steps:
step 8, performing P-type injection and annealing to form a P-type doped region 11;
step 9, forming a source electrode 12 and a drain electrode 13 on the front surface of the wafer;
step 10, coating or depositing a passivation layer 14 on the front surface of the wafer to protect the chip;
and 11, forming a gate electrode 15 on the back of the wafer, and then finishing the manufacture of the anti-radiation junction field effect transistor.
Specifically, the invention relates to a method for manufacturing an anti-radiation junction field effect transistor, which comprises the following steps:
step 8, performing P-type ion implantation and high-temperature annealing for multiple times in the gate region 10;
step 9, depositing to form SiO with a certain thickness2Forming a P-type doped region 11;
step 10, forming a source drain region ohmic contact hole by a corrosion or etching method after photoetching a pattern;
and step 13, depositing metal electrode metal on the back of the wafer to form a gate electrode 15, and finishing the manufacture of the anti-radiation junction field effect transistor.
The impurity of the P-type ion implantation in the step 2 is boron, the implantation energy is in the range of 30keV to 120keV, and the implantation dosage is 1E14 to 1E17 per square centimeter.
The impurity of N-type ion implantation in step 4 is phosphorus, the implantation energy is in the range of 30keV to 120keV, and the implantation dosage is 1E11 to 1E14 per square centimeter.
The impurity of N-type ion implantation in step 6 is phosphorus, the implantation energy is in the range of 30keV to 120keV, and the implantation dosage is 1E14 to 1E17 per square centimeter.
In the step 8, the impurity of the P-type ion implantation is boron, the implantation times are 2-5 times, the single implantation energy is in the range of 30keV to 120keV, and the single implantation dosage is 1E12 to 1E15 per square centimeter.
Deposition of SiO in step 92The thickness of the layer is 100nm to 1000 nm.
The metal of the source electrode 12 and the drain electrode 13 in step 11 is Al.
The type of the passivation layer 14 in the step 12 is polyimide, SiO2Or a combination of one or more of SiN, and the thickness of the passivation layer 14 is 100nm to 5000 nm.
The metal of the gate electrode 15 in step 13 is one or more of Al, Ti, Ni, Ag, and Au.
The invention has the advantages that the specific surface concentration and in-vivo impurity concentration distribution of the gate region can be formed through multiple gate implantation and annealing; the theory of the process method is simple and easy to understand, different process technicians can adjust the process method according to different equipment and process conditions, the result meeting the process requirements can be obtained by following the process method, and the application range is wide.
Claims (10)
1. A method for manufacturing an anti-radiation junction field effect transistor is characterized by comprising the following steps,
step 1, forming a P-type epitaxial layer on a P-type silicon substrate, and forming a first dielectric layer (1) on the P-type epitaxial layer;
step 2, photoetching is carried out on the first medium layer (1) to form a protective ring area (2); carrying out P-type injection on the protective ring region (2) to form a P-type doped region (3);
step 3, photoetching is carried out on the first medium layer (1) of the P-type epitaxial layer to form a drift region (4), and N-type injection is carried out on the drift region (4) to form an N-type doped region (5);
step 4, forming a source drain region (7) on the drift region (4) through photoetching, and then performing N-type injection to form an N-type doped region (8);
step 5, photoetching is carried out on the drift region (4) to form a gate region (10); the gate region (10) penetrates through the drift region (4) and extends to the P-type epitaxial layer, and P-type implantation and annealing are carried out in the gate region (10) for multiple times to form a P-type doped region (11);
step 6, forming a source electrode (12) and a drain electrode (13) in the drift region (4);
step 7, forming a passivation layer (14) on the surface;
and 8, forming a gate electrode (15) on the back of the P-type silicon substrate, and then finishing the anti-radiation junction field effect transistor.
2. The method of claim 1 wherein in step 1, the resistivity of said P-type silicon substrate is in the range of 0.0001 to 0.1 Ω & cm, and the resistivity of said P-type epitaxial layer is in the range of 1 to 100 Ω & cm.
3. The method as claimed in claim 1, wherein in step 2, the P-type implantation is P + ion implantation, the impurity of the P + ion implantation is boron, the implantation energy is in the range of 30keV to 120keV, and the implantation dose is in the range of 1E14 to 1E17 per square centimeter.
4. The method as claimed in claim 1, wherein in step 3, the N-type implantation is N-ion implantation, the impurity of the N-ion implantation is phosphorus, the implantation energy is in the range of 30keV to 120keV, and the implantation dose is in the range of 1E11 to 1E14 per square centimeter.
5. The method as claimed in claim 1, wherein in step 4, the N-type implantation is N-ion implantation, the impurity of the N-ion implantation is phosphorus, the implantation energy is in the range of 30keV to 120keV, and the implantation dose is in the range of 1E14 to 1E17 per square centimeter.
6. The method as claimed in claim 1, wherein in step 5, the P-type implantation is P + ion implantation, the impurity of the P + ion implantation is boron, the energy of the single implantation ranges from 30keV to 120keV, and the dose of the single implantation is 1E12 to 1E15 per square centimeter.
7. The method according to claim 1, wherein in step 5, the number of P-type implants is 2-5.
8. The method for manufacturing the radiation-resistant junction field effect transistor according to claim 1, wherein in step 6, the metal of the source electrode (12) and the drain electrode (13) is aluminum.
9. The method for manufacturing the radiation-resistant junction field effect transistor according to claim 1, wherein in the step 7, the passivation layer (14) is made of polyimide or SiO2Or a combination of one or more of SiN, and the thickness of the passivation layer (14) is 100 nm-5000 nm.
10. The method for manufacturing the radiation-resistant junction field effect transistor according to claim 1, wherein in step 8, the metal of the gate electrode (15) is one or more of Al, Ti, Ni, Ag and Au.
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