CN116069726B - Management method, equipment and medium of integrated circuit design library - Google Patents

Abstract

The application provides a management method, equipment and medium of an integrated circuit design library. The method comprises the following steps: in response to the data export request, exporting a parametrizable portion of the first design data corresponding thereto as a parametrized unit and exporting the remaining portion as a non-parametrized unit according to the associated first circuit layout file format and parameterized unit types supported by the integrated circuit design library; in response to the data import request, a parametrizable portion in the second design data corresponding thereto is determined according to the associated second circuit layout file format and parameterized cell type, and then the parametrizable portion is imported into the corresponding parameterized cell, and a non-parameterized portion is determined and a reproduction operation is performed to obtain a reproduction result, which is then imported into the design library. The reproduction operation includes classifying the non-parameterized portion according to the parameterized element type and extracting parameters according to the classification result. Thus, the design efficiency is improved.

Description

Management method, equipment and medium of integrated circuit design library

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a medium for managing an integrated circuit design library.

Background

Integrated circuits (integrated circuit, ICs) refer to circuits in which a large number of various elements such as transistors, diodes, resistors, capacitors, and inductors, and wiring are integrated on a wafer by a semiconductor process to have a specific function. With the increasing complexity and integration of integrated circuits, it is necessary to complete the design and verification of chips by means of electronic design automation (electronic design automation, EDA) tools until manufacturing. However, different EDA tool suppliers offer different EDA tool flows, data models, design data storage formats or design platforms, etc., and open source EDA tools and open standard data, etc., also exist. In the process of developing integrated circuit designs, the design is often required to be changed or an existing design scheme is introduced, and the design may involve different EDA tools, data models, design data storage formats or how data between design platforms are unified and normalized, which causes inconvenience to layout modification and design. In addition, even for single vendor flows, the lack of flexibility due to the limitations of the generic database affects the design smoothness.

Therefore, the application provides a management method, equipment and medium of an integrated circuit design library, which are used for improving the design efficiency of an integrated circuit, providing flexibility in design and being beneficial to standardization of the integrated circuit design library.

Disclosure of Invention

The embodiment of the application provides a management method, equipment and medium of an integrated circuit design library, which are used for solving the problems in the prior art.

In a first aspect, the present application provides a method of managing an integrated circuit design library. The management method comprises the following steps: in response to receiving a data export request of the integrated circuit design library, exporting a parametrizable portion of first design data in the integrated circuit design library corresponding to the data export request as a parametrizable unit stored in the first circuit layout file format according to a first circuit layout file format associated with the data export request and a parameterized unit type supported by the integrated circuit design library, and exporting a remaining portion of the first design data as a non-parametrized unit stored in the first circuit layout file format; in response to receiving a data import request of the integrated circuit design library, determining a parameterizable portion in second design data stored in the second circuit layout file format corresponding to the data import request according to a second circuit layout file format associated with the data import request and a parameterized unit type supported by the integrated circuit design library, then importing the parameterizable portion in the second design data into parameterized units in the integrated circuit design library corresponding to the parameterizable portion in the second design data, and determining a non-parameterized portion in the second design data and performing a reproduction operation on the non-parameterized portion in the second design data to obtain a reproduction result of the non-parameterized portion in the second design data, and then importing the reproduction result into the integrated circuit design library. The reproduction operation at least comprises classifying non-parameterized parts in the second design data according to parameterized unit types supported by the integrated circuit design library and extracting parameters according to classification results.

According to the first aspect of the application, the export operation is performed based on the first circuit layout file format associated with the data export request and the import operation is performed based on the second circuit layout file format associated with the data import request, so that unification and standardization are realized according to the parameterized unit types supported by the integrated circuit design library, the data size of the exported file and the data size of the integrated circuit design library after import are reduced as much as possible, the support of the standard general data model provided by the integrated circuit design library is utilized as much as possible, namely the supported parameterized unit types are utilized as much as possible, and various technologies and products provided by different EDA tool suppliers are integrated, and design flexibility is provided while design efficiency is guaranteed.

In a possible implementation manner of the first aspect of the present application, the first circuit layout file format is different from the second circuit layout file format, and the first design data corresponds to the same integrated circuit layout as the second design data.

In a possible implementation manner of the first aspect of the present application, the first circuit layout file format is different from the second circuit layout file format, and the first design data corresponds to a different integrated circuit layout than the second design data.

In a possible implementation manner of the first aspect of the present application, the first circuit layout file format is the same as the second circuit layout file format, and the first design data is the same as the second design data.

In a possible implementation manner of the first aspect of the present application, the non-parameterized portion in the second design data corresponds to a non-parameterized unit stored in the first circuit layout file format, from which the remaining portion in the first design data is derived.

In a possible implementation manner of the first aspect of the present application, the reproduction operation is a reverse reproduction operation, and the reverse reproduction operation includes classifying a non-parameterized portion in the second design data as a parameterized unit type corresponding to a remaining portion in the first design data.

In a possible implementation manner of the first aspect of the present application, the non-parameterized units stored in the first circuit layout file format, from which the remaining portion of the first design data is derived, are determined by comparing parameterized unit types supported by the first circuit layout file format with parameterized unit types supported by the integrated circuit design library.

In a possible implementation manner of the first aspect of the present application, the parameterizable portion in the first design data is derived to obtain parameterized units stored in the first circuit layout file format, and the parameterized unit types supported by the first circuit layout file format and the parameterized unit types supported by the integrated circuit design library are determined by comparing.

In a possible implementation manner of the first aspect of the present application, the non-parameterized portion in the second design data is determined by comparing parameterized cell types supported by the second circuit layout file format with parameterized cell types supported by the integrated circuit design library.

In a possible implementation manner of the first aspect of the present application, the parametrizable portion in the second design data is determined by comparing a parameterized cell type supported by the second circuit layout file format with a parameterized cell type supported by the integrated circuit design library.

In a possible implementation manner of the first aspect of the present application, the integrated circuit design library is an open acquisition library, a Galaxy library, or is from an open source design platform.

In one possible implementation of the first aspect of the present application, the parametrizable portion of the first design data and the parametrizable portion of the second design data are used in a process design suite, which is Synopsys, cadence, mentor, empyrean, or sambucus.

In a possible implementation manner of the first aspect of the present application, the parametrizable portion of the first design data and the parametrizable portion of the second design data are used for the same process design kit or for different process design kits.

In a possible implementation manner of the first aspect of the present application, the reproducing operation further includes naming a non-parameterized portion of the second design data according to the process design kit.

In a possible implementation manner of the first aspect of the present application, the first circuit layout file format and/or the second circuit layout file format is a GDS, a GDSII, or an OASIS.

In a possible implementation manner of the first aspect of the present application, the parameterized cell types supported by the integrated circuit design library include field effect transistors, triodes, resistors, capacitors, holes, and guard rings.

In a possible implementation manner of the first aspect of the present application, when the classification result of the non-parameterized portion in the second design data includes a field effect transistor, performing parameter extraction according to the classification result includes extracting a length, a width, an origin, or a direction of the field effect transistor.

In a possible implementation manner of the first aspect of the present application, the reproducing operation further includes replacing the non-parameterized portion in the second design data with a parameter extraction result.

In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product, characterized in that the computer program product comprises instructions stored on a computer-readable storage medium, which instructions, when run on a computer device, cause the computer device to perform a method according to any one of the implementation forms of any one of the preceding aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a chip design flow provided in an embodiment of the present application;

FIG. 2 is a flow chart of a method for managing an integrated circuit design library according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a reverse replication automation process according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The embodiment of the application provides a management method, equipment and medium of an integrated circuit design library, which are used for solving the problems in the prior art. The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated.

It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

Fig. 1 is a schematic diagram of a chip design flow provided in an embodiment of the present application. As shown in FIG. 1, the chip design flow includes front-end design 102, front-end simulation 104, back-end design 106, verification 108, back-end simulation 110, and packet delivery 112. Front-end design 102 describes the hardware behavior, structure, and data flow of the circuitry in a hardware description language (hardware description language, HDL), such as the common Verilog HDL, on the basis of specification formulation, i.e., setting up the purpose and performance of the chip and the agreed standards that need to be met, and performing functional allocation and unit division. The front-end design 102 is typically described in terms of code, such as HDL, and may be described in terms of circuitry for a particular analog circuit design. Special specification definition and system design links may be performed before the front-end design 102 to determine the chip's requirement analysis and to determine the overall design direction, such as determining the cost control level, the power consumption sensitivity level, the supported connection mode, the system security level, etc., and further to determine the chip architecture, the service modules, the power supply system, etc., i.e., to perform functional allocation and unit division, such as determining interactions between systems, specific interfaces, etc. After the front-end design 102, a front-end simulation 104 is performed. The front end simulation 104 primarily performs functional and performance simulations of the design of the front end design 102, such as formulating verification schemes based on the design under test (design under test, DUT), drawing and configuring the environmental block diagram through platform tools provided by the verification platform and generating a verification environment. The front-end simulation 104, also called front-end simulation, helps to verify whether the chip design meets requirements such as correctness of logic timing, etc. before chip production, and provides specification of corresponding standards, unification of coding style and environment architecture of the verification platform, etc. through verification methodology. Common authentication methodologies include general authentication methodologies (universal verification methodology, UVM), authentication methodologies manual (verification methodology manual, VMM) and open authentication methodologies (open verification methodology, OVM). Back-end design 106 is performed after front-end simulation 104, and back-end design 106 converts HDL code into a logic circuit diagram and performs simulation verification, typically by an electronic design automation (electronic design automation, EDA) tool; finally, the logic circuit diagram is converted into a gate-level circuit netlist (netlist) through the automatic synthesis function of an EDA tool, and circuit layout (floor plan) and routing (routing) are carried out so as to obtain a specific circuit wiring structure. The back-end design 106 includes a physical design and a layout design (as opposed to the front-end design 102 including a logic design) for converting the front-end data obtained through the front-end design 102 and the front-simulation 104, including device symbols, codes, etc., into physical graphics that can be used for subsequent links. That is, HDL is used in front-end design 102 for register transfer level (Register Transfer Level, RTL) code description of hardware behavior, structure, and data flow of circuitry; the RTL code thus generated is passed through the pre-simulation 104 to verify the correctness of the code design, and at the back-end design 106, the code description of the RTL is converted into a gate level netlist by the automatic synthesis function of a logic synthesis tool, such as an EDA tool. The back-end design 106 generates an integrated circuit layout (integrated circuit layout) for use by subsequent manufacturers to fabricate masks (masks). The integrated circuit layout is the result of the physical design of the bottommost step in the integrated circuit design, and the result of logic synthesis (gate-level netlist) is converted into a physical layout file on the basis of the physical design by a layout and wiring technology, and the file contains the shape, area and position information of each hardware unit on a chip. The layout design must adhere to the relevant design rule requirements of the manufacturing process and meet the constraints of timing, area, power consumption, etc. After the back-end design 106 has completed the design of the integrated circuit layout, verification 108 is performed, including design rule checking (Design Rule Check, DRC) verification and layout logic diagram matching (Layout Versus Schematics, LVS) verification. In order to ensure that the design of the integrated circuit layout obtained at the back-end design 106 meets the requirements of relevant design rules and the logic diagram obtained by the simulation before matching 104, DRC verification includes checking whether the layout has potential open circuits, short circuits or adverse effects caused by violating the design rules, which embody constraints in terms of geometric dimensions, etc. that are established by the foundry for different process parameters to meet the chip manufacturing yield, for example, determining that the design rules, such as minimum width, minimum pitch, etc. are met; LVS verification involves comparing the connectivity of the layout and logic diagram at the transistor level, such as by comparing the device types, sizes, wires, etc. of the netlist, and finding out where there is a disparity between the layout and logic diagram, such as node disparity, device disparity, etc. After verification 108, a back-end simulation 110, also called back-end simulation, is performed. The front-end design 102 generally makes a certain estimate of parasitic capacitance, parasitic resistance, process parameters, etc. and provides a certain margin in design, and introduces actual parasitic capacitance, parasitic resistance, etc. when the back-end design 106 is, that is, when generating a physical pattern, in order to avoid affecting the performance power consumption of the final chip product, the back-simulation 110 determines the influence of the trace, etc. on the parasitic capacitance, parasitic resistance, etc. and feeds back to the front-end design 102 and the back-end design 106. After the post-simulation 110, the entire integrated circuit design flow is essentially completed, followed by packet delivery 112, i.e., delivery of layout files for manufacturing to a semiconductor processing plant, from which the actual hardware chips are manufactured using semiconductor device manufacturing equipment and techniques. The chip manufacturing comprises the steps of processing and generating a circuit on a silicon wafer (front-end production) and filling through holes and manufacturing electric connection wires among transistors on the basis of the silicon wafer with the circuit processed, and cutting and packaging to obtain a chip finished product (back-end production). Various variations of the chip design flow illustrated in fig. 1 are possible, with the complexity of the links being increased or decreased, but the basic design flow includes front-end design and simulation followed by back-end design and simulation. In addition, there are often signature off checks in the chip design data, which represent the last rule verification after the front-end design and back-end design are completed.

With continued reference to fig. 1, with the widespread use of System On Chip (SOC) and the development of more advanced process, it is important to discover potential problems in advance and reduce the risk of chip failure during the chip design stage, so that chip verification occupies most of the workload of the whole chip design process, which means that the improvement of chip verification efficiency and the improvement of chip verification environment have a significant impact on the development cycle of the chip project and the subsequent production efficiency. The various links from the front-end design 102 to the data packet delivery 112 described above constitute the basic flow of the chip design, where the various links may use various EDA tools or software, etc., such as tools for circuit and layout design, tools for layout physical verification, tools for RTL code synthesis, tools for analysis of timing power consumption noise, etc. Some EDA tool suppliers offer design-platform products, providing a complete set of products for each link of the chip design flow to form a closed-loop of products. Some EDA tool suppliers offer technologies and products that have outstanding performance in certain segments and even become industry standards. In the process of integrated circuit design development, products from a single vendor, such as a complete set of design platform products, may be used, and the most appropriate technology and products for each link may be selected from multiple vendors, thus requiring integration of tools with differentiation, and also facing differences in data models, e.g., different EDA tools may provide different standard models and different design libraries. In addition, even with the design-platfonn products provided by a single EDA tool vendor, the limitations imposed by the generic database, generic data model, and thus affect design flexibility and design fluency. How the above challenges are addressed is described in detail below in connection with other embodiments of the present application.

Fig. 2 is a flowchart of a method for managing an integrated circuit design library according to an embodiment of the present application. As shown in fig. 2, the management method includes the following steps.

Step S210: in response to receiving a data export request from the integrated circuit design library, exporting a parametrizable portion of first design data in the integrated circuit design library corresponding to the data export request as a parametrizable unit stored in the first circuit layout file format and exporting the remaining portion of the first design data as a non-parametrized unit stored in the first circuit layout file format according to a first circuit layout file format associated with the data export request and a parameterized unit type supported by the integrated circuit design library.

Step S220: in response to receiving a data import request of the integrated circuit design library, determining a parameterizable portion in second design data stored in the second circuit layout file format corresponding to the data import request according to a second circuit layout file format associated with the data import request and a parameterized unit type supported by the integrated circuit design library, then importing the parameterizable portion in the second design data into parameterized units in the integrated circuit design library corresponding to the parameterizable portion in the second design data, and determining a non-parameterized portion in the second design data and performing a reproduction operation on the non-parameterized portion in the second design data to obtain a reproduction result of the non-parameterized portion in the second design data, and then importing the reproduction result into the integrated circuit design library.

The reproduction operation at least comprises classifying non-parameterized parts in the second design data according to parameterized unit types supported by the integrated circuit design library and extracting parameters according to classification results.

Referring to the steps of the integrated circuit design library management method described above and to fig. 2, the integrated circuit design library is a reference database used in the chip design flow and generally includes standard programming interfaces (Application Programming Interface, API) for interaction between EDA vendors, semiconductor designers, and semiconductor manufacturers. EDA tool suppliers may provide standard data models and unified design data storage formats by providing integrated circuit design libraries, such as the Open Access (OA) library also known as the OA library, provided by Cadence corporation, which is a reference database that provides open standard data APIs and APIs supporting IC designs for unified data exchange between integrated circuit design tools; there is also a storage format design platform provided by Synopsys, inc. that provides a unified design for the Galaxy (Milkway) library. Also similar are products or services offered by Empyrean, or nine days from China, etc. Integrated circuit design libraries typically include parameterized cells (Parameterized Cell, pcell), which are circuit cells that can be parameterized and modified, which describe possible customization methods for devices such as transistors and other devices so that semiconductor designers can use Pcell in using EDA tools to quickly customize devices to improve design efficiency. In the chip design flow shown in fig. 1, the design scheme generated in the front-end design 102, i.e., the logic design (e.g., RTL code), needs to be converted into layout files at the back-end design 106 and used for subsequent manufacturing links. To ensure that the fab can produce chips based on design and ensure that the intended functions and performance are achieved, a set of documentation reflecting the details of the semiconductor process needs to be provided to the EDA tool manufacturer for physical verification in conjunction with the specific details of the semiconductor process. The technology package required for such a design is called a process design kit (Process Design Kit, PDK) which contains elements reflecting the basic manufacturing process, such as transistors, contact holes, interconnects, etc. The content of the PDK generally includes design rule files, electrical rule files, layout hierarchy definition files, SPICE simulation models, device layout, device customization parameters, and the like. The Pcells in the integrated circuit design library, i.e., parameterized cells, are circuit cells in the content of the PDK that facilitate modification of design parameters, instantiation, and repeated invocation. In addition, the layout files of the integrated circuit layout design obtained at the back-end design 106 typically have a particular file format, such as a graphic design system (Graphic Design System, GDS). The GDS is a file storage standard for storing mask images, and the GDS file represents geometric figures, characters of planes, layers and attributes of the figures, and other data by binary coding. When it is desired to export design data from an integrated circuit design library, such as an OA library, it is typically exported in a particular file format, such as GDS format, which is an input material to the EDA tool so that the EDA presents the hierarchical circuit design layout in two dimensions. The content of the PDK comprises a technical file and a process file for layout design and verification, wherein the technical file comprises a mapping relation definition of a design data layer and a process layer in a specific file format such as GDS format, an attribute definition of the design data layer, an online design rule, an electrical rule, a color display definition, a graphic format definition and the like. As mentioned above, in the process of developing an integrated circuit design, a product from a single vendor, such as a complete set of design platform products, may be used, or the most suitable technology and product for each link may be selected from multiple vendors, and thus different EDA tools, data models, design data storage formats, or design platforms may be involved, and in addition, the products of the same EDA tool vendor typically provide standard generic data models and design libraries, which means that problems in standardization and flexibility of design data may be faced in a particular chip design. For example, in some application scenarios, when design data is exported from an integrated circuit design library, such as an OA library, into a particular circuit layout file format, such as a GDS format, modifications may be required to the exported integrated circuit design, and when the modified design data is reintroduced into the integrated circuit design library, it may be found that some of the designs do not correspond to parameterized cells in the integrated circuit design library, such designs may be due to changes that are beyond the scope supported by the parameterized cells or due to the introduction of other EDA tools during modification of the design data, and finally the design portions that cannot correspond to the parameterized cells may be stored as separate cells in the integrated circuit design library, and may still be stored as separate cells in the integrated circuit layout file when the separate cells are subsequently exported again. However, because it is difficult to make accurate predictions of the modifications faced by the design data and the intervention of other EDA tools when the design data is initially derived from the integrated circuit design library, it is necessary to store such difficult-to-parameterize design elements through a large amount of memory space, thereby burdening the server and also affecting design efficiency. Furthermore, as the hardware size and complexity of on-chip integration increases, the chip design process may need to face multiple similar importation of data stored in GDS format into and exportation of design data from the integrated circuit design library into data stored in GDS format, and modifications to the integrated circuit design between each importation and exportation operation may also need to be introduced as well as the effects of other EDA tools. In addition, techniques and products from different EDA tool suppliers may employ different standard data models, thus making the scope of parameterized cells supported in the respective design libraries inconsistent, a given design cell may be parameterizable in one design library and non-parameterizable in another design library. In addition, different EDA tools or different wafer factories may provide the contents of different PDKs, which may also result in a given design unit being parametrizable in one design library and non-parametrizable in another design library. In addition, different tools and products may employ different storage formats for layout files, the same integrated circuit design may be exported as a layout file in one format and then imported as a layout file in another format, and the effects of format differences may also create design elements that are difficult to parameterize or difficult to describe with standard generic parameterization elements. Even for a complete set of EDA tools, such as a design platform, for a product of the same EDA tool vendor, design elements that are difficult to parameterize may be generated because changes to the circuit layout design are outside the scope supported by the parameterized elements. In addition, the integrated circuit design library, that is, the reference database used in the chip design flow, is generally provided by the EDA tool provider, but the coverage of the parameterized units supported by the reference database may not be consistent with the file format stored after the design data is exported, so that some of the design units originally stored in the form of parameterized units in the content of the PDK are finally stored in the layout design file as independent units which cannot be parameterized after being exported, so that when the design units are subsequently imported, the design units stored in the form of parameterized units before being exported are finally stored in the design library in the form of independent units which cannot be parameterized, thereby increasing the load of a server and affecting the design efficiency.

With continued reference to fig. 2, in step S210, in response to receiving a data export request of the integrated circuit design library, a parametrizable portion of first design data in the integrated circuit design library corresponding to the data export request is exported as a parametrized unit stored in the first circuit layout file format, and a remaining portion of the first design data is exported as a non-parametrized unit stored in the first circuit layout file format, according to a first circuit layout file format associated with the data export request and a parameterized unit type supported by the integrated circuit design library. In this way, considering possible differences between the first circuit layout file format and the parameterized cell types supported by the integrated circuit design library, adapting the first circuit layout file format is achieved by exporting parameterizable portions of the first design data in the integrated circuit design library corresponding to the data export request as parameterized cells stored in the first circuit layout file format, achieving a data size of the layout file exported in compression as much as possible, and exporting the remaining portions of the first design data as non-parameterized cells stored in the first circuit layout file format. Wherein the first circuit layout file format is a file format associated with the data export request, and may be, for example, a GDS format or any other file format. The data export request represents any possible request to export design data from the integrated circuit design library, possibly for modification of the design, or for functional verification or for federation with other EDA tools, or any other requirement. In step S220, in response to receiving a data import request of the integrated circuit design library, a parametrizable portion in second design data stored in the second circuit layout file format corresponding to the data import request is determined according to a second circuit layout file format associated with the data import request and a parameterized unit type supported by the integrated circuit design library, and then the parametrizable portion in the second design data is imported into parameterized units in the integrated circuit design library corresponding to the parametrizable portion in the second design data. Here, the second circuit layout file format is associated with a data import request, referring to the storage format of the file to be imported into the integrated circuit design library. The second circuit layout file format may or may not be the same as the first circuit layout file format. Thus, the second circuit layout file format associated with the data import request represents any of the possible data import requirements, and thus may be adapted to the various situations described above, e.g., different tools and products may employ different layout file storage formats, etc. And, according to the second circuit layout file format associated with the data import request and the parameterized unit type supported by the integrated circuit design library, the parameterizable portion in the second design data stored in the second circuit layout file format corresponding to the data import request is determined, which means that the parameterizable portion in the second design data is determined in consideration of possible differences between the second circuit layout file format and the parameterized unit type supported by the integrated circuit design library, so that the data size of the integrated circuit design library after the import is compressed as much as possible is also adapted to the second circuit layout file format, and thus any possible data import requirement can be met. And, in step S220, determining the non-parameterized portion in the second design data and performing a reproduction operation on the non-parameterized portion in the second design data to obtain a reproduction result of the non-parameterized portion in the second design data, and then importing the reproduction result into the integrated circuit design library. Here, the reproduction operation includes at least classifying the non-parameterized portion of the second design data according to the parameterized cell types supported by the integrated circuit design library and performing parameter extraction according to the classification result. In this way, by determining the parametrizable portion in the second design data and determining the non-parametrizable portion in the second design data, and then performing a reproduction operation on the non-parametrizable portion in the second design data to obtain a reproduction result of the non-parametrized portion in the second design data, it is achieved that the second design data is processed in a targeted manner according to the second circuit layout file format associated with the data import request and the type of the parameterized unit supported by the integrated circuit design library, the parametrizable portion is imported into the corresponding parameterized unit to compress the data size, and performing the reproduction operation on the non-parametrizable portion includes classifying the non-parametrized portion and extracting parameters according to the classification result, which is equivalent to unified normalization of the non-parametrized portion. By performing the operations described in step S210 and the operations described in step S220 on the data import request, respectively, it is achieved that the exporting operation is performed based on the first circuit layout file format associated with the data import request (including exporting the parametrizable portion of the first design data corresponding to the data export request in the integrated circuit design library to parametrizable portions stored in the first circuit layout file format, and exporting the remaining portion of the first design data to non-parametrizable portions stored in the first circuit layout file format) and the importing operation is performed based on the second circuit layout file format associated with the data import request (including determining the parametrizable portion of the second design data corresponding to the data import request in the second circuit layout file format, and then exporting the parametrizable portion of the second design data in the second design data to non-parametrizable portions in the second design data, and then copying the data corresponding to the second circuit layout file format, based on the second circuit layout file format associated with the data import request and the second circuit layout file format supported by the integrated circuit layout file library, determining whether the current parameter portion of the second design data corresponds to the second circuit layout file format data corresponding to the second circuit layout file format, the integrated circuit design library realizes unification and standardization according to the parameterized unit types supported by the integrated circuit design library, is beneficial to reducing the data scale of the exported files and the data scale of the imported integrated circuit design library as much as possible, and utilizes the support of the standard general data model provided by the integrated circuit design library, namely the supported parameterized unit types, is beneficial to integrating various technologies and products provided by different EDA tool suppliers, and ensures design efficiency while providing design flexibility.

With continued reference to FIG. 2, it was mentioned above that for the application scenario of multiple EDA tool suppliers, different EDA tool supplier techniques and products may employ different standard data models and result in the range of parameterized cells supported in the respective design libraries may not be uniform, further the content of different PDKs may result in a given design cell being parameterizable in one design library and non-parameterizable in another design library, further different tools and products may employ different storage formats for layout files and format differences may also result in design cells that are difficult to parameterize or design cells that are difficult to describe with standard generic parameterized cells. For the application scenario of the same EDA tool vendor, it is also possible to generate design elements that are difficult to parameterize because the changes to the circuit layout design are outside the scope supported by the parameterized elements. In view of these application scenarios, a method for managing an integrated circuit design library as described above provides a reliable solution. In particular, in one possible implementation, the first circuit layout file format is different from the second circuit layout file format, and the first design data corresponds to the same integrated circuit layout as the second design data. This means that the embodiments of the present application are at least applicable to application scenarios where the layout file format changes, which may be caused by using different EDA tools or PDKs. In one possible implementation, the first circuit layout file format is different from the second circuit layout file format, and the first design data corresponds to a different integrated circuit layout than the second design data. This means that the embodiment of the present application is at least suitable for changing the format of the layout file, and at the same time, changing the application scenario of the original integrated circuit layout, or corresponding to the application scenario. In one possible implementation, the first circuit layout file format is the same as the second circuit layout file format, and the first design data is the same as the second design data. This means that the embodiments of the present application are at least applicable to application scenarios of the same EDA tool provider, or correspond to application scenarios where design data is exported, then validated for simulation, and then imported into the design library. As mentioned above, for the same EDA tool vendor application scenario, it is also possible to generate design elements that are difficult to parameterize because the changes to the circuit layout design are outside the range supported by the parameterized elements. In addition, for the application scenario of the same EDA tool provider, the coverage of the parameterized units supported by the design library provided by the EDA tool provider may not be consistent with the file format stored after the design data is exported, so that some design units originally stored in a parameterized unit manner in the content of the PDK are finally stored in the layout design file as independent units which cannot be parameterized after being exported, and thus, when the design library is subsequently imported, the design units stored in a parameterized unit manner before being exported are finally stored in the design library in an independent unit manner which cannot be parameterized. In some embodiments, the non-parameterized portion of the second design data corresponds to non-parameterized cells stored in the first circuit layout file format from which the remainder of the first design data was derived. This means that, when the first circuit layout file format is the same as the second circuit layout file format and the first design data is the same as the second design data, the non-parameterized part in the second design data corresponds to the non-parameterized unit derived from the rest of the first design data and stored in the first circuit layout file format, so that the design unit difficult to parameterize due to the import and export operation can be avoided, which is beneficial to reducing the load of the server and improving the design efficiency. In some embodiments, the reproduction operation is a reverse reproduction operation that includes classifying a non-parameterized portion of the second design data as a parameterized cell type corresponding to a remaining portion of the first design data. Therefore, through the reverse reproduction operation, the design unit which is difficult to parameterize and is generated due to the import and export operation is avoided, and the server load is reduced and the design efficiency is improved.

In one possible implementation, the non-parameterized cells stored in the first circuit layout file format from which the remainder of the first design data is derived are determined by comparing parameterized cell types supported by the first circuit layout file format with parameterized cell types supported by the integrated circuit design library. Thus, the difference between the parameterized unit types supported by the first circuit layout file format and the parameterized unit types supported by the integrated circuit design library is adapted.

In one possible implementation, the parameterizable portion of the first design data is derived from parameterized cells stored in the first circuit layout file format by comparing parameterized cell types supported by the first circuit layout file format with parameterized cell types supported by the integrated circuit design library. Thus, the difference between the parameterized unit types supported by the first circuit layout file format and the parameterized unit types supported by the integrated circuit design library is adapted.

In one possible implementation, the non-parameterized portion of the second design data is determined by comparing parameterized cell types supported by the second circuit layout file format with parameterized cell types supported by the integrated circuit design library. Thus, the difference between the parameterized unit type supported by the second circuit layout file format and the parameterized unit type supported by the integrated circuit design library is adapted.

In one possible implementation, the parametrizable portion of the second design data is determined by comparing the parameterized cell types supported by the second circuit layout file format with the parameterized cell types supported by the integrated circuit design library. Thus, the difference between the parameterized unit type supported by the second circuit layout file format and the parameterized unit type supported by the integrated circuit design library is adapted.

In one possible implementation, the integrated circuit design library is an open acquisition library, a Galaxy library, or from an open source design platform. Here, an Open Access (OA) library, also called an OA library, provided by Cadence corporation is a reference database that provides an open standard data API and an API supporting IC design for unified data exchange between integrated circuit design tools. The Galaxy (Milkway) library offered by Synopsys, inc. provides a uniformly designed storage format design platform. The open source design platform may be any open source standard database or open source EDA tool.

In one possible implementation, the parametrizable portion of the first design data and the parametrizable portion of the second design data are for a process design kit that is Synopsys, cadence, mentor, empyrean, or sampsonian. In some embodiments, the parametrizable portion of the first design data and the parametrizable portion of the second design data are for the same process design kit or different process design kits. In some embodiments, the reproducing operation further includes naming the non-parameterized portion of the second design data according to the process design suite. Thus, classification and blackness can be better achieved by specific naming rules, such as adding tool names and numbers to device names.

In one possible implementation, the first and/or second circuit layout file formats are GDS, GDSII, or OASIS. Here, any storage format of the layout design file may be used.

In one possible implementation, the parameterized cell types supported by the integrated circuit design library include field effect transistors, triodes, resistors, capacitors, holes, guard rings. In some implementations, when the classification result of the non-parameterized portion in the second design data includes a field effect transistor, performing parameter extraction according to the classification result includes extracting a length, a width, an origin, or a direction of the field effect transistor. In some implementations, the reproducing operation further includes replacing the non-parameterized portion of the second design data with the parameter extraction results. Here, for the data model of the field effect transistor, parameter extraction may be performed by extracting the length, width, origin or direction of the field effect transistor, and the reproduction result thus obtained may also replace the non-parameterized portion in the second design data, thereby completing the uniform normalization of the equivalent non-parameterized portion.

Fig. 3 is a schematic diagram of a reverse reproduction automation flow provided in an embodiment of the present application. As shown in fig. 3, the reverse replication automation flow includes the following steps.

Step S302: GDS was introduced.

Step S304: an OA library with scattered Pcell is obtained.

Step S306: the scattered Pcells are classified.

Step S308: and respectively establishing mapping according to the classifications.

Step S310: the Pcell is reproduced inversely.

Step S312: an OA library with scattered Pcell is obtained.

Referring to the details of fig. 2, when the first circuit layout file format is the same as the second circuit layout file format and the first design data is the same as the second design data, the non-parameterized portion in the second design data corresponds to the non-parameterized unit stored in the first circuit layout file format, which is derived from the rest of the first design data, so that the design unit which is difficult to parameterize due to the import and export operation can be avoided, which is beneficial to reducing the load of the server and improving the design efficiency. Thus, the reproduction operation is a reverse reproduction operation that includes classifying the non-parameterized portion of the second design data as the parameterized cell type corresponding to the remaining portion of the first design data. Therefore, through the reverse reproduction operation, the design unit which is difficult to parameterize and is generated due to the import and export operation is avoided, and the server load is reduced and the design efficiency is improved. Specifically, the first circuit layout file format is the same as the second circuit layout file format and is the GDS format, and the integrated circuit design library is an OA library. The scattered Pcell refers to a non-parameterized portion, i.e., a design cell in the design data that is difficult to parameterize. Through each step shown in fig. 3, reverse reproduction is finally realized, so that the problem that design units which are difficult to parameterize are stored in an OA library in a mode of independent units is avoided, and the server load is reduced and the design efficiency is improved.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the present embodiment, the computing device 400 may be configured to implement some or all of the functions of one or more components of the apparatus embodiments described above, and the communication interface 420 may be configured to implement communication functions and the like necessary for the functions of the apparatuses, components, and the processor 410 may be configured to implement processing functions and the like necessary for the functions of the apparatuses, components.

It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.

The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in this embodiment. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.

The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.

The bus 440 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.

Embodiments of the present application also provide a system that includes a plurality of computing devices, where each computing device may have a structure that refers to the structure of the computing device described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein. Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again. Embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform the method steps in the method embodiments described above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims (14)

1. A method of managing an integrated circuit design library, the method comprising:

in response to receiving a data export request of the integrated circuit design library, exporting a parametrizable portion of first design data in the integrated circuit design library corresponding to the data export request as a parametrizable unit stored in the first circuit layout file format according to a first circuit layout file format associated with the data export request and a parameterized unit type supported by the integrated circuit design library, and exporting a remaining portion of the first design data as a non-parametrized unit stored in the first circuit layout file format;

In response to receiving a data import request of the integrated circuit design library, determining a parameterizable portion in second design data stored in the second circuit layout file format corresponding to the data import request according to a second circuit layout file format associated with the data import request and parameterized cell types supported by the integrated circuit design library, then importing the parameterizable portion in the second design data into parameterized cells in the integrated circuit design library corresponding to the parameterizable portion in the second design data, and determining a non-parameterized portion in the second design data and performing a reproduction operation on the non-parameterized portion in the second design data to obtain a reproduction result of the non-parameterized portion in the second design data, then importing the reproduction result into the integrated circuit design library,

wherein the reproduction operation includes at least classifying non-parameterized portions of the second design data according to parameterized cell types supported by the integrated circuit design library and performing parameter extraction according to classification results,

the data export request corresponds to a first file, the storage format of the first file is the first circuit layout file format, the data import request corresponds to a second file, the storage format of the second file is the second circuit layout file format,

The non-parametric portion of the second design data corresponds to the non-parametric unit of the first design data that is derived from the remainder of the first design data and stored in the first circuit layout file format, the rendering operation being a reverse rendering operation comprising classifying the non-parametric portion of the second design data as a type of parametric unit corresponding to the remainder of the first design data,

the non-parameterized cells stored in the first circuit layout file format derived from the remainder of the first design data are determined by comparing parameterized cell types supported by the first circuit layout file format with parameterized cell types supported by the integrated circuit design library, the parameterizable cells stored in the first circuit layout file format derived from the parameterizable portion of the first design data are determined by comparing parameterized cell types supported by the first circuit layout file format with parameterized cell types supported by the integrated circuit design library,

the non-parameterized portion of the second design data is determined by comparing parameterized cell types supported by the second circuit layout file format with parameterized cell types supported by the integrated circuit design library, and the parameterizable portion of the second design data is determined by comparing parameterized cell types supported by the second circuit layout file format with parameterized cell types supported by the integrated circuit design library.

2. The method of claim 1, wherein the first circuit layout file format is different from the second circuit layout file format, and wherein the first design data corresponds to the same integrated circuit layout as the second design data.

3. The method of managing of claim 1, wherein the first circuit layout file format is different from the second circuit layout file format, the first design data corresponding to a different integrated circuit layout than the second design data.

4. The method of managing of claim 1, wherein the first circuit layout file format is the same as the second circuit layout file format, and wherein the first design data is the same as the second design data.

5. The method of claim 1, wherein the integrated circuit design library is an open acquisition library, a Galaxy library, or from an open source design platform.

6. The method of claim 1, wherein the parametrizable portion of the first design data and the parametrizable portion of the second design data are used in a process design suite, the process design suite being Synopsys, cadence, mentor, empyrean, or sambucus.

7. The method of claim 6, wherein the parametrizable portion of the first design data and the parametrizable portion of the second design data are for a same process design kit or different process design kits.

8. The method of claim 6, wherein the reproducing operation further comprises naming a non-parameterized portion of the second design data based on the process design suite.

9. The method of claim 1, wherein the first and/or second circuit layout file formats are GDS, GDSII, or OASIS.

10. The method of claim 1, wherein the parameterized cell types supported by the integrated circuit design library include field effect transistors, resistors, capacitors, holes, guard rings.

11. The method of claim 10, wherein when the classification result of the non-parameterized portion in the second design data includes a field effect transistor, performing parameter extraction according to the classification result includes extracting a length, a width, an origin, or a direction of the field effect transistor.

12. The method of managing of claim 10, wherein the reproducing operation further comprises replacing non-parameterized portions of the second design data with parameter extraction results.

13. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 12 when executing the computer program.

14. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 12.

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