CN113381737A - Schmitt trigger with adjustable forward threshold voltage - Google Patents

Schmitt trigger with adjustable forward threshold voltage Download PDF

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Publication number
CN113381737A
CN113381737A CN202110710441.0A CN202110710441A CN113381737A CN 113381737 A CN113381737 A CN 113381737A CN 202110710441 A CN202110710441 A CN 202110710441A CN 113381737 A CN113381737 A CN 113381737A
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CN
China
Prior art keywords
pmos transistor
drain electrode
threshold voltage
transistor
electrode
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Pending
Application number
CN202110710441.0A
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Chinese (zh)
Inventor
吴佳
李礼
吴叶楠
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Shanghai V&g Information Technology Co ltd
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Shanghai V&g Information Technology Co ltd
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Priority to CN202110710441.0A priority Critical patent/CN113381737A/en
Publication of CN113381737A publication Critical patent/CN113381737A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356165—Bistable circuits using complementary field-effect transistors using additional transistors in the feedback circuit

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  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a Schmitt trigger with adjustable forward threshold voltage, which comprises a PMOS (P-channel metal oxide semiconductor) transistor group, a first NMOS (N-channel metal oxide semiconductor) transistor and a phase inverter, wherein the PMOS transistor group is connected with the first NMOS transistor; the input ports of the first PMOS transistor and the first NMOS transistor are input signals IN, and the input port of the third PMOS transistor is a forward threshold voltage adjusting signal ADP; the output ports of the PMOS transistor group and the first NMOS transistor are output signals OUT; the drain electrode of the PMOS transistor group is connected with the drain electrode of the first NMOS transistor and the input end of the phase inverter, the source electrode and the body of the PMOS transistor group are connected with a power supply VDD, and the grid electrode of the PMOS transistor group is connected with an input signal IN. The invention can change the forward threshold voltage by adjusting the voltage of the forward threshold voltage adjusting signal ADP.

Description

Schmitt trigger with adjustable forward threshold voltage
Technical Field
The invention relates to the technical field of Schmitt triggers, in particular to a Schmitt trigger with adjustable forward threshold voltage.
Background
The Schmitt trigger is often placed at an input port of the integrated circuit to serve as a waveform shaping circuit, and can shape external signal waveforms with interference into standard square wave waveforms, so that the influence of the external interference on the inside of the integrated circuit is reduced, and the processing speed of the integrated circuit is increased. A conventional schmitt trigger is the structure shown in fig. 1.
Schmitt triggers have two stable states, but unlike conventional triggers, schmitt triggers use a potential-triggered approach, the state of which is maintained by the input signal potential. Referring to fig. 2, the schmitt trigger has different threshold voltages for two different changing directions of input signals, namely negative-going decreasing and positive-going increasing. That is, when the input voltage is higher than the forward threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output is unchanged, that is, the corresponding threshold voltage is different when the output is inverted from high level to low level or from low level to high level. The output level changes only when the input level changes sufficiently.
Some practitioners have proposed a schmitt trigger circuit (chinese patent application 201710190467.0), which includes an inverter circuit composed of MOS transistors, a first feedback circuit, and a first inverter; the inverter circuit is used for determining the negative threshold voltage of the trigger through the overturning voltage of the inverter circuit; the feedback circuit is used for changing the forward threshold voltage by changing the width-to-length ratio of the MOS tube; the first inverter is used for shaping the output signal of the inverter circuit. The Schmitt trigger circuit realizes the change of the threshold voltage of the trigger by changing the width-length ratio of the MOS tube, can only change the threshold voltage when the Schmitt trigger circuit is designed, and cannot dynamically adjust the positive or negative threshold voltage when the circuit works after being manufactured.
However, with the development of integrated circuits, application scenarios such as wide voltage control and the like desire that the forward threshold voltage of the schmitt trigger at the input port of the integrated circuit is adjustable. Obviously, the structure of the existing Schmitt trigger is complex, and the adjusting effect cannot really meet the actual requirement.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the Schmitt trigger with the adjustable forward threshold voltage, which has the advantages of simple structure, low cost, simple and convenient manufacture and wide application range.
In order to solve the technical problems, the invention adopts the following technical scheme:
a Schmitt trigger with adjustable forward threshold voltage comprises a PMOS transistor group, a first NMOS transistor and an inverter; the input ports of the first PMOS transistor and the first NMOS transistor are input signals IN, and the input port of the third PMOS transistor is a forward threshold voltage adjusting signal ADP; the output ports of the PMOS transistor group and the first NMOS transistor are output signals OUT. The drain electrode of the PMOS transistor group is connected with the drain electrode of the first NMOS transistor and the input end of the phase inverter, the source electrode and the body of the PMOS transistor group are connected with a power supply VDD, and the grid electrode of the PMOS transistor group is connected with an input signal IN.
As a further improvement of the invention: the PMOS transistor group comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor.
As a further improvement of the invention: the structure of the PMOS transistor group comprises:
the drain electrode of the first PMOS transistor is connected with the drain electrode of the first NMOS transistor, the drain electrode of the second PMOS transistor and the input end of the inverter, the source electrode and the body are connected with a power supply VDD, and the grid electrode is connected with an input signal IN.
The drain electrode of the second PMOS transistor is connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor and the input end of the phase inverter, the source electrode of the second PMOS transistor is connected with the drain electrode of the third PMOS transistor, the body of the second PMOS transistor is connected with a power supply VDD, and the grid electrode of the second PMOS transistor is connected with the output end of the phase inverter.
The drain electrode of the third PMOS transistor is connected with the source electrode of the second PMOS transistor, the source electrode and the body are connected with a power supply VDD, and the grid electrode of the third PMOS transistor is connected with a forward threshold voltage adjusting signal ADP.
As a further improvement of the invention: the drain electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, the drain electrode of the second PMOS transistor and the input end of the inverter, the source electrode of the first NMOS transistor is connected with the ground GND, and the grid electrode of the first NMOS transistor is connected with the input signal IN.
As a further improvement of the invention: the input end of the phase inverter is connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor and the drain electrode of the second PMOS transistor, and the output end of the phase inverter is connected with the output signal OUT.
As a further improvement of the invention: the inverter circuit comprises a fourth PMOS transistor and a second NMOS transistor, wherein the source electrode and the body of the fourth PMOS transistor are connected with a power supply VDD, the drain electrode of the fourth PMOS transistor is connected with the drain electrode and the output end OUT of the second NMOS transistor, and the grid electrode of the fourth PMOS transistor is connected with the input end IN. The source and the body of the second NMOS transistor are connected with the ground GND, the drain of the second NMOS transistor is connected with the drain of the fourth PMOS transistor and the output end OUT, and the gate of the second NMOS transistor is connected with the input end IN.
Compared with the prior art, the invention has the advantages that:
the Schmitt trigger with the adjustable forward threshold voltage has the advantages of simple structure, low cost and simple and convenient manufacture, and can provide the function of adjusting the forward threshold voltage, namely the forward threshold voltage can be changed by adjusting the voltage of a forward threshold voltage adjusting signal ADP. Therefore, the application range of the Schmitt trigger is greatly expanded, and the Schmitt trigger can meet different application requirements of various fields.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of a conventional schmitt trigger.
Fig. 2 is a schematic diagram illustrating the operation of a conventional schmitt trigger.
Fig. 3 is a schematic diagram of a circuit structure of a schmitt trigger in a specific application example.
FIG. 4 is a schematic diagram of a circuit structure of an inverter according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating the forward threshold voltage adjustment signal ADP is 0V in an embodiment of the present invention.
FIG. 6 is a diagram illustrating the forward threshold voltage adjustment signal ADP of 0.4V in an exemplary embodiment of the present invention.
FIG. 7 is a diagram illustrating the forward threshold voltage adjusting signal ADP of 1.2V in an exemplary embodiment of the present invention.
In fig. 3-7: 1 a first PMOS transistor, 2 a first NMOS transistor, 3 a third PMOS transistor, 4 a second PMOS transistor, 5 an inverter, 6 a fourth PMOS transistor, 7 a second NMOS transistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in fig. 3-7, a forward threshold voltage adjustable schmitt trigger of the present invention comprises a PMOS transistor set, a first NMOS transistor 2 and an inverter 5; the input ports of the first PMOS transistor 1 and the first NMOS transistor 2 are input signals IN, and the input port of the third PMOS transistor 3 is a forward threshold voltage adjustment signal ADP; the output ports of the PMOS transistor group and the first NMOS transistor 2 are output signals OUT; the drain electrode of the PMOS transistor group is connected with the drain electrode of the first NMOS transistor 2 and the input end of the phase inverter 5, the source electrode and the body of the PMOS transistor group are connected with a power supply VDD, and the grid electrode of the PMOS transistor group is connected with an input signal IN; the drain of the first NMOS transistor 2 is connected to the drain of the PMOS transistor group and the input terminal of the inverter 5, the source and the bulk are connected to ground GND, and the gate is connected to the input signal IN.
In a specific application example, the PMOS transistor group includes a first PMOS transistor 1, a second PMOS transistor 4, and a third PMOS transistor 3.
In a specific application example, the detailed structure of the invention comprises:
the drain of the first PMOS transistor 1 is connected to the drain of the first NMOS transistor 2, the drain of the second PMOS transistor 4, and the input terminal of the inverter 5, the source and bulk of which are connected to the power supply VDD, and the gate of which is connected to the input signal IN.
The drain of the first NMOS transistor 2 is connected to the drain of the first PMOS transistor 1, the drain of the second PMOS transistor 4, and the input terminal of the inverter 5, the source and the bulk are connected to ground GND, and the gate is connected to the input signal IN.
The drain of the second PMOS transistor 4 is connected to the drain of the first PMOS transistor 1, the drain of the first NMOS transistor 2, and the input terminal of the inverter 5, the source is connected to the drain of the third PMOS transistor 3, the bulk is connected to the power supply VDD, and the gate is connected to the output terminal of the inverter 5.
The drain of the third PMOS transistor 3 is connected to the source of the second PMOS transistor 4, the source and bulk are connected to the power supply VDD, and the gate is connected to the forward threshold voltage adjustment signal ADP.
It is understood that other embodiments employing PMOS transistor group structures are also within the scope of the present invention.
The input end of the inverter 5 is connected with the drain of the first PMOS transistor 1, the drain of the first NMOS transistor 2 and the drain of the second PMOS transistor 4, and the output end is connected with the output signal OUT.
IN a preferred embodiment, as shown IN fig. 4, the present invention further optimizes the inverter 5 circuit, the inverter 5 circuit comprises a fourth PMOS transistor 6 and a second NMOS transistor 7, wherein the source and the bulk of the fourth PMOS transistor 6 are connected to the power VDD, the drain of the fourth PMOS transistor 6 is connected to the drain of the second NMOS transistor 7 and the output OUT, and the gate of the fourth PMOS transistor 6 is connected to the input IN. The source and the bulk of the second NMOS transistor 7 are connected to ground GND, the drain of the second NMOS transistor 7 is connected to the drain of the fourth PMOS transistor 6 and to the output OUT, and the gate of the second NMOS transistor 7 is connected to the input IN.
The invention is a specific application example to illustrate the working principle of the structure.
For a circuit of the present invention implemented IN a certain process, when the positive threshold voltage adjustment signal ADP is 0V, the positive threshold voltage is 0.9V, and the negative threshold voltage is 0.46V, as shown IN fig. 5, where I is an IN voltage and II is an OUT voltage.
When the positive threshold voltage adjusting signal ADP is 0.4V, the positive threshold voltage becomes 0.85V, and the negative threshold voltage is still 0.46V, as shown IN fig. 6, I is IN voltage and II is OUT voltage.
When the positive threshold voltage adjusting signal ADP is 1.2V, the positive threshold voltage becomes 0.78V, and the negative threshold voltage is still 0.46V, as shown IN fig. 7, I is IN voltage and II is OUT voltage.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (3)

1. A Schmitt trigger with adjustable forward threshold voltage comprises a PMOS transistor group, a first NMOS transistor (2) and an inverter (5); the PMOS transistor group comprises a first PMOS transistor (1), a second PMOS transistor (4) and a third PMOS transistor (3);
the drain electrode of the first PMOS transistor (1) is connected with the drain electrode of the first NMOS transistor (2), the drain electrode of the second PMOS transistor (4) and the input end of the inverter (5), the source electrode and the body of the first PMOS transistor (1) are connected with a power supply VDD, and the grid electrode of the first PMOS transistor is connected with an input signal IN;
the drain electrode of the second PMOS transistor (4) is connected with the drain electrode of the first PMOS transistor (1), the drain electrode of the first NMOS transistor (2) and the input end of the inverter (5), the source electrode of the second PMOS transistor (4) is connected with the drain electrode of the third PMOS transistor (3) and is connected with a power supply VDD, and the grid electrode of the second PMOS transistor (4) is connected with the output end of the inverter (5);
the drain electrode of the third PMOS transistor (3) is connected with the source electrode of the second PMOS transistor (4), the source electrode of the third PMOS transistor (3) is connected with a power supply VDD in a bulk mode, and the grid electrode of the third PMOS transistor (3) is connected with a forward threshold voltage adjusting signal ADP.
2. The schmitt trigger according to claim 1, characterized in that: the input end of the phase inverter (5) is connected with the drain electrode of the first PMOS transistor (1), the drain electrode of the first NMOS transistor (2) and the drain electrode of the second PMOS transistor (4), and the output end of the phase inverter is connected with the output signal OUT.
3. The schmitt trigger according to claim 2, characterized in that: the inverter (5) circuit comprises a fourth PMOS transistor (6) and a second NMOS transistor (7), wherein the source electrode of the fourth PMOS transistor (6) is connected with a power supply VDD through a body, the drain electrode of the fourth PMOS transistor (6) is connected with the drain electrode of the second NMOS transistor (7) and an output end OUT, the gate electrode of the fourth PMOS transistor (6) is connected with an input end IN, the source electrode of the second NMOS transistor (7) is connected with a ground GND through the body, the drain electrode of the second NMOS transistor (7) is connected with the drain electrode of the fourth PMOS transistor (6) and the output end OUT, and the gate electrode of the second NMOS transistor (7) is connected with the input end IN.
CN202110710441.0A 2021-06-25 2021-06-25 Schmitt trigger with adjustable forward threshold voltage Pending CN113381737A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080309384A1 (en) * 2007-06-13 2008-12-18 Honeywell International Inc. Initialization Circuitry Having Fuse Leakage Current Tolerance
CN103368532A (en) * 2013-07-09 2013-10-23 华东师范大学 Hysteretic voltage digital adjustable Schmitt trigger
CN103607184A (en) * 2013-10-23 2014-02-26 上海华力微电子有限公司 CMOS Schmidt trigger circuit
CN105680829A (en) * 2015-12-31 2016-06-15 峰岹科技（深圳）有限公司 Schmitt trigger circuit
CN108183699A (en) * 2017-12-29 2018-06-19 芯原微电子(上海)有限公司 The method for triggering the adjustable Schmidt trigger of window and its adjusting triggering window
CN108667440A (en) * 2017-03-28 2018-10-16 峰岹科技（深圳）有限公司 A kind of Schmitt trigger circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080309384A1 (en) * 2007-06-13 2008-12-18 Honeywell International Inc. Initialization Circuitry Having Fuse Leakage Current Tolerance
CN103368532A (en) * 2013-07-09 2013-10-23 华东师范大学 Hysteretic voltage digital adjustable Schmitt trigger
CN103607184A (en) * 2013-10-23 2014-02-26 上海华力微电子有限公司 CMOS Schmidt trigger circuit
CN105680829A (en) * 2015-12-31 2016-06-15 峰岹科技（深圳）有限公司 Schmitt trigger circuit
CN108667440A (en) * 2017-03-28 2018-10-16 峰岹科技（深圳）有限公司 A kind of Schmitt trigger circuit
CN108183699A (en) * 2017-12-29 2018-06-19 芯原微电子(上海)有限公司 The method for triggering the adjustable Schmidt trigger of window and its adjusting triggering window

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