CN113362769A

CN113362769A - Pixel circuit, gate drive circuit and display panel

Info

Publication number: CN113362769A
Application number: CN202110713033.0A
Authority: CN
Inventors: 盖翠丽; 李俊峰; 王玲
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2021-09-07

Abstract

The embodiment of the invention discloses a pixel circuit, a grid drive circuit and a display panel. The pixel circuit comprises a leakage current suppression module, wherein the leakage current suppression module is used for responding to a second light-emitting control signal, disconnecting a current path between the control end of the driving module and the grid initialization module, and disconnecting the current path between the control end of the driving module and the data writing module. The channel type of the transistor in the leakage current suppression module is the same as that of the transistor in the light emission control module, and the first light emission control signal and the second light emission control signal are opposite in level. Compared with the prior art, the embodiment of the invention improves the electric leakage problem of the pixel circuit, improves the driving performance of the pixel circuit and improves the user experience.

Description

Pixel circuit, gate drive circuit and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a gate driving circuit and a display panel.

Background

With the continuous development of display technologies, the application range of display panels is wider and wider, and the image quality requirements of people on display panels are higher and higher. Self-luminous display panels such as AMOLED display panels emit light by current driving, and the driving circuit is a pixel circuit. The gate-source voltage difference of the driving transistor in the pixel circuit determines the magnitude of the current flowing through the driving transistor, i.e., the magnitude of the current flowing through the light emitting device. However, the existing pixel circuit has defects, and particularly under the condition of low refresh frequency, the display brightness of the light emitting device is obviously reduced due to the electric leakage problem of the pixel circuit, so that the display panel generates the problem of flicker, and the user experience is influenced.

Disclosure of Invention

The embodiment of the invention provides a pixel circuit, a gate drive circuit and a display panel, which are used for improving the electric leakage problem of the pixel circuit, improving the drive performance of the pixel circuit and improving the user experience.

In order to achieve the technical purpose, the embodiment of the invention provides the following technical scheme:

a pixel circuit, comprising:

the driving module is used for responding to the voltage of the control end of the driving module to generate driving current;

the grid initialization module is used for responding to a first scanning signal and initializing the control end of the driving module;

the data writing module is used for responding to a second scanning signal and writing a data signal into the control end of the driving module;

the light-emitting control module is used for responding to the first light-emitting control signal and conducting a current path between the driving module and the light-emitting device;

the leakage current suppression module is used for responding to a second light-emitting control signal, disconnecting a current path between the control end of the driving module and the grid initialization module and disconnecting a current path between the control end of the driving module and the data writing module;

the channel type of the transistor in the leakage current suppression module is the same as that of the transistor in the light emission control module, and the first light emission control signal and the second light emission control signal are opposite in level.

Optionally, the leakage current suppression module includes a control end, a first end and a second end, the control end of the leakage current suppression module is connected to the second light-emitting control signal, and the first end of the leakage current suppression module is electrically connected to the control end of the driving module;

the drive module further comprises a first end and a second end; the data writing module comprises a first end, a second end, a third end, a fourth end and a fifth end, the fifth end of the data writing module is connected with the second scanning signal, the first end of the data writing module is connected with the data signal, the second end of the data writing module is electrically connected with the first end of the driving module, the third end of the data writing module is electrically connected with the second end of the driving module, and the fourth end of the data writing module is electrically connected with the second end of the leakage current suppression module;

preferably, the gate initialization module includes a control end, a first end and a second end, the control end of the gate initialization module is connected to the first scanning signal, the first end of the gate initialization module is connected to the initialization signal, and the second end of the gate initialization module is electrically connected to the second end of the leakage current suppression module;

preferably, the gate initialization module includes a first transistor, a gate of the first transistor is used as a control terminal of the gate initialization module, a first pole of the first transistor is used as a first terminal of the gate initialization module, and a second pole of the first transistor is used as a second terminal of the gate initialization module;

the data writing module comprises a second transistor and a third transistor, wherein a grid electrode of the second transistor is electrically connected with a grid electrode of the third transistor and is used as a fifth end of the data writing module, a first pole of the second transistor is used as a fourth end of the data writing module, a second pole of the second transistor is used as a third end of the data writing module, a first pole of the third transistor is used as a second end of the data writing module, and a second pole of the third transistor is used as a first end of the data writing module;

the leakage current suppression module comprises a fourth transistor, a grid electrode of the fourth transistor is used as a control end of the leakage current suppression module, a first pole of the fourth transistor is used as a first end of the leakage current suppression module, and a second pole of the fourth transistor is used as a second end of the leakage current suppression module.

Optionally, the leakage current suppression module includes a control end, a first end and a second end, the control end of the leakage current suppression module is connected to the second light emission control module, and the first end of the leakage current suppression module is electrically connected to the control end of the driving module;

the drive module further comprises a first end and a second end; the data writing module comprises a first end, a second end and a fifth end, the fifth end of the data writing module is connected with the second scanning signal, the first end of the data writing module is connected with the data signal, and the second end of the data writing module is electrically connected with the first end of the driving module; the second end of the driving module is electrically connected with the second end of the leakage current suppression module;

the grid initialization module comprises a control end, a first end and a second end, the control end of the grid initialization module is connected to the first scanning signal, the first end of the grid initialization module is connected to the initialization signal, and the second end of the grid initialization module is electrically connected with the second end of the leakage current suppression module;

the data writing module comprises a third transistor, wherein the grid electrode of the third transistor is used as the fifth end of the data writing module, the first pole of the third transistor is used as the second end of the data writing module, and the second pole of the third transistor is used as the first end of the data writing module;

Optionally, the transistor in the gate initialization module is a double-gate transistor; the transistor electrically connected with the control end of the driving module in the data writing module is a double-gate transistor;

preferably, transistors in the driving module, the gate initialization module, the data writing module and the drain current suppression module are all P-type transistors or all N-type transistors.

Optionally, the lighting control module includes a first end, a second end, a third end, a fourth end and a fifth end, the fifth end of the lighting control module is connected to the first lighting control signal, the first end of the lighting control module is connected to the first power signal, the second end of the lighting control module is electrically connected to the first end of the driving module, the third end of the lighting control module is electrically connected to the second end of the driving module, and the fourth end of the lighting control module is electrically connected to the light emitting device;

preferably, the light emitting control module comprises a fifth transistor and a sixth transistor, and a gate of the fifth transistor is electrically connected to a gate of the sixth transistor and serves as a fifth terminal of the light emitting control module; a first pole of the fifth transistor is used as a first end of the light emitting control module, a second pole of the fifth transistor is used as a second end of the light emitting control module, a first pole of the sixth transistor is used as a third end of the light emitting control module, and a second pole of the sixth transistor is used as a fourth end of the light emitting control module;

preferably, the driving module comprises a driving transistor, a gate of the driving transistor is used as a control terminal of the driving module, a first pole of the driving transistor is used as a first terminal of the driving module, and a second pole of the driving module is used as a second terminal of the driving module;

preferably, the pixel circuit further includes a storage module, the storage module includes a first end and a second end, the first end of the storage module is connected to the first power signal, and the second end of the storage module is electrically connected to the control end of the driving module;

preferably, the memory module comprises a storage capacitor, a first pole of the storage capacitor is used as a first end of the memory module, and a second pole of the storage capacitor is used as a second end of the memory module;

preferably, the pixel circuit further comprises an anode initialization module, the anode initialization module comprises a control terminal, a first terminal and a second terminal, the control terminal of the anode initialization module is connected to the first scanning signal or the second scanning signal, the first terminal of the anode initialization module is connected to an initialization signal, and the second terminal of the anode initialization module is electrically connected to the anode of the light emitting device;

preferably, the anode initialization module includes a seventh transistor, a gate of the seventh transistor is used as the control terminal of the anode initialization module, a first pole of the seventh transistor is used as the first terminal of the anode initialization module, and a second pole of the seventh transistor is used as the second terminal of the anode initialization module.

Accordingly, the present invention also provides a gate driving circuit for providing the first light emission control signal and the second light emission control signal to the pixel circuit according to any embodiment of the present invention, the gate driving circuit including:

the first input module is used for responding to a first clock signal and transmitting the first luminous control signal of the preceding stage to the output end of the first input module;

the second input module is used for responding to the first clock signal and transmitting the preceding-stage second light-emitting control signal to the output end of the second input module;

the first bootstrap and output module comprises an output end, and the output end of the first bootstrap and output module outputs the second light-emitting control signal of the current stage; the first bootstrap and output module is configured to respond to a signal at an output end of the second input module, output a first level signal at an output end of the first bootstrap and output module, perform bootstrap coupling in response to the output first level signal and a second clock signal, and maintain output of the first level signal; the first bootstrap and output module is used for responding to the signal of the output end of the first input module and outputting a second level signal at the output end of the first bootstrap and output module;

the second bootstrap and output module comprises an output end, and the output end of the second bootstrap and output module outputs the first luminous control signal of the current stage; the second bootstrap and output module is configured to respond to a signal at an output end of the first input module, output the first level signal at an output end of the second bootstrap and output the first level signal, perform bootstrap coupling in response to the output first level signal and the second clock signal, and maintain output of the first level signal; and the second bootstrap and output module is used for controlling the output end of the second bootstrap and output module to output the second level signal when the second light-emitting control signal of the current level is the first level signal.

Optionally, the first bootstrap and output module further includes a first end, a second end, a third end, a fourth end and a fifth end, the first end of the first bootstrap and output module is electrically connected to the output end of the first input module, the second end of the first bootstrap and output module is electrically connected to the output end of the second input module, the third end of the first bootstrap and output module is connected to the first level signal, the fourth end of the first bootstrap and output module is connected to the second level signal, and the fifth end of the first bootstrap and output module is connected to the second clock signal;

preferably, the first bootstrap and output module includes:

the first bootstrap unit comprises a first end, a second end, a third end and a fourth end, the first end of the first bootstrap unit is electrically connected with the output end of the first input module, the second end of the first bootstrap unit is connected to the second level signal, the third end of the first bootstrap unit is electrically connected with the output end of the second input module, and the fourth end of the first bootstrap unit is connected to the second clock signal; the first bootstrap unit is used for responding to the second clock signal to carry out bootstrap coupling;

the first transmission unit comprises an input end and an output end, and the input end of the first transmission unit is electrically connected with the output end of the second input module; the first transmission unit is used for transmitting a signal at the output end of the second input module;

a second bootstrap unit, including a first end, a second end, a third end, a fourth end and an output end, where the first end of the second bootstrap unit is electrically connected to the output end of the first input module, the second end of the second bootstrap unit is connected to the second level signal, the third end of the second bootstrap unit is electrically connected to the output end of the first transmission unit, the fourth end of the second bootstrap unit is connected to the first level signal, and the output end of the second bootstrap unit is used as the output end of the first bootstrap and output module; the second bootstrap unit is configured to respond to a signal at an output end of the first transmission unit, output the first level signal at an output end of the second bootstrap unit, and perform bootstrap coupling in response to the output first level signal; and, responding to the signal at the output of the first input module, outputting the second level signal at its output;

preferably, the first bootstrap unit includes:

a gate of the eighth transistor is electrically connected with the output end of the first input module, and a first pole of the eighth transistor is connected to the second level signal;

a ninth transistor, a gate of which is electrically connected to the output terminal of the second input module, a first pole of which is connected to the second clock signal, and a second pole of which is electrically connected to the second pole of the eighth transistor;

a first capacitor connected between the gate and the second pole of the ninth transistor;

preferably, the first transmission unit includes a tenth transistor, a gate of the tenth transistor is electrically connected to the first pole and serves as an input terminal of the first transmission unit, and a second pole of the tenth transistor serves as an output terminal of the first transmission unit;

preferably, the second bootstrap unit includes:

a gate of the eleventh transistor is electrically connected to the output end of the first transmission unit, a first pole of the eleventh transistor is connected to the first level signal, and a second pole of the eleventh transistor serves as the output end of the second bootstrap unit;

a twelfth transistor, a gate of which is electrically connected to the output terminal of the first input module, a first pole of which is connected to the second level signal, and a second pole of which is electrically connected to the output terminal of the first transmission unit;

a thirteenth transistor, a gate of which is electrically connected to the output terminal of the first input module, a first pole of which is connected to the second level signal, and a second pole of which is electrically connected to the second pole of the eleventh transistor;

a second capacitor connected between the gate and the second pole of the eleventh transistor.

Optionally, the second bootstrap and output module further includes a first end, a second end, a third end, a fourth end, and a fifth end, the first end of the second bootstrap and output module is electrically connected to the output end of the first bootstrap and output module, the second end of the second bootstrap and output module is electrically connected to the output end of the first input module, the third end of the second bootstrap and output module is connected to the first level signal, the fourth end of the second bootstrap and output module is connected to the second level signal, and the fifth end of the second bootstrap and output module is connected to the second clock signal;

preferably, the second bootstrap and output module includes:

a third bootstrap unit, including a first end, a second end, a third end and a fourth end, where the first end of the third bootstrap unit is electrically connected to the output end of the first input module, the second end of the third bootstrap unit is electrically connected to the output end of the second input module, the third end of the third bootstrap unit is connected to the second level signal, and the fourth end of the third bootstrap unit is connected to the second clock signal; the third bootstrap unit is configured to perform bootstrap coupling in response to the second clock signal;

the second transmission unit comprises an input end and an output end, and the input end of the second transmission unit is electrically connected with the output end of the first input module; the second transmission unit is used for transmitting the signal of the output end of the first input module;

a fourth self-lifting unit, including a first end, a second end, a third end, a fourth end, a fifth end and an output end, where the first end of the fourth self-lifting unit is electrically connected to the output end of the first bootstrap and output module, the second end of the fourth self-lifting unit is connected to the second level signal, the third end of the fourth self-lifting unit is electrically connected to the output end of the second transmission unit, the fourth end of the fourth self-lifting unit is connected to the first level signal, the fifth end of the fourth self-lifting unit is electrically connected to the output end of the second input module, and the output end of the fourth self-lifting unit serves as the output end of the second bootstrap and output module; the fourth self-lifting unit is used for responding to the signal at the output end of the second transmission unit, outputting the first level signal at the output end of the fourth self-lifting unit, and performing bootstrap coupling in response to the output first level signal; the fourth self-lifting unit is used for controlling the output end of the fourth self-lifting unit to output the second level signal when the second light-emitting control signal of the current stage is the first level signal;

preferably, the third bootstrap unit includes:

a gate of the fourteenth transistor is electrically connected with the output end of the first input module, and a first pole of the fourteenth transistor is connected to the second clock signal;

a fifteenth transistor, a gate of which is electrically connected to the output terminal of the second input module, a first pole of which is connected to the second level signal, and a second pole of which is electrically connected to the second pole of the fourteenth transistor;

a third capacitor connected between the gate and the second pole of the fourteenth transistor;

preferably, the second transmission unit includes a sixteenth transistor, a gate of the sixteenth transistor is electrically connected to the first pole and serves as an input terminal of the second transmission unit, and a second pole of the sixteenth transistor serves as an output terminal of the second transmission unit;

preferably, the fourth self-lifting unit comprises:

a seventeenth transistor, a gate of which is electrically connected to the output terminal of the second transmission unit, and a first pole of which is connected to the first level signal;

a gate of the eighteenth transistor is electrically connected to the output end of the first bootstrap and output module, a first pole of the eighteenth transistor is connected to the second level signal, and a second pole of the eighteenth transistor is electrically connected to the second pole of the seventeenth transistor and serves as the output end of the fourth self-lifting unit;

a nineteenth transistor, a gate of which is electrically connected to the output terminal of the second input module, a first pole of which is connected to the second level signal, and a second pole of which is electrically connected to the output terminal of the second transmission unit;

a fourth capacitor connected between the gate and the second pole of the seventeenth transistor.

Optionally, the gate driving circuit further comprises:

the first isolating module is connected between the second input module and the first bootstrap and output module and used for isolating the transmission of the level signal in the first bootstrap and output module to the second input module;

the second isolating module is connected between the first input module and the second bootstrap and output module and used for isolating the transmission of the level signal in the second bootstrap and output module to the first input module;

preferably, the first blocking module comprises a twentieth transistor, a gate of the twentieth transistor is connected to the first level signal, a first pole of the twentieth transistor is electrically connected to the first bootstrap and output module, and a second pole of the twentieth transistor is electrically connected to the second input module;

the second partition module comprises a twenty-first transistor, the grid electrode of the twenty-first transistor is connected to the first level signal, the first pole of the twenty-first transistor is electrically connected with the second bootstrap and output module, and the second pole of the twenty-first transistor is electrically connected with the first input module;

preferably, the first input module includes a twenty-second transistor, a gate of the twenty-second transistor is connected to the first clock signal, a first pole of the twenty-second transistor is connected to the previous stage of the first lighting control signal, and a second pole of the twenty-second transistor is electrically connected to the second blocking module;

the second input module comprises a twenty-third transistor, a gate of the twenty-third transistor is connected to the first clock signal, a first pole of the twenty-third transistor is connected to the preceding stage of the second light-emitting control signal, and a second pole of the twenty-third transistor is electrically connected to the first partition module.

Correspondingly, the invention further provides a display panel, which comprises a plurality of cascade-connected gate driving circuits according to any embodiment of the invention, and a plurality of pixel circuits according to any embodiment of the invention arranged in an array.

In the embodiment of the invention, the drain current suppression module controlled by the second light-emitting control signal is added in the pixel circuit, the channel type of the transistor in the drain current suppression module is the same as that of the transistor in the light-emitting control module, and the level of the second light-emitting control signal is opposite to that of the first light-emitting control signal. And the leakage current suppression module is arranged between the grid initialization module and the grid, and is arranged between the data writing module and the grid. Equivalently, a leakage current suppression module is added on a branch where the gate initialization module is located and a branch where the data writing module is located, so that the structure of the pixel circuit is simplified. Meanwhile, the leakage current suppression module provided by the embodiment of the invention can simultaneously suppress the leakage current problem brought by the grid initialization module and the data writing module in the light-emitting stage on the basis of not influencing the normal work of the grid initialization module and the data writing module, and the problems of obvious reduction of the display brightness of a light-emitting device and flicker of a display panel under the condition of low refreshing frequency are improved. Therefore, the embodiment of the invention improves the driving performance of the pixel circuit and improves the user experience. In addition, the transistors in each module can be set to be transistors with the same channel type, for example, all the transistors are P-type transistors, so that the preparation process is simplified, the practicability is high, and the implementation is easy.

Drawings

Fig. 1 is a schematic structural diagram of a conventional pixel circuit;

FIG. 2 is an equivalent diagram of the gate connection of the driving transistor in the light-emitting stage of FIG. 1;

fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of the pixel circuit of FIG. 4;

FIG. 6 is an equivalent diagram of the gate connection of the driving transistor in the light-emitting stage of FIG. 4;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 8 is an equivalent diagram of the gate connection of the driving transistor in the light-emitting stage of FIG. 7;

fig. 9 is a diagram illustrating a simulation result of a gate leakage effect of a driving transistor according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention;

fig. 11 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 12 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention;

fig. 13 is a timing diagram of a gate driving circuit according to an embodiment of the invention;

fig. 14-17 are schematic diagrams illustrating switching states of a gate driving circuit at various stages according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional pixel circuit has a leakage problem, and particularly, the display brightness of the light emitting device is obviously reduced due to the leakage problem under a low refresh frequency, so that the display panel flickers, and user experience is affected. The inventor researches and finds that the reason of the problem is as follows:

fig. 1 is a schematic structural diagram of a conventional pixel circuit. Referring to fig. 1, connected to the gate G of the driving transistor DTFT are a first transistor T1 and a second transistor T2. In the light emitting period, the driving transistor DTFT generates a driving current in response to the potential of the gate electrode G. At this stage, the first transistor T1 and the second transistor T2 are in an off-phase. However, based on the conventional manufacturing process, the first transistor T1 and the second transistor T2 have leakage current, and the equivalent circuit thereof is a resistor, not an open circuit. Fig. 2 is an equivalent diagram of the gate connection relationship of the driving transistor in the light emitting stage of fig. 1. Referring to fig. 2, each of the first transistor T1 and the second transistor T2 is equivalent to a resistor having a resistance value R. That is, the equivalent resistance value between the gate G of the driving transistor DTFT and the initialization signal Vini is R, and the equivalent resistance value between the gate G and the node Na is R. Since the first transistor T1 and the second transistor T2 have leakage currents, the potential of the gate G is affected, so that the voltage of the gate G is lowered. Particularly, in the case of a low refresh frequency, as the light emitting time is prolonged, the voltage of the gate G is reduced significantly, and the driving current generated by the driving transistor DTFT is reduced, which affects the current flowing through the light emitting device OLED, so that the display luminance of the light emitting device OLED is reduced, thereby causing a problem of flicker of the display panel.

In view of this, embodiments of the present invention provide a pixel circuit to reduce the leakage of the gate G, improve the driving performance of the pixel circuit, and improve the user experience. Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 3, the pixel circuit includes: the driving module 110, the gate initializing module 120, the data writing module 130, the light emitting control module 140, and the leakage current suppressing module 150. The driving module 110 is used for generating a driving current in response to a voltage of a control terminal (gate G) thereof. The gate initialization module 120 is configured to initialize the control terminal (gate G) of the driving module 110 in response to the first scan signal S1. The Data writing module 130 is used for writing the Data signal Data into the control terminal (gate G) of the driving module 110 in response to the second scan signal S2. The light emission control module 140 is configured to conduct a current path between the driving module 110 and the light emitting device OLED in response to the first light emission control signal EMS. The leakage current suppressing module 150 is configured to disconnect a current path between the control terminal of the driving module 110 and the gate initialization module 120 and disconnect a current path between the control terminal of the driving module 110 and the data writing module 130 in response to the second light emitting control signal EMSB.

Wherein the channel type of the transistor in the drain current suppressing module 150 is the same as the channel type of the transistor in the light emitting control module 140, and the levels of the first and second light emitting control signals EMS and EMSB are opposite.

Illustratively, if the transistors in the lighting control module 140 are P-type transistors, the transistors in the leakage current suppression module 150 are also P-type transistors. In the initialization stage, the data writing and threshold voltage compensation stage, the first light emission control signal EMS is at a high level, and controls the light emission control module 140 to be turned off; the second emission control signal EMSB is at a low level, the leakage current suppressing module 150 is controlled to be turned on, and the initialization signal Vini can initialize the gate G. In the light emitting stage, the first light emitting control signal EMS is at a low level, and controls the light emitting control module 140 to be turned on; the second emission control signal EMSB is high, and controls the leakage current suppressing module 150 to turn off to disconnect the current path between the gate G and the gate initializing module 120 and the current path between the gate G and the data writing module 130.

Illustratively, if the transistors in the lighting control module 140 are N-type transistors, the transistors in the leakage current suppression module 150 are also N-type transistors. In the initialization stage, the data writing and threshold voltage compensation stage, the first light emission control signal EMS is at a low level, and controls the light emission control module 140 to be turned off; the second emission control signal EMSB is at a high level, the leakage current suppressing module 150 is controlled to be turned on, and the initialization signal Vini can initialize the gate G. In the light emitting stage, the first light emitting control signal EMS is at a high level, and controls the light emitting control module 140 to be turned on; the second emission control signal EMSB is low, and controls the leakage current suppressing module 150 to turn off to disconnect the current path between the gate G and the gate initializing module 120 and the current path between the gate G and the data writing module 130.

It can be seen that the embodiment of the present invention adds the leakage current suppressing module 150 controlled by the second emission control signal EMSB to the pixel circuit, and the connection position of the leakage current suppressing module is disposed between the gate initializing module 120 and the gate G and between the data writing module 130 and the gate G. Equivalently, a leakage current suppression module 150 is added to both the branch where the gate initialization module 120 is located and the branch where the data writing module 130 is located, so that the structure of the pixel circuit is simplified. Meanwhile, the leakage current suppression module 150 provided by the embodiment of the present invention can suppress the leakage current caused by the gate initialization module 120 and the data write module 130 at the same time in the light emitting stage without affecting the normal operation of the gate initialization module 120 and the data write module 130, thereby improving the problems of significant reduction of the display brightness of the light emitting device and flicker of the display panel under the condition of low refresh frequency. Therefore, the embodiment of the invention improves the driving performance of the pixel circuit and improves the user experience. And the transistors in each module can be set as transistors with the same channel type, for example, all the transistors are P-type transistors, so that the preparation process is simplified, the practicability is high, and the implementation is easy.

Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 4, on the basis of the foregoing embodiments, optionally, the leakage current suppressing module 150 includes a control terminal, a first terminal and a second terminal, the control terminal of the leakage current suppressing module 150 is connected to the second light-emitting control signal EMSB, and the first terminal of the leakage current suppressing module 150 is electrically connected to the control terminal (gate G) of the driving module 110. Illustratively, the leakage current suppressing module 150 includes a fourth transistor T4, and a gate of the fourth transistor T4 is used as a control terminal of the leakage current suppressing module 150 and is connected to the second light emitting control signal EMSB. A first electrode of the fourth transistor T4 serves as a first terminal of the leakage current suppressing module 150 and is electrically connected to the control terminal (gate G) of the driving module 110.

With reference to fig. 4, optionally, the driving module 110 further includes a first terminal and a second terminal, the first terminal of the driving module 110 is connected to the first power signal VDD, and the second terminal of the driving module 110 is a node Na. Illustratively, the driving module 110 includes a driving transistor DTFT, a gate of the driving transistor DTFT is used as a control terminal of the driving module 110, a first pole of the driving transistor DTFT is used as a first terminal of the driving module 110, and is connected to the first power signal VDD; the second pole of the driving module 110 serves as a second terminal of the driving module 110.

With reference to fig. 4, optionally, the Data writing module 130 includes a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, the fifth terminal of the Data writing module 130 is connected to the second scanning signal S2, the first terminal of the Data writing module 130 is connected to the Data signal Data, the second terminal of the Data writing module 130 is electrically connected to the first terminal of the driving module 110, the third terminal of the Data writing module 130 is electrically connected to the second terminal of the driving module 110, and the fourth terminal of the Data writing module 130 is electrically connected to the second terminal of the leakage current suppressing module 150. Illustratively, the data writing module 130 includes a second transistor T2 and a third transistor T3, and a gate of the second transistor T2 is electrically connected to a gate of the third transistor T3 and is connected to the second scan signal S2 as a fifth terminal of the data writing module 130. The first pole of the second transistor T2 serves as the fourth terminal of the data writing module 130 and is electrically connected to the second terminal of the leakage current suppressing module 150. The second pole of the second transistor T2 is electrically connected to the second terminal (node Na) of the driving module 110 as the third terminal of the data writing module 130. A first pole of the third transistor T3 is electrically connected to the first terminal of the driving module 110 as a second terminal of the data writing module 130. The second pole of the third transistor T3 is used as the first end of the Data writing module 130 to receive the Data signal Data.

With continued reference to fig. 4, optionally, the gate initialization module 120 includes a control terminal, a first terminal and a second terminal, the control terminal of the gate initialization module 120 is connected to the first scan signal S1, the first terminal of the gate initialization module 120 is connected to the initialization signal Vini, and the second terminal of the gate initialization module 120 is electrically connected to the second terminal of the leakage current suppression module 150. Illustratively, the gate initialization module 120 includes a first transistor T1, and a gate of the first transistor T1 is used as a control terminal of the gate initialization module 120 and is connected to the first scan signal S1. The first pole of the first transistor T1 is used as the first terminal of the gate initialization module 120, and is connected to the initialization signal Vini. The second pole of the first transistor T1, serving as the second terminal of the gate initialization module 120, is electrically connected to the second terminal of the leakage current suppressing module 150.

With reference to fig. 4, optionally, the light-emitting control module 140 includes a first end, a second end, a third end, a fourth end and a fifth end, the fifth end of the light-emitting control module 140 is connected to the first light-emitting control signal EMS, the first end of the light-emitting control module 140 is connected to the first power signal VDD, the second end of the light-emitting control module 140 is electrically connected to the first end of the driving module 110, the third end of the light-emitting control module 140 is electrically connected to the second end of the driving module 110, the fourth end of the light-emitting control module 140 is electrically connected to the anode a of the light-emitting device OLED, and the cathode of the light-emitting device OLED is connected to the second power signal VSS. Exemplarily, the light emitting control module 140 includes a fifth transistor T5 and a sixth transistor T6, and a gate of the fifth transistor T5 is electrically connected to a gate of the sixth transistor T6, and is used as a fifth terminal of the light emitting control module 140 to receive the first light emitting control signal EMS. A first pole of the fifth transistor T5 is used as a first terminal of the light emitting control module 140, and is connected to the first power signal VDD. A second pole of the fifth transistor T5 is connected to the first pole of the driving transistor DTFT as a second terminal of the light emission control module 140. A first pole of the sixth transistor T6 is electrically connected to the second pole of the driving transistor DTFT as a third terminal of the light emission control module 140. The second pole of the sixth transistor T6 serves as the fourth terminal of the light emission control module 140 and is electrically connected to the anode a of the light emitting device OLED.

With continued reference to fig. 4, optionally, the pixel circuit further includes a memory module 160, the memory module 160 includes a first terminal and a second terminal, the first terminal of the memory module 160 is connected to the first power signal VDD, and the second terminal of the memory module 160 is electrically connected to the control terminal (gate G) of the driving module 110. Illustratively, the storage module 160 includes a storage capacitor Cst, and a first pole of the storage capacitor Cst is used as a first terminal of the storage module 160 and is coupled to the first power signal VDD. The second pole of the storage capacitor is used as the second terminal of the memory module 160 and is electrically connected to the gate G.

With continued reference to fig. 4, optionally, the pixel circuit further includes an anode initialization module 170, the anode initialization module 170 includes a control terminal, a first terminal and a second terminal, the control terminal of the anode initialization module 170 is connected to the first scan signal S1 or the second scan signal S2, the first terminal of the anode initialization module 170 is connected to the initialization signal Vini, and the second terminal of the anode initialization module 170 is electrically connected to the anode a of the light emitting device OLED. Illustratively, the anode initialization module includes a seventh transistor T7, and a gate of the seventh transistor T7 is used as a control terminal of the anode initialization module 170 and is connected to the first scan signal S1 or the second scan signal S2. A first pole of the seventh transistor T7 serves as a first terminal of the anode initialization block 170 and receives the initialization signal Vini. The second pole of the seventh transistor T7 serves as the second terminal of the anode initialization module 170 and is electrically connected to the anode a of the light emitting device OLED.

The initialization signal Vini received by the anode initialization module 170 and the initialization signal Vini received by the gate initialization module 150 are the same initialization signal, and the scan signal received by the anode initialization module 170 is used to multiplex the first scan signal S1 or the second scan signal S2. This arrangement is advantageous in reducing the number of signal lines to simplify the structure of the pixel circuit. In other embodiments, the initialization signal received by the anode initialization module 170 may be different from the initialization signal received by the gate initialization module 150, and the scan signal received by the anode initialization module 170 may be different from the first scan signal S1 and the second scan signal S2, which may be set as required in practical applications.

FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4. Referring to fig. 4 and 5, each transistor is a P-type transistor, and is turned off by a high level driving and turned on by a low level driving, for example. The driving timing of the pixel circuit includes an initialization stage JD1, a data writing and threshold voltage compensation stage JD2 and a lighting stage JD 3.

In the initialization phase JD1, the first lighting control signal EMS is at a high level, and the fifth transistor T5 and the sixth transistor T6 are turned off; the second scan signal S2 is at a high level, and the second transistor T2 and the third transistor T3 are turned off; the second light emission control signal EMSB is at a low level, and the fourth transistor T4 is turned on; the first scan signal S1 is at a low level, the first transistor T1 is turned on, the initialization signal Vini initializes the gate G of the driving transistor DTFT through the first transistor T1, and the potential of the gate G is equal to the potential of the initialization signal Vini; at the same time, the seventh transistor T7 is turned on, and the initialization signal Vini resets the anode a of the light emitting device OLED through the seventh transistor T7, and the potential of the anode a is equal to the potential of the initialization signal Vini. At this stage, since the fourth transistor T4 is turned on under the control of the second light emission control signal EMSB, the first transistor T1 can transmit the initialization signal Vini to the gate G.

During the data writing and threshold voltage compensation stage JD2, the first light-emitting control signal EMS is still at a high level, and the fifth transistor T5 and the sixth transistor T6 are turned off; the first scan signal S1 is at a high level, the first transistor T1 and the seventh transistor T7 are turned off; the second light emission control signal EMSB is at a low level, and the fourth transistor T4 is turned on; the second scan signal S2 is at a low level, the second transistor T2 and the third transistor T3 are turned on, the Data signal Data charges the gate G and is stored in the storage capacitor Cst, and when the voltage of the gate G is Data + Vth, the driving transistor DTFT is turned off due to the off condition being satisfied, and the threshold voltage compensation and the Data writing are completed; where Vth is a threshold voltage of the driving transistor DTFT. At this stage, since the fourth transistor T4 is turned on under the control of the second light emission control signal EMSB, the third transistor T3 and the second transistor T2 can write the Data signal Data into the gate G.

In the lighting period JD3, the first scan signal S1, the second scan signal S2 and the second lighting control signal EMSB are all high, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are all turned off; the first light emission control signal EMS is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on; the magnitude of the driving current I of the driving transistor DTFT at this time is:

where Vgs is a gate-source voltage difference of the driving transistor DTFT, W is a channel width, L is a channel length, μ is an electron mobility, and Cox is a unit area channel capacitance. The threshold voltage Vth is greatly influenced by process fluctuation, and the influence of the threshold voltage Vth on the driving current I can be eliminated by compensating the threshold voltage of the driving transistor DTFT, so that the display uniformity is improved. At this stage, since the fourth transistor T4 is turned off under the control of the second emission control signal EMSB, which is equivalent to adding a large resistor between the gate G and the first transistor T1 and between the gate G and the second transistor T2, it is beneficial to suppress the generation of leakage current at the gate G through the first transistor T1 and the second transistor T2.

As can be seen from the above analysis, the fourth transistor T4 controlled by the second emission control signal EMSB is connected to the gate of the driving transistor DTFT, and the initialization signal Vini is not affected to the gate G during the initialization phase JD 1; the Data signal Data write gate G is not affected during the Data write and threshold voltage compensation phase JD 2; the drain of the gate G can be reduced during the lighting period JD 3. Therefore, the embodiment of the invention reduces the electric leakage problem of the pixel circuit and improves the driving performance of the pixel circuit on the basis of not changing the working time sequence of the pixel circuit.

With continued reference to fig. 4, based on the above embodiments, the first transistor T1 and the second transistor T2 are optionally double-gate transistors. Compared with a single-gate transistor, the double-gate transistor has the characteristic of smaller leakage current, so that the leakage current of the gate G in the light emitting stage can be further reduced by adopting the double-gate transistors in the first transistor T1 and the second transistor T2, and the driving performance of the pixel circuit is improved. If the equivalent resistance R of the single-gate transistor in the off state is larger than the equivalent resistance R of the double-gate transistor in the off state, the equivalent resistance of the double-gate transistor in the off state is smaller than 2R. Fig. 6 is an equivalent diagram of the gate connection relationship of the driving transistor in the light emitting stage of fig. 4. Referring to fig. 4 and 6, the fourth transistor T4 is equivalent to a resistor with a resistance value R during the light emitting period. The first transistor T1 and the second transistor T2 are equivalent to resistors, and have a resistance value of 2R. Therefore, the equivalent resistance value between the gate G and the initialization signal Vini is 3R, and the equivalent resistance value between the gate G and the node Na is 3R. In the embodiment of the present invention, by adding the fourth transistor T4, which is equal to adding an equivalent resistor R in both the two branches, the leakage current of the two branches can be reduced at the same time.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention, and fig. 8 is an equivalent schematic diagram of a gate connection relationship of a driving transistor when the pixel circuit of fig. 7 operates in a light-emitting stage. Referring to fig. 7 and 8, unlike the above-described embodiment, the first transistor T1 and the second transistor T2 are single-gate transistors, and the fourth transistor T4 is a double-gate transistor. In the light emitting period, the fourth transistor T4 is equivalent to a resistor with a resistance value of 2R. The first transistor T1 and the second transistor T2 are equivalent to resistors, and have a resistance value R. Compared with fig. 4, the pixel circuit shown in fig. 7 has the same effect of reducing the leakage, only one transistor is provided as the double gate, and the number of the transistors provided as the double gate is small, which is beneficial to saving the layout space of the display panel.

The invention also provides simulation verification for the pixel circuit shown in fig. 4 and the pixel circuit shown in fig. 7 in the prior art. Fig. 9 is a diagram illustrating a simulation result of a gate leakage effect of a driving transistor according to an embodiment of the present invention. Referring to fig. 9, wherein the horizontal axis represents one frame time, the vertical axis represents the ratio of the voltage value V of the voltage of the gate electrode G at the end of the light emitting period to the voltage value V0 at the start of the light emitting period. A line L1 represents the related art, a line L2 represents the pixel circuit shown in fig. 4, and a line L3 represents the pixel circuit shown in fig. 7. The leakage effect is plotted in fig. 9 for the cases of refresh frequencies of 60Hz, 30Hz, 20Hz and 10 Hz. See table 1 for specific numerical results.

TABLE 1

		Va	Vb	Vc
					60Hz	16.7msec	98％	100％	100％
30Hz	33msec	94％	99％	99％
					20Hz	50msec	90％	98％	98％
10Hz	100msec	79％	95％	95％

Where Va denotes V/V0 in the related art, Vb denotes V/V0 of the pixel circuit shown in fig. 4, and Vc denotes V/V0 of the pixel circuit shown in fig. 7. As can be seen from fig. 9 and table 1, the embodiment of the present invention can effectively reduce the leakage current of the path connecting the gate G and the light emitting stage, improve the current holding ratio of the driving transistor DTFT, and improve the problem of flicker of the display panel under the condition of low refresh frequency. And the lower the refresh frequency is, the better the improvement effect of the voltage holding ratio of the gate G of the driving transistor DTFT is compared with the prior art in the embodiment of the present invention.

On the basis of the above embodiments, optionally, one of the first transistor T1 and the second transistor T2 may also be provided as a double-gate transistor; it is also possible to provide the first transistor T1, the second transistor T2, and the fourth transistor T4 as double gate transistors.

On the basis of the above embodiments, the embodiments of the present invention further provide the following extension schemes. Fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 10, alternatively, different from the above embodiments, the connection manner of the data writing module 130 and the driving module 110 is changed, and the structure of the data writing module 130 is simpler. The Data writing module 130 only includes a first end, a second end and a fifth end, the fifth end of the Data writing module 130 is connected to the second scanning signal S2, the first end of the Data writing module 130 is connected to the Data signal Data, and the second end of the Data writing module 130 is electrically connected to the first end of the driving module 110; a second end of the driving module 110 is electrically connected to a second end of the leakage current suppressing module 150. Illustratively, the data writing module 130 includes a third transistor T3, and the driving module 110 includes a driving transistor DTFT. The gate of the third transistor T3 is used as the fifth terminal of the data writing module 130, and is connected to the second scan signal S2. A first pole of the third transistor T3 serves as a second terminal of the data writing module 130, and is electrically connected to a first pole of the driving transistor DTFT. The second pole of the third transistor T3 is used as the first end of the Data writing module 130 to receive the Data signal Data. The second pole of the driving transistor DTFT is electrically connected to the first pole of the fourth transistor T4.

As can be seen from the above analysis, in the initialization stage JD1, the initialization signal Vini is written into the gate G of the driving transistor DTFT; meanwhile, with the pixel circuit shown in fig. 10, in the initialization stage JD1, it is also possible to write the initialization signal Vini to the second pole (node Na) of the driving transistor DTFT through the first transistor T1. In the Data writing and threshold voltage compensation phase JD2, the Data signal Data is written into the gate of the driving transistor DTFT through the third transistor T3, the driving transistor DTFT and the fourth transistor T4. Therefore, the setting can initialize the gate G and the second pole (node Na) of the driving transistor DTFT simultaneously in the initialization stage JD1 without affecting data writing and threshold voltage compensation, thereby facilitating the improvement of the initialization effect of the driving transistor DTFT and the performance of the pixel circuit.

In the above embodiments, the transistors are all P-type transistors, which are used as an example, and the present invention is not limited thereto. In other embodiments, each transistor may also be an N-type transistor, and in practical applications, the setting may be performed as needed, and the connection relationship between the transistors may be adjusted.

The embodiment of the invention also provides a gate driving circuit. The gate driving circuit can simultaneously output a first light-emitting control signal and a second light-emitting control signal with opposite levels, and is suitable for providing the first light-emitting control signal and the second light-emitting control signal for the pixel circuit provided by any embodiment of the invention. Fig. 11 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention. Referring to fig. 11, the gate driving circuit includes: a first input module 210, a second input module 220, a first bootstrap and output module 230, and a second bootstrap and output module 240.

The first input block 210 is configured to transmit a first front-stage first lighting control signal EMS (n-1) to an output terminal of the first input block 210 in response to the first clock signal ECK 1. The first front-stage light-emitting control signal EMS (n-1) is a first input signal EIN of the gate driving circuit. The second input block 220 is used for transmitting a previous stage second light emitting control signal EMSB (n-1) to an output terminal of the second input block 220 in response to the first clock signal ECK 1. The front-stage second emission control signal EMSB (n-1) is the second input signal EINB of the gate driving circuit. The first bootstrap and output module 230 includes an output end, and the output end of the first bootstrap and output module 230 outputs the current-stage second light-emitting control signal emsb (n); the first bootstrap and output module 230 is configured to output a first level signal VGL at an output end thereof in response to a signal at the output end of the second input module 220, and perform bootstrap coupling in response to the output first level signal VGL and the second clock signal ECK2 to maintain the output of the first level signal VGL; and, the first bootstrap and output module 230 is used for responding to the signal at the output terminal of the first input module 210, and outputting the second level signal VGH at the output terminal thereof. The second bootstrap and output module 240 includes an output end, and the output end of the second bootstrap and output module 240 outputs the first lighting control signal ems (n) of this level; the second bootstrap and output module 240 is configured to respond to the signal at the output end of the first input module 210, output a first level signal VGL at the output end thereof, perform bootstrap coupling in response to the output first level signal VGL and the second clock signal ECK2, and maintain the output of the first level signal VGL; and, the second bootstrap and output module 240 is configured to control the output end thereof to output the second level signal VGH when the second emission control signal emsb (n) of the current stage is the first level signal VGL.

The second input module 220 and the first bootstrap and output module 230 are configured to output a current-stage second light-emitting control signal emsb (n), and the second input module 220 and the first bootstrap and output module 230 are collectively referred to as an upper branch. The first input module 210 and the second bootstrap and output module 240 are configured to output a current-stage first lighting control signal ems (n), and the first input module 210 and the second bootstrap and output module 240 are collectively referred to as a down branch.

It can be seen that the embodiment of the invention provides a novel gate driving circuit, which is capable of simultaneously receiving a previous stage first emission control signal EMS (n-1) and a previous stage second emission control signal EMSB (n-1), and coupling the first clock signal ECK1, the second clock signal ECK2, the first level signal VGL, and the second level signal VGH, and simultaneously outputting the present stage first emission control signal EMS (n) and the present stage second emission control signal EMSB (n). Therefore, the gate driving circuit provided by the embodiment of the invention can meet the requirement of the pixel circuit provided by the embodiment of the invention on the light-emitting control signal. And the circuit structure of the embodiment of the invention is simple and easy to realize.

With continued reference to fig. 11, based on the above embodiment, optionally, the first bootstrap and output module 230 further includes a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. A first end of the first bootstrap and output module 230 is electrically connected to an output end of the first input module 210, a second end of the first bootstrap and output module 230 is electrically connected to an output end of the second input module 220, a third end of the first bootstrap and output module 230 is connected to the first level signal VGL, a fourth end of the first bootstrap and output module 230 is connected to the second level signal VGH, and a fifth end of the first bootstrap and output module 230 is connected to the second clock signal ECK 2.

Optionally, the first bootstrap and output module 230 includes: a first bootstrap unit 231, a first transmission unit 232, and a second bootstrap unit 233.

The first bootstrap unit 231 includes a first end, a second end, a third end and a fourth end, the first end of the first bootstrap unit 231 is electrically connected to the output end of the first input module 210, the second end of the first bootstrap unit 231 is connected to the second level signal VGH, the third end of the first bootstrap unit 231 is electrically connected to the output end of the second input module 220, and the fourth end of the first bootstrap unit 231 is connected to the second clock signal ECK 2; the first bootstrap unit 231 is configured to perform bootstrap coupling in response to the second clock signal ECK 2. The first bootstrap unit is equivalent to a previous stage bootstrap circuit of the upper branch.

The first transmission unit 232 comprises an input end and an output end, and the input end of the first transmission unit 232 is electrically connected with the output end of the second input module 220; the first transmission unit 232 is used for transmitting the signal at the output terminal of the second input module 220.

The second bootstrap unit 233 includes a first end, a second end, a third end, a fourth end and an output end, the first end of the second bootstrap unit 233 is electrically connected to the output end of the first input module 210, the second end of the second bootstrap unit 233 is connected to the second level signal VGH, the third end of the second bootstrap unit 233 is electrically connected to the output end of the first transmission unit 232, the fourth end of the second bootstrap unit 233 is connected to the first level signal VGL, the output end of the second bootstrap unit 233 serves as the output end of the first bootstrap and output module 230, and outputs the second light emission control signal emsb (n) of this stage; the second bootstrap unit 233 is configured to respond to the signal at the output end of the first transmission unit 232, output a first level signal VGL at the output end thereof, and perform bootstrap coupling in response to the output first level signal VGL; and, in response to the signal at the output terminal of the first input module 210, outputs the second level signal VGH at the output terminal thereof. The second bootstrap unit 233 corresponds to a subsequent stage bootstrap circuit and an output terminal of the upper branch.

Therefore, by providing the first bootstrap unit 231, the embodiment of the present invention can implement the function of performing bootstrap coupling in the first bootstrap and output module 230 in response to the second clock signal ECK 2; the second bootstrap unit 233 is configured to enable the first bootstrap and output module 230 to output the first level signal VGL at the output end thereof in response to the signal at the output end of the second input module 220, perform bootstrap coupling in response to the output first level signal VGL, and output the second level signal VGH at the output end thereof in response to the signal at the output end of the first input module 210; the first transmission unit 232 is configured to transmit a low level and an ultra-low level to a subsequent circuit (the second bootstrap unit 233), so as to improve the stability of the circuit.

With reference to fig. 11, on the basis of the foregoing embodiments, optionally, the second bootstrap and output module 240 further includes a first end, a second end, a third end, a fourth end, and a fifth end, the first end of the second bootstrap and output module 240 is electrically connected to the output end of the first bootstrap and output module 230, the second end of the second bootstrap and output module 240 is electrically connected to the output end of the first input module 210, the third end of the second bootstrap and output module 240 is connected to the first level signal VGL, the fourth end of the second bootstrap and output module 240 is connected to the second level signal VGH, and the fifth end of the second bootstrap and output module 240 is connected to the second clock signal ECK 2.

With continued reference to fig. 11, optionally, the second bootstrap and output module 240 includes: a third bootstrapping unit 241, a second transmission unit 242 and a fourth bootstrapping unit 243.

The third bootstrap unit 241 includes a first end, a second end, a third end and a fourth end, the first end of the third bootstrap unit 241 is electrically connected to the output end of the first input module 210, the second end of the third bootstrap unit 241 is electrically connected to the output end of the second input module 220, the third end of the third bootstrap unit 241 is connected to the second level signal VGH, and the fourth end of the third bootstrap unit 241 is connected to the second clock signal ECK 2; the third bootstrap unit 241 is configured to bootstrap couple in response to the second clock signal ECK 2. The third bootstrap unit 241 corresponds to a previous stage bootstrap circuit of the lower branch.

The second transmission unit 242 includes an input terminal and an output terminal, and the input terminal of the second transmission unit 242 is electrically connected to the output terminal of the first input module 210; the second transmission unit 242 is used for transmitting the signal at the output terminal of the first input module 210.

The fourth self-lifting unit 243 includes a first end, a second end, a third end, a fourth end, a fifth end and an output end, the first end of the fourth self-lifting unit 243 is electrically connected to the output end of the first bootstrap and output module 230, and is connected to the second light-emitting control signal emsb (n) of the current stage; a second end of the fourth self-lifting unit 243 is connected to the second level signal VGH, a third end of the fourth self-lifting unit 243 is electrically connected to an output end of the second transmission unit 242, a fourth end of the fourth self-lifting unit 243 is connected to the first level signal VGL, a fifth end of the fourth self-lifting unit 243 is electrically connected to an output end of the second input module 220, and an output end of the fourth self-lifting unit 243 is used as an output end of the second bootstrap and output module 240 to output a first local-level lighting control signal ems (n); the fourth self-lifting unit 243 is configured to respond to the signal at the output end of the second transmission unit 242, output the first level signal VGL at the output end thereof, and perform bootstrap coupling in response to the output first level signal VGL; and the fourth self-lifting unit 243 is used for controlling the output end thereof to output the second level signal VGH when the current-stage second light-emitting control signal emsb (n) is the first level signal VGL. The fourth self-lifting unit 243 is equivalent to the bootstrap circuit and the output terminal of the next stage of the lower branch.

Therefore, in the embodiment of the present invention, by providing the third bootstrap unit 241, the function of performing bootstrap coupling in response to the second clock signal ECK2 in the second bootstrap and output module 240 can be realized; the fourth self-lifting unit 243 is configured to enable the second bootstrap and output module 240 to respond to the signal at the output end of the first input module 210, output the first level signal VGL at the output end thereof, and perform bootstrap coupling in response to the output first level signal VGL; and when the second light-emitting control signal EMSB (n) of the current stage is the first level signal VGL, controlling the output end of the second light-emitting control signal EMSB (n) to output a second level signal VGH; the second transmission unit 242 is configured to transmit a low level and an ultra-low level to a subsequent circuit (the fourth self-lifting unit 243), so as to improve the stability of the circuit.

On the basis of the foregoing embodiments, optionally, the gate driving circuit further includes: a first partition module and a second partition module. The first blocking module is connected between the second input module 220 and the first bootstrap and output module 230, and is configured to block transmission of the too low level signal in the first bootstrap and output module 230 to the second input module 220. A first end of the first partition module is electrically connected to the second input module 220, and a second end of the first partition module is electrically connected to the first bootstrap and output module 230. The second blocking module is connected between the first input module 210 and the second bootstrap and output module 240, and is configured to block transmission of a too low level signal in the second bootstrap and output module 240 to the first input module 210. The first end of the second partition module is electrically connected to the first input module 210, and the second end of the first partition module is electrically connected to the second bootstrap and output module 240.

On the basis of the foregoing embodiments, specific arrangement modes of the transistors in the first bootstrap unit 231, the first transmission unit 232, the second bootstrap unit 233, the third bootstrap unit 241, the second transmission unit 242, the fourth bootstrap unit 243, the first partition module, the second partition module, the first input module 210, and the second input module 220 are described below, but the present invention is not limited thereto.

Fig. 12 is a schematic structural diagram of another gate driving circuit according to an embodiment of the invention. Referring to fig. 12, in an embodiment of the present invention, optionally, the first bootstrap unit 231 includes: an eighth transistor M1, a ninth transistor M2, and a first capacitor C1. The gate of the eighth transistor M1 is electrically connected to the output terminal of the first input module 210, and the first pole of the eighth transistor M1 is connected to the second level signal VGH. The gate of the ninth transistor M2 is electrically connected to the output terminal of the second input module 220 (or the second terminal of the first partition module 250), the first pole of the ninth transistor M2 is connected to the second clock signal ECK2, and the second pole of the ninth transistor M2 is electrically connected to the second pole of the eighth transistor M1. The first capacitor C1 is connected between the gate and the second pole of the ninth transistor M2.

In one embodiment of the present invention, optionally, the first transmission unit 232 comprises a tenth transistor M3, a gate of the tenth transistor M3 is electrically connected to the first pole and serves as an input terminal of the first transmission unit 232, and a second pole of the tenth transistor M3 serves as an output terminal of the first transmission unit 232. Wherein the tenth transistor M3 is diode-connected for transmitting low and very low levels to the right.

In one embodiment of the present invention, the second bootstrap unit 233 optionally includes an eleventh transistor M4, a twelfth transistor M5, a thirteenth transistor M6 and a second capacitor C2. A gate of the eleventh transistor M4 is electrically connected to the output terminal of the first transmission unit 232, a first pole of the eleventh transistor M4 is connected to the first level signal VGL, and a second pole of the eleventh transistor M4 serves as the output terminal of the second bootstrap unit 233. A gate of the twelfth transistor M5 is electrically connected to the output terminal of the first input module 210, a first pole of the twelfth transistor M5 is connected to the second level signal VGH, and a second pole of the twelfth transistor M5 is electrically connected to the output terminal of the first transmission unit 232. A gate of the thirteenth transistor M6 is electrically connected to the output terminal of the first input module 210, a first pole of the thirteenth transistor M6 is connected to the second level signal VGH, and a second pole of the thirteenth transistor M6 is electrically connected to a second pole of the eleventh transistor M4. The second capacitor C2 is connected between the gate and the second pole of the eleventh transistor M4.

In an embodiment of the present invention, optionally, the third bootstrap unit 241 includes: a fourteenth transistor M7, a fifteenth transistor M8, and a third capacitor C3. The gate of the fourteenth transistor M7 is electrically connected to the output terminal of the first input module 210 (or the second terminal of the second partition module 260), and the first pole of the fourteenth transistor M7 is connected to the second clock signal ECK 2. A gate of the fifteenth transistor M8 is electrically connected to the output terminal of the second input module 220 (or the second terminal of the first blocking module 250), a first pole of the fifteenth transistor M8 is connected to the second level signal VGH, and a second pole of the fifteenth transistor M8 is electrically connected to the second pole of the fourteenth transistor M7. The third capacitor C3 is connected between the gate and the second pole of the fourteenth transistor M7.

In one embodiment of the present invention, optionally, the second transmission unit 242 includes a sixteenth transistor M9, a gate of the sixteenth transistor M9 is electrically connected to the first pole and serves as an input terminal of the second transmission unit, and a second pole of the sixteenth transistor M9 serves as an output terminal of the second transmission unit. Wherein the sixteenth transistor M9 is diode-connected for transmitting low and very low levels to the right.

In an embodiment of the present invention, optionally, the fourth self-lifting unit 243 includes: a seventeenth transistor M10, an eighteenth transistor M11, a nineteenth transistor M12, and a fourth capacitor C4. The gate of the seventeenth transistor M10 is electrically connected to the output terminal of the second transmission unit 242, and the first pole of the seventeenth transistor M10 is connected to the first level signal VGL. The gate of the eighteenth transistor M11 is electrically connected to the output terminal of the first bootstrap and output module 230, the first pole of the eighteenth transistor M11 is connected to the second level signal VGH, and the second pole of the eighteenth transistor M11 is electrically connected to the second pole of the seventeenth transistor M10 and serves as the output terminal of the fourth bootstrap unit 243. A gate of the nineteenth transistor M12 is electrically connected to the output terminal of the second input module 220 (or the second terminal of the first blocking module 250), a first pole of the nineteenth transistor M12 is connected to the second level signal VGH, and a second pole of the nineteenth transistor M12 is electrically connected to the output terminal of the second transmission unit. The fourth capacitor C4 is connected between the gate and the second pole of the seventeenth transistor M10.

In an embodiment of the invention, optionally, the first blocking module 250 includes a twentieth transistor M13, a gate of the twentieth transistor M13 is connected to the first level signal VGL, a first pole of the twentieth transistor M13 is electrically connected to the first bootstrap and output module 230, and a second pole of the twentieth transistor M13 is electrically connected to the second input module 220.

In an embodiment of the present invention, optionally, the second blocking module 260 includes a twenty-first transistor M14, a gate of the twenty-first transistor M14 is connected to the first level signal VGL, a first pole of the twenty-first transistor M14 is electrically connected to the second bootstrap and output module 240, and a second pole of the twenty-first transistor M14 is electrically connected to the first input module 210.

In an embodiment of the present invention, optionally, the first input module 210 includes a twenty-second transistor M15, a gate of the twenty-second transistor M15 is connected to the first clock signal ECK1, a first pole of the twenty-second transistor M15 is connected to the first front-stage emission control signal EMS (n-1), and a second pole of the twenty-second transistor M15 is electrically connected to the second partition module 260.

In an embodiment of the invention, optionally, the second input module 220 includes a twenty-third transistor M16, a gate of the twenty-third transistor M16 is connected to the first clock signal ECK1, a first pole of the twenty-third transistor M16 is connected to the previous stage of the second light emitting control signal EMSB (n-1), and a second pole of the twenty-third transistor M16 is electrically connected to the first blocking module.

Here, the second pole of the twentieth transistor M15 is defined as the first node N1, the first pole of the twenty-first transistor M14 is defined as the second node N2, the first pole of the twentieth transistor M13 is defined as the third node N3, the second pole of the eighth transistor M1 is defined as the fourth node N4, the second pole of the fourteenth transistor M7 is defined as the fifth node N5, the second pole of the tenth transistor M3 is defined as the sixth node N6, and the gate of the seventeenth transistor M10 is defined as the seventh node N7.

Fig. 13 is a timing diagram of a gate driving circuit according to an embodiment of the invention, and fig. 14 to 17 are switching state diagrams of the gate driving circuit at various stages according to the embodiment of the invention. Referring to fig. 13 to 17, each transistor is a P-type transistor, the first level signal VGL is at a low level, and the second level signal VGH is at a high level. The driving process of the gate driving circuit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t 5. In fig. 14 to 17, x represents that the transistor is off and the capacitor is discharged or not charged and discharged; v represents that the transistor is turned on and the capacitor is charged; the dotted line indicates no current flow; the solid line indicates that current is flowing.

In the first phase t1, referring to fig. 13 and 14, the first clock signal ECK1 and the first input signal EIN are at a low level, and the second clock signal ECK2 and the second input signal EINB are at a high level. The high level of the second input signal EINB enters the third node N3, the first capacitor C1 is discharged, and the ninth transistor M9 is turned off. The low level of the first input signal EIN turns on the thirteenth transistor M6, and sets the current-stage second emission control signal emsb (n) high. The low level of the first input signal EIN enters the first node N1 and the second node N2, the fourteenth transistor M7 is turned on, the third capacitor C3 is charged, and enters the seventh node N7 through the sixteenth transistor M9, at which the seventeenth transistor M10 is turned on, the current-stage first lighting control signal ems (N) is pulled down, and the seventh node N7 is coupled by the fourth capacitor C4 and continuously drops to a potential lower than the first level signal VGL (e.g., about-11V), so that the current-stage first lighting control signal ems (N) can directly drop from the second level signal VGH to the first level signal VGL without signal tailing.

In the second stage t2, referring to fig. 13 and 15, the second clock signal ECK2 and the first input signal EIN are at a low level, and the first clock signal ECK1 and the second input signal EINB are at a high level. Since the ninth transistor M2 is turned off in the first stage t1, the low level of the second clock signal ECK2 is not transmitted, the up-branch signal is unchanged, and the current stage of the second emission control signal emsb (n) maintains the high level substantially unchanged. The down-branch second clock signal ECK2 jumps down to a low level, the potential of the second node N2 is pushed down to a level (e.g., -14V) far lower than the first level signal VGL by the fourteenth transistor M7 and the third capacitor C3, and the potential of the seventh node N7 is pulled down a little by the sixteenth transistor M9, the seventeenth transistor M10 remains turned on strongly, and the present stage of the first lighting control signal ems (N) remains low substantially.

In the third stage t3, the switching state of the gate driving circuit repeats the switching states of the first stage t1 and the second stage t2, which is not described again.

In the fourth phase t4, referring to fig. 13 and 16, the first clock signal ECK1 and the second input signal EINB are at a low level, and the second clock signal ECK2 and the first input signal EIN are at a high level. The low level of the second input signal EINB is inputted to the third node N3, the ninth transistor M2 is turned on, the first capacitor C1 is charged, the low level of the third node N3 is transmitted to the sixth node N6 through the tenth transistor M3, the eleventh transistor M4 is turned on, and the present stage second emission control signal emsb (N) is pulled low. Meanwhile, the sixth node N6 is coupled by the second capacitor C2, and the voltage level drops below the first level signal VGL, so that the current stage of the second emission control signal emsb (N) can directly drop from the second level signal VGH to the first level signal VGL without trailing the falling edge signal. The eighteenth transistor M11 is turned on, and the current-stage first emission control signal ems (n) outputs a high level. The level of the first input signal EIN enters the second node N2 through the twenty-second transistor M15, the twenty-first transistor M14, the third capacitor C3 is discharged, the fourteenth transistor M7 is turned off, the high level enters the seventh node N7 through the nineteenth transistor M12, and the seventeenth transistor M10 is turned off.

In the fifth phase t5, the second clock signal ECK2 and the second input signal EINB are at a low level, and the first clock signal ECK1 and the first input signal EIN are at a high level. The low level of the second clock signal ECK2 is coupled to the third node N3 through the parasitic capacitance of the ninth transistor M2, so that the potential of the third node N3 drops below the first level signal VGL and the potentials of the other nodes are substantially maintained.

The on-off states of the fourth stage t4 and the fifth stage t5 are repeated, so that the current-stage second light-emitting control signal emsb (n) maintains the output low level, and the current-stage first light-emitting control signal ems (n) maintains the output high level, which is not described again.

As described above, when the potential of the sixth node N6 is extremely low, although there is a leak current through the tenth transistor M3 and the twelfth transistor M5, and the potential of the sixth node N6 is gradually raised, the potential of the sixth node N6 is continuously pulled down by the extremely low potential periodically at the third node N3. Therefore, the sixth node N6 does not drift to a potential higher than the first level signal VGL due to leakage when it remains lower than the low level for a long time. The seventh node N7 and the sixth node N6 are similar in operation, and therefore, the gate driving circuit provided by the embodiment of the invention has no low voltage loss and signal tailing, and has good long-term stability.

The embodiment of the invention also provides a display panel, which can be an organic light-emitting diode display panel or a micro light-emitting diode display panel lamp active light-emitting display panel. The display panel includes a plurality of gate driving circuits provided in any of the embodiments of the present invention and connected in cascade, and a plurality of pixel circuits provided in any of the embodiments of the present invention and arranged in an array.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A pixel circuit, comprising:

2. The pixel circuit according to claim 1, wherein the leakage current suppressing module comprises a control terminal, a first terminal and a second terminal, the control terminal of the leakage current suppressing module is connected to the second light-emitting control signal, and the first terminal of the leakage current suppressing module is electrically connected to the control terminal of the driving module;

3. The pixel circuit according to claim 1, wherein the leakage current suppressing module comprises a control terminal, a first terminal and a second terminal, the control terminal of the leakage current suppressing module is connected to the second light emitting control module, and the first terminal of the leakage current suppressing module is electrically connected to the control terminal of the driving module;

4. The pixel circuit according to any one of claims 1-3,

the transistor in the grid initialization module is a double-grid transistor; the transistor electrically connected with the control end of the driving module in the data writing module is a double-gate transistor;

5. The pixel circuit according to any one of claims 1 to 3, wherein the light emission control module comprises a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal, the fifth terminal of the light emission control module is connected to the first light emission control signal, the first terminal of the light emission control module is connected to the first power signal, the second terminal of the light emission control module is electrically connected to the first terminal of the driving module, the third terminal of the light emission control module is electrically connected to the second terminal of the driving module, and the fourth terminal of the light emission control module is electrically connected to the light emitting device;

6. A gate drive circuit for supplying the first light emission control signal and the second light emission control signal to the pixel circuit according to any one of claims 1 to 5, the gate drive circuit comprising:

7. The gate driving circuit according to claim 6, wherein the first bootstrap and output module further includes a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal, the first terminal of the first bootstrap and output module is electrically connected to the output terminal of the first input module, the second terminal of the first bootstrap and output module is electrically connected to the output terminal of the second input module, the third terminal of the first bootstrap and output module is connected to the first level signal, the fourth terminal of the first bootstrap and output module is connected to the second level signal, and the fifth terminal of the first bootstrap and output module is connected to the second clock signal;

preferably, the first bootstrap and output module includes:

preferably, the first bootstrap unit includes:

preferably, the second bootstrap unit includes:

8. The gate driving circuit according to claim 6, wherein the second bootstrap and output module further includes a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal, the first terminal of the second bootstrap and output module is electrically connected to the output terminal of the first bootstrap and output module, the second terminal of the second bootstrap and output module is electrically connected to the output terminal of the first input module, the third terminal of the second bootstrap and output module is connected to the first level signal, the fourth terminal of the second bootstrap and output module is connected to the second level signal, and the fifth terminal of the second bootstrap and output module is connected to the second clock signal;

preferably, the second bootstrap and output module includes:

preferably, the third bootstrap unit includes:

preferably, the fourth self-lifting unit comprises:

9. The gate drive circuit of claim 6, further comprising:

10. A display panel comprising a plurality of gate driver circuits as claimed in any one of claims 6 to 9 connected in cascade, and a plurality of pixel circuits as claimed in any one of claims 1 to 5 arranged in an array.