CN113327982B - Super junction MOSFET device and chip - Google Patents
Super junction MOSFET device and chip Download PDFInfo
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- CN113327982B CN113327982B CN202110554780.4A CN202110554780A CN113327982B CN 113327982 B CN113327982 B CN 113327982B CN 202110554780 A CN202110554780 A CN 202110554780A CN 113327982 B CN113327982 B CN 113327982B
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- 229910052796 boron Inorganic materials 0.000 claims description 7
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- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
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- 229910052785 arsenic Inorganic materials 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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Abstract
The application discloses super junction MOSFET device and chip. The super junction MOSFET device comprises an N-type epitaxial layer, and a cell area and a terminal area which are positioned on the N-type epitaxial layer; the cellular region comprises a first super-junction structure, the upper surfaces of two sides of the first super-junction structure are respectively provided with a first P-type base region, the upper end surface of the middle of the first super-junction structure is provided with a first polysilicon gate, the lower surface and two side surfaces of the first polysilicon gate are respectively provided with a first oxide layer, and the periphery of the first oxide layer is provided with source metal; the terminal area comprises a second super junction structure, a second P-type base area is arranged on the upper surface of the second super junction structure, a second oxidation layer is arranged on the upper surface of the second P-type base area, and a second polysilicon gate is arranged on the second oxidation layer; and controlling the states of the first polysilicon gate and the second polysilicon gate to form a conductive channel for current to pass on the surface of the first P-type base region. The present application can improve reverse recovery characteristics.
Description
Technical Field
The application relates to the field of power semiconductor devices, in particular to a super junction MOSFET device and a chip.
Background
The body diode characteristic of a super-junction Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) device is worse than that of a conventional MOSFET because the super-junction MOSFET device has an alternating PN column structure inside, so that the concentration of unbalanced carriers stored in a voltage-withstanding layer is higher when the body diode is in forward conduction, and the speed of extracting the unbalanced carriers is very high in the reverse recovery process of the body diode. Overshoot of current and voltage is easy to occur in the reverse recovery process, so that the super junction MOSFET device is damaged, and the reverse recovery characteristic is poor.
Disclosure of Invention
In view of this, the present application provides a super junction MOSFET device and a chip to solve the problem of poor reverse recovery characteristics of the existing super junction MOSFET device.
The super junction MOSFET device comprises an N-type epitaxial layer, and a cell area and a terminal area which are positioned on the N-type epitaxial layer; wherein the content of the first and second substances,
the cell area comprises a first super-junction structure, the upper surfaces of two sides of the first super-junction structure are respectively provided with a first P-type base area, the upper end surface of the middle of the first super-junction structure is provided with a first polysilicon gate, the lower surface and two side surfaces of the first polysilicon gate are respectively provided with a first oxide layer, and the periphery of the first oxide layer is provided with source metal;
the terminal area comprises a second super-junction structure, a second P-type base area is arranged on the upper surface of the second super-junction structure and is in contact with the first P-type base area, a second oxide layer is arranged on the upper surface of the second P-type base area, a second polysilicon grid is arranged on the second oxide layer, and a grid PAD (welding PAD) is arranged on the upper surface of the second polysilicon grid;
and controlling the states of the first polysilicon gate and the second polysilicon gate to form a conductive channel for current to pass on the surface of the first P-type base region.
The first polysilicon gate comprises first N-type polysilicon and first P-type polysilicon located on the upper surface of the first N-type polysilicon, the first P-type polysilicon forms ohmic contact with the source metal, and the first N-type polysilicon is connected with the gate PAD through a gate wire.
And the first P-type base region on each side is provided with an N + source region and a P + body region which are contacted with each other, wherein the upper surface of the part of the N + source region and the upper surface of the part of the P + body region on one side are connected with one end of the source metal, and the upper surface of the part of the N + source region and the upper surface of the part of the P + body region on the other side are connected with the other end of the source metal.
The thickness of the first oxide layer on the two side surfaces of the first polysilicon grid is larger than that of the first oxide layer on the lower surface of the first polysilicon grid.
The first super-junction structure comprises a first N column and first P columns located on two sides of the first N column, the first N column is a partial region of the N-type epitaxial layer, the upper surface of the first P column on each side is in contact with the first P-type base region located on the same side, and the upper surface of the first N column is in contact with the first oxide layer.
The first N-type polycrystalline silicon is P-type polycrystalline silicon doped with phosphorus, and the first P-type polycrystalline silicon is P-type polycrystalline silicon doped with boron.
The second polysilicon gate comprises second N-type polysilicon and second P-type polysilicon positioned on the upper surface of the second N-type polysilicon, and the second P-type polysilicon forms ohmic contact with gate metal on the gate PAD.
The second N-type polycrystalline silicon comprises a first N-type polycrystalline silicon area and a second N-type polycrystalline silicon area which are in contact with each other, and the second N-type polycrystalline silicon area is located at the center position of the super junction MOSFET device or close to the center position of the super junction MOSFET device.
The first N-type polycrystalline silicon area is connected with the gate routing, the width of the first N-type polycrystalline silicon area is equal to that of the second P-type polycrystalline silicon, and the second N-type polycrystalline silicon area extends to be in contact with the first N-type polycrystalline silicon along the gate interdigital.
The second super junction structure comprises second N columns and second P columns which are alternately distributed, the second N columns are partial regions of the N-type epitaxial layer, and the upper surfaces of the second N columns and the second P columns are both in contact with the second P-type base region.
The application provides a chip, which comprises a super junction MOSFET device provided by the embodiment of the application.
According to the super junction MOSFET device and the chip, the N-type epitaxial layer, the cellular region and the terminal region are arranged on the N-type epitaxial layer; the cell area comprises a first super-junction structure, the upper surfaces of two sides of the first super-junction structure are respectively provided with a first P-type base area, the upper end surface of the middle of the first super-junction structure is provided with a first polysilicon gate, the lower surface and two side surfaces of the first polysilicon gate are respectively provided with a first oxide layer, and the periphery of the first oxide layer is provided with source metal; the terminal area comprises a second super-junction structure, a second P-type base area is arranged on the upper surface of the second super-junction structure and is in contact with the first P-type base area, a second oxidation layer is arranged on the upper surface of the second P-type base area, and a second polysilicon gate is arranged on the second oxidation layer. Therefore, the states of the first polysilicon gate and the second polysilicon gate can be controlled to control the conductive channel for current to pass through formed on the surface of the first P-type base region. Thus, current is made to flow through the MOS channel path and not through the body diode path, reducing the injection of unbalanced minority carriers. Therefore, the present application can improve reverse recovery characteristics.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a top-view structure of a super junction MOSFET device provided by an embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of section AA 'BB' of FIG. 1, provided in accordance with an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view of section CC' D of FIG. 1 provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of a chip provided in an embodiment of the present application.
Detailed Description
The body diode characteristics of the super-junction MOSFET device are worse than those of the conventional MOSFET because the super-junction MOSFET device has an alternating PN column structure inside, so that the concentration of non-equilibrium carriers stored in a voltage-withstanding layer is higher when the body diode is in forward conduction, and the extraction speed of the non-equilibrium carriers is high in the reverse recovery process of the body diode. Overshoot of current and voltage is easy to occur in the reverse recovery process, so that the super junction MOSFET device is damaged, and the reverse recovery characteristic is poor. In order to solve this problem, the present application proposes a super junction MOSFET device that can improve reverse recovery characteristics.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic structural diagram of a super junction MOSFET device according to an embodiment of the present application; FIG. 2 is a schematic cross-sectional view of section AA 'BB' of FIG. 1, provided in accordance with an embodiment of the present disclosure; fig. 3 is a schematic cross-sectional view of section CC' D in fig. 1 provided by an embodiment of the present application. The super junction MOSFET device comprises an N-type epitaxial layer 10, a cell region 20 and a termination region 30, wherein the cell region 20 and the termination region 30 are located on the N-type epitaxial layer 10. The cell region 20 and the termination region 30 may be in contact.
It should be noted that the BB' section corresponds to a cell area 20 of the super junction MOSFET device, and in the embodiment of the present application, one cell area 20 is exemplarily shown, in practical applications, the number of the cell areas 20 may also be multiple according to specific requirements, and the number of the cell areas 20 in the embodiment of the present application is not particularly limited.
In this embodiment, the cell region 20 is a cell structure of a super junction MOSFET device, the cell region 20 includes a first super junction structure 201, first P-type base regions 202 are respectively disposed on upper surfaces of two sides of the first super junction structure 201, a first polysilicon gate 203 is disposed on an upper end surface in the middle of the first super junction structure 201, first oxide layers 204 are disposed on a lower surface and two side surfaces of the first polysilicon gate 203, a source metal 205 is disposed on a periphery of the first oxide layer 204, and the first oxide layer 204 can be used to isolate the first polysilicon gate 203 from the source metal 205, so as to avoid a short circuit phenomenon.
In one embodiment, the material of the first oxide layer 204 may be silicon dioxide (SiO 2). In another embodiment, the material of the first oxide layer 204 may be a composite material of silicon dioxide and silicon nitride.
In the embodiment of the present application, the width of the two ends of the source metal 205 may be smaller than the width of the first P-type base region 202 on the same side, so that the two ends of the source metal 205 may be formed within the limited width range of the first P-type base region 202, so as to save space.
In this embodiment, the terminal region 30 includes a second super junction structure 301, a second P-type base region 302 is disposed on an upper surface of the second super junction structure 301, and the second P-type base region 302 is in contact with the first P-type base region 202. A second oxide layer 303 is disposed on the upper surface of the second P-type base region 302, a second polysilicon gate 304 is disposed on the second oxide layer 303, and the second oxide layer 303 may be used to isolate the second polysilicon gate 304 from the source metal 205, so as to avoid a short circuit.
In one embodiment, the material of the second oxide layer 303 may be silicon dioxide (SiO 2). In another embodiment, the material of the second oxide layer 303 may be a composite material of silicon dioxide and silicon nitride.
In the embodiment, a gate PAD305 is disposed on the upper surface of the second polysilicon gate 304.
In the embodiment of the present invention, the states of the first polysilicon gate 203 and the second polysilicon gate 304 may be controlled to control the formation of a conductive channel on the surface of the first P-type base region 202 through which power can flow. For example, by controlling the forward bias of the first polysilicon gate 203 of the cell region 20 and the reverse bias of the second polysilicon gate 304 under the gate PAD305, the surface of the first P-type base region 202 can be inverted to form a conductive channel for current to flow through, which can enable current to flow through a MOS channel path rather than through a body diode path of the super junction MOSFET device, thereby reducing unbalanced minority carrier injection.
It is understood that in the embodiment of the present application, the N-type epitaxial layer 10 and the cell region 20 and the termination region 30 are disposed on the N-type epitaxial layer 10. The cellular region 20 includes a first super-junction structure 201, first P-type base regions 202 are respectively disposed on upper surfaces of two sides of the first super-junction structure 201, a first polysilicon gate 203 is disposed on an upper end surface of the first super-junction structure 201 located at a middle position, first oxide layers 204 are disposed on a lower surface and two side surfaces of the first polysilicon gate 203, and a source metal 205 is disposed on a periphery of the first oxide layers 204. The terminal region 30 includes a second super junction structure 301, a second P-type base region 302 is disposed on an upper surface of the second super junction structure 301, the second P-type base region 302 is in contact with the first P-type base region 202, a second oxide layer 303 is disposed on an upper surface of the second P-type base region 302, and a second polysilicon gate 304 is disposed on the second oxide layer 303. Therefore, the states of the first polysilicon gate 203 and the second polysilicon gate 304 can be controlled to control the formation of a conductive channel on the surface of the first P-type base region 202 for current to pass through. Thus, current is made to flow through the MOS channel path and not through the body diode path, reducing the injection of unbalanced minority carriers. Therefore, the present application can improve reverse recovery characteristics.
For example, in one embodiment, the first polysilicon gate 203 may include a first N-type polysilicon 231 and a first P-type polysilicon 232, wherein the first P-type polysilicon 232 may be located on an upper surface of the first N-type polysilicon 231, the first P-type polysilicon 232 forms an ohmic contact with the source metal 205, and the first N-type polysilicon 231 is connected to the gate PAD305 through a gate trace to ensure that the first N-type polysilicon 231 is communicated with the gate PAD 305.
It should be noted that the first N-type polysilicon 231 is a heavily doped region, for example, in one embodiment, the first N-type polysilicon 231 may be an N-type polysilicon doped with phosphorus. The first P-type polysilicon 232 is a heavily doped region, for example, in one embodiment, the first P-type polysilicon 232 may be a boron-doped P-type polysilicon, which may be a composite material implanted with arsenic and boron, or may be pure boron.
In the embodiment of the present application, the cell region 20 includes two first P-type base regions 202, and the two first P-type base regions 202 are symmetrically distributed with respect to a center line of the first super junction structure 201.
For example, in one embodiment, the first P-type base region 202 on each side may be provided with an N + source region 221 and a P + body region 222 in contact, wherein a portion of the upper surface of the N + source region 221 and a portion of the upper surface of the P + body region 222 on one side are connected to one end of the source metal 205, and a portion of the upper surface of the N + source region 221 and a portion of the upper surface of the P + body region 222 on the other side are connected to the other end of the source metal 205.
In the embodiment of the present application, N + source region 221 may be near the center of the top of first superjunction structure 201. The N + source regions 221 on both sides may be symmetrically distributed with respect to the top of the first super junction structure 201, and the P + body regions 222 on both sides may be symmetrically distributed with respect to the first super junction structure 201, so as to ensure that the insulating properties of the first oxide layer 204 on both sides of the source metal 205 are uniform.
For example, in an embodiment, the thickness of the first oxide layer 204 on the two side surfaces of the first polysilicon gate 203 may be greater than the thickness of the first oxide layer 204 on the lower surface of the first polysilicon gate 203, so as to improve the isolation effect between the first polysilicon gate 203 and the source metal 205, and further avoid the occurrence of the short circuit phenomenon.
Of course, in other embodiments, the thickness of the first oxide layer 204 on the two sides of the first polysilicon gate 203 may be equal to the thickness of the first oxide layer 204 on the lower surface of the first polysilicon gate 203, or the thickness of the first oxide layer 204 on the two sides of the first polysilicon gate 203 may be smaller than the thickness of the first oxide layer 204 on the lower surface of the first polysilicon gate 203, and at this time, the isolation effect on the first polysilicon gate 203 and the source metal 205 may be deteriorated.
For example, in one embodiment, first superjunction structure 201 may include first N-pillar 211 and first P-pillars 212 located on both sides of first N-pillar 211, i.e., two first P-pillars 212 are included in first superjunction structure 201. The first N pillars 211 and the first P pillars 212 are alternately arranged, and the first N pillars 211 and the first P pillars 212 may constitute a body diode.
It should be noted that the first N pillar 211 may be a partial region of an N-type epitaxial layer, the upper surface of the first P pillar 212 on each side is in contact with the first P-type base region 202 located on the same side, and the upper surface of the first N pillar 211 is in contact with the first oxide layer 204.
Exemplarily depicted in fig. 2, first superjunction structure 201 includes one first N-pillar 211 and two first P-pillars 212. In practical applications, the first super-junction structure may include a plurality of first N pillars and a plurality of first P pillars, the first N pillars and the first P pillars are alternately distributed, and a body diode may be formed by adjacent first N pillars and first P pillars, and in a case where the first super-junction structure includes a plurality of first N pillars and a plurality of first P pillars, a plurality of body diodes may be formed.
For example, the number of the first P columns is two, the number of the first N columns is two, and the first P columns and the first N columns are alternately distributed, for example, from left to right, in the order of the first P columns, the first N columns, the first P columns, and the first N columns.
For another example, the number of the first P columns is three, the number of the first N columns is two, and the first P columns and the first N columns are alternately distributed, for example, from left to right, in the order of the first P columns, the first N columns, and the first P columns.
For another example, the number of the first P columns is four, the number of the first N columns is three, and the first P columns and the first N columns are alternately distributed, for example, from left to right, in the order of the first P columns, the first N columns, and the first P columns. In practical application, the number of the first N pillars and the first P pillars included in the super junction structure may be set according to specific requirements, and the number of the first N pillars 211 and the first P pillars 212 included in the first super junction structure 201 is not particularly limited in the embodiment of the present application.
It should be noted that all or a part of the cell region 20 of the super junction MOSFET device may be used as a trench diode to prevent the body diode (e.g., the body diode formed by the first N pillar 211 and the first P pillar 212, the body diode formed by the first N-type polysilicon 231 and the first P-type polysilicon 232, etc.) in the cell region 20 from being turned on. The channel diode has almost no unbalanced carrier storage effect, so that the reverse recovery time is shorter and the reverse recovery characteristic is better.
For example, in one embodiment, the first P-type base region 202 may be disposed on the upper surface of the first P pillar 212 and a portion of the side surface of the first N pillar 211, and contact the upper surface of the first P pillar 212 and a portion of the side surface of the first N pillar 211.
For example, in one embodiment, the second polysilicon gate 304 may include a second N-type polysilicon and a second P-type polysilicon 341 on an upper surface of the second N-type polysilicon, and the second P-type polysilicon 341 forms an ohmic contact with the gate metal on the gate PAD305 to ensure that the second P-type polysilicon 341 is connected to the gate metal on the gate PAD 305. As can be seen from the AA 'section and the CC' section, the second N-type polysilicon and the second P-type polysilicon 341 below the gate PAD305 form a second polysilicon diode.
It should be noted that the second N-type polysilicon is a heavily doped region, for example, in one embodiment, the second N-type polysilicon may be an N-type polysilicon doped with phosphorus. The second P-type polysilicon 341 is a heavily doped region, for example, in one embodiment, the second P-type polysilicon 341 may be a boron doped P-type polysilicon, which may be a composite material implanted with arsenic and boron, or may be pure boron.
For example, in one embodiment, as seen in the AA 'section and the CC' section of the figure, the second N-type polysilicon includes a first N-type polysilicon region 342 and a second N-type polysilicon region 343 that are in contact. Thus, the first N-type poly region 342 and the second N-type poly region 343 may respectively constitute a second poly diode having different properties with the second P-type poly 341. Wherein second N-type polysilicon region 343 may be located at or near a center location of the superjunction MOSFET device.
For example, in one embodiment, the first N-type polysilicon region 342 connects the gate traces, please refer to section AA', and the width of the first N-type polysilicon region 342 may be equal to the width of the second P-type polysilicon 341. Referring to the section CC', the second N-type polysilicon region 343 may extend along the gate finger CD direction to contact the first N-type polysilicon 231 of the cell region 20, and also contact the first polysilicon diode and the second polysilicon diode, so as to control the states of the first polysilicon diode and the second polysilicon diode at the same time.
It should be noted that, in order to ensure that the second N-type polysilicon region 343 may extend along the gate interdigital CD direction, in one embodiment, the width of the second P-type base region 302 may be greater than the width of the first P-type base region 202. When the width of the second P-type base region 302 can be greater than the width of the first P-type base region 202, enough space can be provided on the upper surface of the second P-type base region 302 for laying out the second oxide layer 303, and accordingly, the second oxide layer 303 can provide enough space for the second N-type polysilicon region 343 to extend along the gate finger CD direction.
For example, in one embodiment, second superjunction structure 301 includes second N pillars 311 and second P pillars 312 alternately distributed, where second N pillars 311 are a partial region of N-type epitaxial layer 10, and an upper surface of second N pillars 311 and an upper surface of second P pillars 312 are both in contact with second P-type base region 302.
It should be noted that the operating principle of the super junction MOSFET device is as follows: when the super-junction MOSFET device works normally as a super-junction MOSFET, the source metal 205 is grounded, the drain metal (the drain metal is led out from the substrate below the N-type epitaxial layer 10 and is not shown in the figure) is connected with a high potential, the gate PAD305 is connected with the high potential, the second polysilicon diode below the gate PAD305 is forward biased, and the gate signal is not influenced to be transmitted to the first polysilicon gate 203 of the cellular area 20 through the gate PAD 305. Meanwhile, the first polysilicon diode (i.e., the first N-type polysilicon gate 203) in the cell region 20 is reverse biased, and the source metal 205 and the first N-type polysilicon gate 203 are in a blocking state, so that the super junction MOSFET device is normally turned on.
When the gate PAD305 and the source metal 205 are both grounded, the drain metal is connected with high voltage, the super junction MOSFET device is turned off, the avalanche breakdown voltage of the super junction MOSFET device is basically the same as that of a common super junction MOSFET with the same parameters, and the turn-off of the super junction MOSFET device is not affected.
When the body diode freewheeling using the super-junction MOSFET device is used, the source metal 205 is connected to a high potential, the drain metal and the gate PAD305 are grounded, the first polysilicon diode of the cell region 20 is forward biased, and the second polysilicon diode under the gate PAD305 is reverse biased, so that the voltage of the first N-type polysilicon 231 of the cell region 20 is the same as the potential of the source metal 205 and is positively charged, the surface of the first P-type base region 202 under the first N-type polysilicon 231 will be reverse-type to form a conductive channel, so that the current will flow through the MOS channel path instead of the body diode path, and the injection of unbalanced minority carriers is reduced. Therefore, the embodiment of the present application can improve the reverse recovery characteristics.
Fig. 4 shows a schematic structure of a chip according to an embodiment of the present application, where fig. 4 is a schematic structure of the chip according to the embodiment of the present application. The chip 400 includes a super junction MOSFET device 401 provided by the embodiments of the present application.
It should be noted that the above embodiments of the present application may be combined with each other, and cooperate to enable a current to flow through the conductive channel path instead of through the body diode path, so as to reduce injection of non-equilibrium carriers, reduce reverse recovery charges, and improve reverse recovery characteristics, which is not illustrated herein.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be considered as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (9)
1. The super junction MOSFET device is characterized by comprising an N-type epitaxial layer, and a cell region and a terminal region which are positioned on the N-type epitaxial layer; the cell area comprises a first super-junction structure, the upper surfaces of two sides of the first super-junction structure are respectively provided with a first P-type base area, the upper end surface of the middle of the first super-junction structure is provided with a first polysilicon gate, the lower surface and two side surfaces of the first polysilicon gate are respectively provided with a first oxide layer, and the periphery of the first oxide layer is provided with source metal;
the terminal area comprises a second super-junction structure, a second P-type base area is arranged on the upper surface of the second super-junction structure and is in contact with the first P-type base area, a second oxide layer is arranged on the upper surface of the second P-type base area, a second polysilicon grid is arranged on the second oxide layer, and a grid PAD is arranged on the upper surface of the second polysilicon grid;
the first polysilicon gate comprises first N-type polysilicon and first P-type polysilicon positioned on the upper surface of the first N-type polysilicon, the first P-type polysilicon forms ohmic contact with the source metal, and the first N-type polysilicon is connected with the gate PAD through a gate wire;
the second polysilicon gate comprises second N-type polysilicon and second P-type polysilicon positioned on the upper surface of the second N-type polysilicon, and the second P-type polysilicon forms ohmic contact with gate metal on the gate PAD;
and controlling the states of the first polysilicon gate and the second polysilicon gate to form a conductive channel for current to pass on the surface of the first P-type base region.
2. The super-junction MOSFET device of claim 1, wherein the first P-type base region on each side has an N + source region and a P + body region in contact therewith, wherein a portion of an upper surface of the N + source region and a portion of an upper surface of the P + body region on one side are connected to one end of the source metal, and a portion of an upper surface of the N + source region and a portion of an upper surface of the P + body region on the other side are connected to the other end of the source metal.
3. The super junction MOSFET device of claim 1, wherein the thickness of the first oxide layer on both sides of the first polysilicon gate is greater than the thickness of the first oxide layer on the lower surface of the first polysilicon gate.
4. The super junction MOSFET device of claim 1, wherein the first super junction structure comprises a first N-pillar and first P-pillars located on both sides of the first N-pillar, the first N-pillar is a partial region of the N-type epitaxial layer, an upper surface of the first P-pillar on each side is in contact with the first P-type base region located on the same side, and an upper surface of the first N-pillar is in contact with the first oxide layer.
5. The super junction MOSFET device of claim 1, wherein the first N-type polysilicon is phosphorus doped N-type polysilicon and the first P-type polysilicon is boron doped P-type polysilicon.
6. The superjunction MOSFET device of claim 1, wherein the second N-type polysilicon comprises first and second N-type polysilicon regions that are in contact, the second N-type polysilicon region being located at or near a center of the superjunction MOSFET device.
7. The super junction MOSFET device of claim 6, wherein the first N-type polysilicon region is connected to a gate trace, the first N-type polysilicon region has a width equal to the width of the second P-type polysilicon, and the second N-type polysilicon region extends along gate fingers to contact the first N-type polysilicon.
8. The super junction MOSFET device of claim 1, wherein the second super junction structure comprises second N pillars and second P pillars alternately distributed, the second N pillars being a partial region of the N-type epitaxial layer, and an upper surface of each of the second N pillars and an upper surface of each of the second P pillars being in contact with the second P-type base region.
9. A chip comprising the superjunction MOSFET device of any of claims 1 to 8.
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Address after: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee after: Shenzhen Weizhao Semiconductor Co.,Ltd. Address before: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee before: VANGUARD SEMICONDUCTOR CO.,LTD. |
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