CN113325297A - Chip system level test system and method - Google Patents
Chip system level test system and method Download PDFInfo
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Abstract
The invention relates to the field of chip testing, in particular to a system level test system and a method for a chip. A chip system level test system, comprising: the device comprises a module to be tested, a main test module, a test monitoring module and a main control module; the module to be tested is respectively connected with the main test module, the test monitoring module and the main control module; the module to be tested is used for: running system software of a chip to be tested, and testing each interface module of the chip to be tested by cooperating with the main testing module; the test monitoring module is used for analyzing the command of the main control module and executing corresponding operation according to the analyzed command; the main control module is used for: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result. The system can realize the system level test of the chips to be tested, has high universality, and can be used by the main test module which can be increased or decreased according to the test requirements and only correspondingly designing the module to be tested of each chip to be tested.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a system level test system and a method for a chip.
Background
In the existing chip testing field, the following chip tests are common:
1. the application numbers are: 202022189406.2, an SOC chip automation QC apparatus that supports manual start-up testing; the butt joint function with an automatic manipulator is not available, only manual testing can be met, and the efficiency is low; the auxiliary test of programmable logic devices such as FPGA and the like is not available, and the test universality is limited; there is no data gathering and statistics module;
2. the application numbers are: 201810326534.1, system level chip evaluation device and method, which can only complete parameter test and can not complete function test; expensive instruments such as an oscilloscope and a signal generator need to be connected, and the chip test of mass production cannot be put into;
3. the application numbers are: 2010010574415.1A functional test system for SOC, which has no test data collection and statistics module; all test circuits are on the test board, the universality and the development hardware cost are higher; the test adopts the test of peripheral devices or the circuit of the chip, and the coverage rate of the test is limited; there is no unified upgrade function for firmware.
Any of the above schemes cannot complete system level tests of functions and performances of all modules of the chip to be tested, and has poor universality, troublesome firmware upgrade, and the like.
Disclosure of Invention
Therefore, a chip system level test system is needed to be provided to solve the technical problems that the prior art cannot complete the system level test of the functions and the performances of all modules of the chip to be tested, and has poor universality, troublesome firmware upgrade and the like. The specific technical scheme is as follows:
a chip system level test system, comprising: the device comprises a module to be tested, a main test module, a test monitoring module and a main control module;
the module to be tested is respectively connected with the main test module, the test monitoring module and the main control module;
the module to be tested is used for: running system software of a chip to be tested, testing each interface module of the chip to be tested by cooperating with the main test module, and sending test result information to the main control module;
the test monitoring module is connected with the main control module and is used for analyzing the command of the main control module, executing corresponding operation according to the analyzed command and returning an operation result to the main control module;
the main control module is used for: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result.
Further, the test monitoring module further includes: an auxiliary test module;
the auxiliary test module is used for: testing the additional testing requirement which cannot be completed by the main testing module by cooperating with the module to be tested;
and the test results of the auxiliary test module and the main test module are communicated.
Further, the test monitoring module is further configured to: and monitoring the auxiliary test thread of the auxiliary test module.
Further, the main control module is configured to: before the test starts, the data sent by the test monitoring module is verified; if the test is passed, judging whether a test starting command sent by the automatic grabbing equipment is received, and if the test starting command is received, sending a command to the test monitoring module;
the master control module is further configured to: and after all the modules to be tested finish the test, returning test result information to the automatic grabbing equipment.
Furthermore, the number of the modules to be tested is more than two;
the module to be tested is connected with the main control module through a communication concentrator;
the module to be tested is connected with the test monitoring module through a control interface to be tested;
the module to be tested is connected with the main test module through a universal interface;
the main test module includes but is not limited to: and (5) FPGA.
Further, the test monitoring module is further configured to: and upgrading the firmware of the module to be tested and the main test module.
Further, the system software of the chip to be tested includes but is not limited to: basic system software, a test driver of each interface and a test driver of an internal module of a chip to be tested;
the test result information includes but is not limited to: log information, test data.
In order to solve the technical problems, the invention also provides a chip system level test method, which comprises the following specific technical scheme:
a chip system level test method comprises the following steps:
the test monitoring module receives the initialization instruction information and sends data to be verified to the main control module;
the main control module checks the data sent by the test monitoring module; if the test is passed, judging whether a test starting command sent by the automatic grabbing equipment is received, and if the test starting command is received, sending a command to the test monitoring module;
the test monitoring module analyzes the command issued by the main control module, if the command is effective, the module to be tested and the main test module corresponding to the issued command are powered on, and a test result is returned to the main control module.
Further, the method also comprises the following steps:
the main control module receives the test result and executes different operations according to different test results;
the method comprises the following steps of:
when the main control module receives the information that a certain device to be tested sends test completion or test error, the main control module sends a command to the monitoring module to power down the corresponding module to be tested, closes the part of the main test module corresponding to the module to be tested, and cuts off the communication between the module to be tested and the main control module;
and after all the modules to be tested finish testing, the test log of the main control module is written into the file named by the corresponding serial number, and the test result information is returned to the automatic grabbing equipment.
Further, the method also comprises the following steps:
packaging the software of the module to be tested and the main test module into a file system of the test monitoring system, upgrading the monitoring module through the main control module, and issuing a command for upgrading the firmware of the module to be tested and the main test module to the monitoring module after upgrading;
and the monitoring module upgrades the software of the module to be tested and the main test module through an interface and returns an upgrade result to the main control module.
The invention has the beneficial effects that: a chip system level test system, comprising: the device comprises a module to be tested, a main test module, a test monitoring module and a main control module; the module to be tested is respectively connected with the main test module, the test monitoring module and the main control module; the module to be tested is used for: running system software of a chip to be tested, testing each interface module of the chip to be tested by cooperating with the main test module, and sending test result information to the main control module; the test monitoring module is connected with the main control module and is used for analyzing the command of the main control module, executing corresponding operation according to the analyzed command and returning an operation result to the main control module; the main control module is used for: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result. The system can realize the system level test of the chips to be tested, has high universality, and can be used by the main test module which can be increased or decreased according to the test requirements and only correspondingly designing the module to be tested of each chip to be tested.
Furthermore, the auxiliary test module mainly serves specific test requirements of the module to be tested, and if the main test module cannot meet the specific test requirements, the main test module can complete the test through the auxiliary test module, such as USB, MIPI CSI, MIPI DSI and the like, so that the functions in the main test module are universal for most chips to be tested, almost no change can be made on the chips, and the auxiliary test module can be modified correspondingly when different chips to be tested face.
Drawings
FIG. 1 is a block diagram of a system-on-chip test system according to an embodiment of the present invention;
FIG. 2 is a block diagram of a system-on-chip test system according to an embodiment of the present invention, schematically illustrating a module connection 2;
FIG. 3 is a block diagram of a system-on-chip test system according to an embodiment of the present invention, schematically illustrating a module connection 3;
FIG. 4 is a schematic diagram of an interface of a system-on-chip test system according to an embodiment;
FIG. 5 is a flowchart illustrating steps of a method for system-on-chip testing according to an embodiment of the present invention.
Description of reference numerals:
100. a system-on-chip (SOC) test system,
101. a module to be tested is provided with a test module,
102. a main testing module for testing the main testing module,
103. a test monitoring module 1031, an auxiliary test module,
104. and a main control module.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to fig. 4, in the present embodiment, an embodiment of a system-on-chip test system 100 is as follows:
the core technical idea of the application is as follows: a chip system level test system 100 is designed to complete the system level test of the functions and performances of all modules of a chip to be tested, and the system comprises a module to be tested 101, a main test module 102, a test monitoring module 103, a main control module 104, and main modules such as a control interface and a communication concentrator module which are connected with the modules, and can simultaneously control a plurality of chips to be tested, identify the unique code of a system platform, collect test data in real time, automatically control the test flow, complete the test flow of each test function and performance module and the control of test conditions, and count and store the test data, defines a complete communication protocol and has high coupling, and can be compatible only by correspondingly designing the module to be tested 101 aiming at different chips to be tested. The method comprises the following specific steps:
a chip system level test system 100, comprising: the system comprises a module to be tested 101, a main test module 102, a test monitoring module 103 and a main control module 104; the module to be tested 101 is respectively connected with the main test module 102, the test monitoring module 103 and the main control module 104; the module to be tested 101 is configured to: running system software of a chip to be tested, testing each interface module of the chip to be tested by cooperating with the main test module 102, and sending test result information to the main control module 104; the test monitoring module 103 is connected to the main control module 104, and the test monitoring module 103 is configured to analyze a command of the main control module 104, execute a corresponding operation according to the analyzed command, and return an operation result to the main control module 104; the master control module 104 is configured to: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result.
Preferably, as shown in fig. 2, the number of the modules 101 to be tested is two or more, so that the chips to be tested can be simultaneously controlled to be tested, and the operation circuits of the devices to be tested are designed according to the requirement of the space for finally grabbing by the manipulator in the factory by the modules 101 to be tested.
Preferably, the modules 101 to be tested are connected to the main control module 104 through a communication hub, which mainly converts each interface of all the modules 101 to be tested into a USB protocol interface, and finally connects to the main control module 104 through a USB cable through a series of hub combinations, and the main control module 104 identifies the USB device corresponding to each module 101 to be tested, and correspondingly receives log information and test data and issues test current time and random number sequence data.
Preferably, the module to be tested 101 is connected to the test monitoring module 103 through a control interface to be tested.
Preferably, the module to be tested 101 is connected to the main test module 102 through a general-purpose interface. The module to be tested 101 enables the corresponding test module to test in a register reading and writing mode, and obtains a test comparison result and the like. The method mainly comprises the following steps: setting an IO output level as a control pin; enabling a certain receiving module to adopt the output signal of the module to be tested 101 and waiting for the test to be finished to obtain a test result; and enabling a certain test module to output a data sequence of a corresponding time sequence, and closing the corresponding test data output after the module to be tested 101 acquires and compares the data sequence.
Further, the system software of the chip to be tested includes but is not limited to: basic system software, a test driver of each interface and a test driver of an internal module of a chip to be tested; the test result information includes but is not limited to: log information, test data. The method specifically comprises the following steps: the module to be tested 101 mainly realizes the system software operation of the chip to be tested, including the basic system software and the test driver of each interface, and the test driver of the internal module (CPU, GPU, NPU, video coding and decoding, etc.) of the chip to be tested; the test of each interface module is completed by cooperating with the main test module 102; testing with an auxiliary test module 1031 (the auxiliary test module 1031 will be described below) of the test monitoring module 103 through the control interface to be tested; through the communication between the communication hub and the main control module 104, each test result information in the test process is mainly sent to the main control module 104 in real time, and the main control module 104 stops the test and starts the corresponding ending process according to the set test that an error is received.
This case has designed a chip system level test system, accomplishes the system level test of the function and the performance of all modules of the chip that awaits measuring, and this system includes: the system comprises a module to be tested 101, a main test module 102, a test monitoring module 103 and a main control module 104; the module to be tested 101 is connected to the main test module 102, the test monitoring module 103 and the main control module 104 respectively; the module to be tested 101 is configured to: running system software of a chip to be tested, testing each interface module of the chip to be tested by cooperating with the main test module 102, and sending test result information to the main control module 104; the test monitoring module 103 is connected to the main control module 104, and the test monitoring module 103 is configured to analyze a command of the main control module 104, execute a corresponding operation according to the analyzed command, and return an operation result to the main control module 104; the master control module 104 is configured to: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result. The system can realize the system level test of the chips to be tested, has high universality, and the main test module 102 can be increased or decreased according to the test requirements and can be used as long as the module to be tested 101 of each chip to be tested is correspondingly designed.
The following description will be further developed on a pair of the main test module 102, the main control module 104 and the test monitoring module 103:
the test monitoring module 103:
further, in consideration of the practical application process, not all the test requirements can be completed by the cooperation of the main test module 102 and the module to be tested 101. The main test module 102 is mainly responsible for testing the peripheral interface of the module to be tested 101, and mainly comprises an FPGA with a large scale, and can support all digital interface docking tests, including a low-speed general interface and most high-speed interfaces, such as: the HDMI, the MIPI DSI, the MIPI CSI, the EDP and the like can be FPGA board cards with different scale interfaces, and selection is carried out according to the complexity of the module to be tested 101.
Therefore, as shown in fig. 3, the test monitoring module 103 further includes: an auxiliary test module 1031; the auxiliary test module 1031 is configured to: testing the additional testing requirement which cannot be completed by the main testing module 102 in cooperation with the module to be tested 101; the auxiliary test module 1031 communicates with the test results of the main test module 102. The method specifically comprises the following steps:
the auxiliary test module 1031 mainly serves specific test requirements of the module to be tested 101, and if the main test module 102 cannot meet the specific test requirements, such as USB, MIPI CSI, MIPI DSI, and the like, the functions in the main test module 102 are generally used by most chips to be tested, and almost no change is made to the chips, so that the auxiliary test module 1031 is only required to be correspondingly modified for different chips to be tested. Therefore, attention needs to be paid to the main control selection of the test monitoring module 103, and the SOC chip has powerful functions and abundant interfaces as much as possible. Meanwhile, for the chips to be tested of some auxiliary interface chips, the control interface to be tested can configure the chips and start the operation of related tests, the feedback of test results and the like.
Additional test requirements for this section include, but are not limited to: the method comprises the steps of power control of each path of the module to be tested 101, power-on and power-off time sequence control, current monitoring in the testing process, voltage detection, control of other peripheral circuits, information acquisition of a board to be tested and the like. The main control flow is controlled by a monitoring flow, a START command triggers the relevant operation of power-on, and an END command triggers the relevant operation of power-off. If the module to be tested 101 does not have external storage devices such as FLASH, EMMC and the like, the module to be tested 101 can be loaded with test software through interfaces such as USB/SPI and the like by recognizing a special upgrade command.
Further, the test monitoring module 103 further includes: a command parsing module, wherein the command parsing module mainly completes command parsing of the main control module 104, performs corresponding control operations for corresponding commands, and sends back operation results and some key data parameters to the main control module 104 in an ACK command combination manner after completing the control operations.
Meanwhile, the test monitoring module 103 is further configured to: and monitoring the auxiliary test thread of the auxiliary test module 1031. And each state stage checks whether the state of the auxiliary test flow is correct or not, and also can confirm whether the thread can carry out normal auxiliary test or not, so that the false test state is prevented. And the current monitoring state is convenient to debug and manually test and observe through visual display modes such as LED lamps and the like.
Further, the test monitoring module 103 may further include: module to be tested 101 information collection module, module to be tested 101 information collection module is used for: software version information collection and auxiliary test random number generation values of the module to be tested 101, the main test module and the test monitoring module 103; the information is acquired after the platform is powered on, namely the acquisition is finished before the test flow is started.
The main control module 104 is explained below:
the master control module 104 is configured to: before the test starts, the data sent by the test monitoring module 103 is verified; if the test is passed, whether a test starting command sent by the automatic grabbing equipment is received is judged, and if the test starting command is received, the command is sent to the test monitoring module 103;
the master control module 104 is further configured to: and when all the modules 101 to be tested finish the test, returning test result information to the automatic grabbing equipment.
The actual operation process is as follows:
1. the start button is pressed down, the configured serial number, number and test version information of the device to be tested are sent to the test monitoring module 103 through an INIT command, the test monitoring module 103 receives the INIT command, the information of the board to be tested, the version of the main test module 102 and the version information of the monitoring module, which are acquired by electrifying, are sent to the main control module 104 through an ACK INIT command, the checking is normally carried out, the state is ready, and otherwise, an error is reported.
2. The main control module 104 waits for the automatic grabbing equipment to send a starting test command after entering a ready state, after receiving the starting test command, the test monitoring module 103 is informed through the START command, after receiving the command, the test monitoring module 103 analyzes effectively, then the corresponding to-be-tested module 101 in the START command is electrified, each path of voltage and current parameter detection is carried out, normally, ACK START OK information is returned to the main control module 104, otherwise, ACK START ERR and related abnormal serial numbers are returned, the main control module 104 receives test log information of each to-be-tested module 101 according to the fact that the ACK information is correct, analyzes the test log information, and otherwise, an error is reported.
3. When the main control module 104 receives information that a certain device to be tested sends test completion or test error, the main control module 104 sends an END + module to be tested 101 number to the test monitoring module 103, the test monitoring module 103 powers down the corresponding module to be tested 101 after analyzing the command correctly, simultaneously closes the part of the main test module 102 corresponding to the module to be tested 101, simultaneously cuts off the communication between the module to be tested 101 and the main control module, ensures that a chip to be tested is damaged without leakage, and acquires the voltage after power down to ensure that the material is changed without electricity. The power down returns to the main control module 104ACK END OK, otherwise ACK END ERR is returned.
4. After all the started modules to be tested 101 are tested normally, the main control module 104 finishes the test of the current round, writes the test logs into the files named by the corresponding serial numbers, returns the test result information to the automatic grabbing equipment and informs the equipment of material change; and after the test monitoring equipment detects that all started equipment to be tested normally end, returning the whole monitoring process to the initial ready state of receiving the START/INIT command.
the main test module 102 is further connected to the test monitoring module 103 through a general interface, and indirectly communicates with the auxiliary test modules 1031 in a register reading and writing manner, so as to achieve the purpose of test start and test result intercommunication of each auxiliary test module 1031, and reading the version information of the main test module 102 is also completed through the interface.
The main test module 102 is also connected to each module 101 to be tested through a general interface, and the module 101 to be tested enables the corresponding test module to test, and obtains the test comparison result and the like through a register read-write mode. The method mainly comprises the following steps: setting an IO output level as a control pin; enabling a certain receiving module to adopt the output signal of the module to be tested 101 and waiting for the test to be finished to obtain a test result; and enabling a certain test module to output a data sequence of a corresponding time sequence, and closing the corresponding test data output after the module to be tested 101 acquires and compares the data sequence.
As shown in fig. 4, which is an interactive interface schematic diagram in an actual application process, it should be noted that different interactive interface schematic diagrams may be designed according to actual application needs, and may generally include these functions: starting test, stopping control, displaying test results, selecting the module to be tested 101, configuring communication interface parameters and the like.
The test process can be controlled by sending an INIT \ START \ END specific command sequence, receiving an ACK command of the test monitoring module 103, analyzing and acquiring corresponding data information such as test parameters, software and hardware versions, platform numbers and the like, receiving test log information of the module to be tested 101, acquiring test items, test results and some special key data information needing to be recorded from a large amount of log information, and recording and storing complete log information for subsequent query and statistics.
The system can be in seamless communication and butt joint with a manipulator machine table of a sealing test factory, automatically completes the function and performance test of a complex SOC chip, and has perfect communication flows of all modules, so that all modules can work smoothly and cooperatively. Meanwhile, the whole test process is controllable, data collection and statistics are carried out to generate reports, and powerful data support is provided for subsequent links such as test software optimization, bad film analysis and bad film tracing. The universality of the whole system is strong, the main test module 102 can be increased or decreased according to the test requirements, and the main test module can be used only by correspondingly designing the module to be tested 101 of each chip to be tested, so that the high hardware and software development cost generated between project transplantation is saved.
Further, the test monitoring module 103 is further configured to: and upgrading the firmware of the module to be tested 101 and the main test module 102. The method specifically comprises the following steps: the software of the module to be tested 101 and the main test module 102 is packaged into a file system of the test monitoring module 103, the test monitoring module 103 is upgraded through the main control module 104, a command for upgrading the firmware of the module to be tested 101 and the main test module 102 is sent out after the upgrade is completed, the test monitoring module 103 receives the command and then upgrades the firmware for the corresponding module through interface modes such as spi \ usb \ flash and the like, and the corresponding result is returned to the main control module 104 after the upgrade is completed. The upgrading is a one-key mode, the operation difficulty of a factory line operator is reduced, and errors in the operation process are prevented due to the fact that the firmware is packaged. The switching of the operation process and the slow firmware downloading factor of the PC tool normally used by the FPGA are omitted, so that the whole upgrading process is more efficient. Through the operation of the main control module tool, the test monitoring module 103 can complete the firmware upgrade of the module to be tested 101 and the main test module, so that the firmware on the factory production line can be updated conveniently and safely.
Referring to fig. 5, in the present embodiment, a chip system level testing method can be applied to the above-mentioned chip system level testing system. The method comprises the following specific steps:
step S501: the test monitoring module receives the initialization instruction information and sends data to be verified to the main control module.
Step S502: the main control module checks the data sent by the test monitoring module; if the test is passed, whether a test starting command sent by the automatic grabbing equipment is received is judged, and if the test starting command is received, the command is sent to the test monitoring module.
Step S503: the test monitoring module analyzes the command issued by the main control module, if the command is effective, the module to be tested and the main test module corresponding to the issued command are powered on, and a test result is returned to the main control module.
Further, the method also comprises the following steps:
the main control module receives the test result and executes different operations according to different test results;
the method comprises the following steps of:
when the main control module receives the information that a certain device to be tested sends test completion or test error, the main control module sends a command to the monitoring module to power down the corresponding module to be tested, closes the part of the main test module corresponding to the module to be tested, and cuts off the communication between the module to be tested and the main control module;
and after all the modules to be tested finish testing, the test log of the main control module is written into the file named by the corresponding serial number, and the test result information is returned to the automatic grabbing equipment.
The actual operation process is as follows:
1. and pressing a start button, sending the configured serial number, number and test version information of the equipment to be tested to the test monitoring module through an INIT command, sending the information of the board to be tested, the version of the main test module and the version information of the monitoring module, which are acquired by electrifying, to the main control module through an ACK INIT command after the test monitoring module receives the INIT command, checking to enter a ready state normally, and otherwise, reporting an error.
2. The main control module waits for the automatic grabbing equipment to send a starting test command after entering a ready state, the test monitoring module is informed through the START command after receiving the command, the test monitoring module conducts electrification, voltage and current parameter detection on the corresponding modules to be tested in the START command if analyzing is effective after receiving the command, ACK START OK information is returned to the main control module if normal, otherwise ACK START ERR and relevant abnormal sequence numbers are returned, the main control module receives test log information of each module to be tested according to the ACK information, and analyzes the test log information, otherwise, an error is reported.
3. When the main control module receives information that a certain device to be tested sends test completion or test errors, the main control module sends an END + module to be tested serial number to the test monitoring module, the test monitoring module powers off the corresponding module to be tested after analyzing the command correctly, meanwhile, the part of the main test module corresponding to the module to be tested is closed, meanwhile, communication between the module to be tested and the main control module is cut off, it is ensured that no leakage damages a chip to be tested, and voltage is collected after power off to ensure no-power reloading. The power-off is normal and returns to the main control module ACK END OK, otherwise it returns ACK END ERR.
4. After all started modules to be tested are tested normally, the main control module finishes the test of the current round, writes the test logs into the files named by the corresponding serial numbers, returns the test result information to the automatic grabbing equipment and informs the equipment of material change; and after the test monitoring equipment detects that all started equipment to be tested normally end, returning the whole monitoring process to the initial ready state of receiving the START/INIT command.
Further, the method also comprises the following steps:
packaging the software of the module to be tested and the main test module into a file system of the test monitoring system, upgrading the monitoring module through the main control module, and issuing a command for upgrading the firmware of the module to be tested and the main test module to the monitoring module after upgrading;
and the monitoring module upgrades the software of the module to be tested and the main test module through an interface and returns an upgrade result to the main control module.
The method specifically comprises the following steps: the software of the module to be tested and the software of the main test module are packaged into a file system of the test monitoring module, the test monitoring module is upgraded through the main control module, a command for upgrading the firmware of the module to be tested and the firmware of the main test module is sent out after the upgrading is finished, the test monitoring module receives the command and then upgrades the firmware of the corresponding module through interface modes of spi \ usb \ flash and the like, and the corresponding result is returned to the main control module after the upgrading is finished. The upgrading is a one-key mode, the operation difficulty of a factory line operator is reduced, and errors in the operation process are prevented due to the fact that the firmware is packaged. The switching of the operation process and the slow firmware downloading factor of the PC tool normally used by the FPGA are omitted, so that the whole upgrading process is more efficient. Through the tool operation of the main control module, the test monitoring module can complete the firmware upgrade of the module to be tested and the main test module, so that the firmware on a factory production line is updated conveniently and safely.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (10)
1. A system-on-chip test system, comprising: the device comprises a module to be tested, a main test module, a test monitoring module and a main control module;
the module to be tested is respectively connected with the main test module, the test monitoring module and the main control module;
the module to be tested is used for: running system software of a chip to be tested, testing each interface module of the chip to be tested by cooperating with the main test module, and sending test result information to the main control module;
the test monitoring module is connected with the main control module and is used for analyzing the command of the main control module, executing corresponding operation according to the analyzed command and returning an operation result to the main control module;
the main control module is used for: and receiving the test result information and the operation result, and executing different operations according to the test result information and the operation result.
2. The chip system level test system of claim 1, wherein the test monitoring module further comprises: an auxiliary test module;
the auxiliary test module is used for: testing the additional testing requirement which cannot be completed by the main testing module by cooperating with the module to be tested;
and the test results of the auxiliary test module and the main test module are communicated.
3. The chip system level test system of claim 2, wherein the test monitoring module is further configured to: and monitoring the auxiliary test thread of the auxiliary test module.
4. The chip system-on-chip test system of claim 1, wherein the main control module is configured to: before the test starts, the data sent by the test monitoring module is verified; if the test is passed, judging whether a test starting command sent by the automatic grabbing equipment is received, and if the test starting command is received, sending a command to the test monitoring module;
the master control module is further configured to: and after all the modules to be tested finish the test, returning test result information to the automatic grabbing equipment.
5. The system-on-chip test system of claim 1,
the number of the modules to be tested is more than two;
the module to be tested is connected with the main control module through a communication concentrator;
the module to be tested is connected with the test monitoring module through a control interface to be tested;
the module to be tested is connected with the main test module through a universal interface;
the main test module includes but is not limited to: and (5) FPGA.
6. The chip system level test system of claim 1, wherein the test monitoring module is further configured to: and upgrading the firmware of the module to be tested and the main test module.
7. The system-on-chip test system of claim 1,
the system software of the chip to be tested includes but is not limited to: basic system software, a test driver of each interface and a test driver of an internal module of a chip to be tested;
the test result information includes but is not limited to: log information, test data.
8. A chip system level test method is characterized by comprising the following steps:
the test monitoring module receives the initialization instruction information and sends data to be verified to the main control module;
the main control module checks the data sent by the test monitoring module; if the test is passed, judging whether a test starting command sent by the automatic grabbing equipment is received, and if the test starting command is received, sending a command to the test monitoring module;
the test monitoring module analyzes the command issued by the main control module, if the command is effective, the module to be tested and the main test module corresponding to the issued command are powered on, and a test result is returned to the main control module.
9. The chip system level testing method according to claim 8, further comprising the steps of:
the main control module receives the test result and executes different operations according to different test results;
the method comprises the following steps of:
when the main control module receives the information that a certain device to be tested sends test completion or test error, the main control module sends a command to the monitoring module to power down the corresponding module to be tested, closes the part of the main test module corresponding to the module to be tested, and cuts off the communication between the module to be tested and the main control module;
and after all the modules to be tested finish testing, the test log of the main control module is written into the file named by the corresponding serial number, and the test result information is returned to the automatic grabbing equipment.
10. The chip system level testing method according to claim 8, further comprising the steps of:
packaging the software of the module to be tested and the main test module into a file system of the test monitoring system, upgrading the monitoring module through the main control module, and issuing a command for upgrading the firmware of the module to be tested and the main test module to the monitoring module after upgrading;
and the monitoring module upgrades the software of the module to be tested and the main test module through an interface and returns an upgrade result to the main control module.
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| CN116738020A (en) * | 2023-04-17 | 2023-09-12 | 深圳市晶存科技有限公司 | Method, system, device and storage medium for displaying chip test result |
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