CN113315507A - Two-dimensional material light-operated logic gate - Google Patents
Two-dimensional material light-operated logic gate Download PDFInfo
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- CN113315507A CN113315507A CN202110566411.7A CN202110566411A CN113315507A CN 113315507 A CN113315507 A CN 113315507A CN 202110566411 A CN202110566411 A CN 202110566411A CN 113315507 A CN113315507 A CN 113315507A
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Abstract
The invention discloses a two-dimensional material light-operated logic gate, which comprises a first photosensitive layer, a first electrode, a second electrode, a third electrode and a fourth electrode, wherein the first photosensitive layer, the first electrode, the second electrode, the third electrode and the fourth electrode are integrated on a first substrate; a second photosensitive layer, a fifth electrode and a sixth electrode integrated on the second substrate; the first photosensitive layer and the second photosensitive layer are both made of two-dimensional materials; the first substrate, the first photosensitive layer, the first electrode and the second electrode form a first phototransistor; the first substrate, the first photosensitive layer, the second electrode and the third electrode form a second phototransistor; the first substrate, the first photosensitive layer, the third electrode and the fourth electrode form a third phototransistor; the second substrate, the second photosensitive layer, the fifth electrode and the sixth electrode form a fourth phototransistor; the first phototransistor, the second phototransistor and the third phototransistor are connected in series; the third phototransistor is connected in parallel with the fourth phototransistor. The two-dimensional material light-operated logic gate has the advantages of simple preparation process, small device volume and contribution to large-scale integration.
Description
Technical Field
The invention relates to the technical field of semiconductor photoelectric integration and logic operation, in particular to a two-dimensional material light-operated logic gate.
Background
Logic Gates (Logic Gates) are the basic components on Integrated circuits (Integrated circuits). A simple logic gate may be comprised of transistors. The combination of these transistors may cause the high and low levels representing both signals to produce a high or low level signal after passing through them. The high and low levels may represent logical "true" and "false" or 1 and 0 in binary, respectively, to implement a logical operation.
Current research on semiconductor materials is largely limited to single electronic or optical component applications with limited functionality, which greatly limits their future development as replacements for traditional silicon-based materials for integrated circuits. And the existing logic gate has the problems of complex preparation process, large device volume and inconvenience for large-scale integration.
Disclosure of Invention
The invention provides a two-dimensional material light-operated logic gate, which aims to solve the technical problems that the existing logic gate is complex in preparation process, large in device size and not beneficial to large-scale integration.
In order to solve the technical problems, the invention provides the following technical scheme:
a two-dimensional material light-operated logic gate comprises a first substrate and a second substrate, wherein a first photosensitive layer, a first electrode, a second electrode, a third electrode and a fourth electrode are integrated on the first substrate; a second photosensitive layer, a fifth electrode and a sixth electrode are integrated on the second substrate; wherein the first and second photosensitive layers are both made of a two-dimensional photosensitive material;
the first substrate, the first photosensitive layer, the first electrode and the second electrode form a first phototransistor; the first substrate, the first photosensitive layer, the second electrode and the third electrode form a second phototransistor; the first substrate, the first photosensitive layer, the third electrode and the fourth electrode form a third phototransistor; the second substrate, the second photosensitive layer, the fifth electrode and the sixth electrode form a fourth phototransistor;
the first substrate serves as a gate of the first, second and third phototransistors, and the first photoactive layer serves as a channel of the first, second and third phototransistors; the first electrode and the second electrode are used as a source electrode and a drain electrode of the first phototransistor, respectively; the second electrode and the third electrode serve as a source and a drain of the second phototransistor, respectively; the third electrode and the fourth electrode serve as a source and a drain of a third phototransistor, respectively; the second substrate serves as a gate of the fourth phototransistor, the second photoactive layer serves as a channel of the fourth phototransistor, and the fifth and sixth electrodes serve as a source and a drain of the fourth phototransistor, respectively;
the first phototransistor, the second phototransistor, and the third phototransistor are connected in series; the third phototransistor is connected in parallel with the fourth phototransistor.
Optionally, the channel widths of the first phototransistor, the second phototransistor, the third phototransistor, and the fourth phototransistor are respectively 2 μm to 3 μm.
Further, the third electrode and the sixth electrode, and the fourth electrode and the fifth electrode are respectively connected through a connecting wire.
Optionally, the connection wire is a gold metal wire.
Optionally, the first photosensitive layer and the second photosensitive layer have a thickness of 3nm to 30nm and a length of 20 μm to 30 μm, respectively.
Optionally, the lowest layer of the first substrate is silicon, and a layer of silicon dioxide is arranged above the silicon.
Optionally, the lowest layer of the second substrate is silicon, and a layer of silicon dioxide is arranged above the silicon.
Optionally, the first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode, and the sixth electrode are all gold metal electrodes.
The technical scheme provided by the invention has the beneficial effects that at least:
the two-dimensional material light-operated logic gate of the invention irradiates a light signal to a channel material of a specific phototransistor in the form of light source spots, and enables the phototransistor to generate photocurrent through the input of the light signal and the magnitude of light power, so that the resistance of the phototransistor is changed, and the output of high and low levels is obtained. The two end electrodes of the corresponding phototransistors are used as nodes, and signals are transmitted and output through the connection of various phototransistors in different modes, so that the signal output of the photoelectric integration and light-operated logic circuit is finally realized. The method has the advantages of simple preparation process, small device volume and contribution to large-scale integration.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a two-dimensional material light-operated logic gate circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an infrared light-regulating not gate logic circuit according to an embodiment of the present invention.
Description of reference numerals:
1. a first substrate; 2. a first photosensitive layer; 3. a first electrode; 4. a second electrode; 5. a third electrode;
6. a fourth electrode; 7. connecting a lead; 8. a second substrate; 9. a second photosensitive layer;
10. a fifth electrode; 11. and a sixth electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
For the principle of the logic circuit, the design of the embodiment proposes that the optical control logic gate circuit is realized by the switch of the optical signal. The method is characterized in that an optical sensitive material (two-dimensional material) with a corresponding waveband is selected to prepare a phototransistor, the channel photocurrent and the resistance of the phototransistor are changed through the optical switch and the optical power, the output of high and low levels of different transistors is finally realized, and the logic operation is finally realized. And the optical waves of different wave bands and corresponding optical sensitive materials are selected, so that the logic operation of different wave bands can be realized. By realizing multiband NOT gates, NAND gates, NOR gates and other logic circuits, a new research direction is provided for the integration of two-dimensional logic circuits in the future.
As shown in fig. 1, the two-dimensional material light-operated logic gate of this embodiment includes a first substrate 1 and a second substrate 8, where the first substrate 1 is integrated with a first photosensitive layer 2, a first electrode 3, a second electrode 4, a third electrode 5, and a fourth electrode 6; a second photosensitive layer 9, a fifth electrode 10 and a sixth electrode 11 are integrated on the second substrate 8; wherein the first photosensitive layer 2 and the second photosensitive layer 9 are both made of two-dimensional photosensitive materials; based on this, the present embodiment constitutes a phototransistor by a substrate, a photosensitive layer made of a two-dimensional material, and electrodes at both ends; the substrate is used as a grid electrode of the photoelectric transistor, the two-dimensional material is used as a channel of the photoelectric transistor, electrodes at two ends are respectively used as a source electrode and a drain electrode of the photoelectric transistor, and the width of the channel can be adjusted through the distance between the source electrode and the drain electrode, and is specifically 2-3 μm.
Specifically, the first substrate 1, the first photosensitive layer 2, the first electrode 3, and the second electrode 4 constitute a first phototransistor; the first substrate 1, the first photosensitive layer 2, the second electrode 4 and the third electrode 5 constitute a second phototransistor; the first substrate 1, the first photosensitive layer 2, the third electrode 5 and the fourth electrode 6 constitute a third phototransistor; the second substrate 8, the second photosensitive layer 9, the fifth electrode 10 and the sixth electrode 11 constitute a fourth phototransistor; wherein the first substrate 1 serves as a gate of the first phototransistor, the second phototransistor, and the third phototransistor, and the first photoactive layer 2 serves as a channel of the first phototransistor, the second phototransistor, and the third phototransistor; the first electrode 3 and the second electrode 4 serve as a source and a drain of the first phototransistor, respectively; the second electrode 4 and the third electrode 5 serve as a source and a drain of the second phototransistor, respectively; the third electrode 5 and the fourth electrode 6 function as a source and a drain of the third phototransistor, respectively; the second substrate 8 serves as the gate of the fourth phototransistor, the second photoactive layer 9 serves as the channel of the fourth phototransistor, and the fifth electrode 10 and the sixth electrode 11 serve as the source and the drain, respectively, of the fourth phototransistor.
Further, the first phototransistor, the second phototransistor, and the third phototransistor are connected in series by connecting the first electrode 3, the second electrode 4, the third electrode 5, and the fourth electrode 6. The third phototransistor and the fourth phototransistor are connected in parallel via a connection wire 7 between the third electrode 5 and the sixth electrode 11, and a connection wire 7 between the fourth electrode 6 and the fifth electrode 10.
The first photosensitive layer 2 and the second photosensitive layer 9 are both two-dimensional materials, the two-dimensional materials are photosensitive materials, and can generate photon-generated carriers under the action of optical signals, and the photon-generated carriers move directionally under the action of bias voltage to generate photocurrent, so that the level of output level is changed. The optical signal is irradiated to the channel material of a specific phototransistor in the form of light source spots, and the phototransistor generates photocurrent through the input of the optical signal and the magnitude of optical power, so that the resistance of the phototransistor is changed, and then the output of high and low levels is obtained. The two end electrodes of the corresponding phototransistors are used as nodes, and signals are transmitted and output through the connection of various phototransistors in different modes, so that the signal output of the photoelectric integration and light-operated logic circuit is finally realized.
The two-dimensional material can be made of sensitive materials with different wave bands, so that logical operation of different wave bands is realized. Optionally, the substrate is an insulating substrate, and the lowest layer of the substrate is silicon and a layer of silicon dioxide is arranged on the substrate. The first electrode 3, the second electrode 4, the third electrode 5, the fourth electrode 6, the fifth electrode 10, and the sixth electrode 11 are all gold metal electrodes. The connecting wire 7 is a gold metal wire. The first photosensitive layer 2 and the second photosensitive layer 9 made of the two-dimensional material have a thickness of 3nm to 30nm, respectively, and a length of 20 to 30 μm, respectively.
In order to further explain the working principle of the two-dimensional material light-operated logic gate of the present embodiment, a visible light-controlled nand gate logic circuit, a visible light-controlled nor gate logic circuit, an infrared light-controlled nor gate logic circuit, and an infrared light-controlled nor gate logic circuit are taken as examples, and the two-dimensional material light-operated logic gate is specifically explained.
One, visible light control NAND gate logic circuit
As shown in fig. 1, the visible light-controlled nand gate logic circuit includes a first substrate 1 and a second substrate 8, wherein a first photosensitive layer 2, a first electrode 3, a second electrode 4, a third electrode 5 and a fourth electrode 6 are integrated on the first substrate 1; a second photosensitive layer 9, a fifth electrode 10 and a sixth electrode 11 are integrated on the second substrate 8; the first photosensitive layer 2 and the second photosensitive layer 9 are both two-dimensional materials, and specifically, in the visible light modulation and control nand gate logic circuit, the two-dimensional material selected is molybdenum disulfide; the material can realize photoelectric induction of visible light wave band. Under the action of visible light signals, photon-generated carriers can be generated, and the photon-generated carriers move directionally under the action of bias voltage to generate photocurrent, so that the level of an output level is changed, and logic operation is realized. And the substrate is an insulating substrate, the lowest layer of the substrate is silicon, the upper layer of the substrate is silicon dioxide, the first electrode 3, the second electrode 4, the third electrode 5, the fourth electrode 6, the connecting lead 7, the fifth electrode 9 and the sixth electrode 10 are all made of gold metal, the thickness of the first photosensitive layer 2 and the thickness of the second photosensitive layer 9 are 3nm-30nm, and the length of the first photosensitive layer and the second photosensitive layer is 20 mu m-30 mu m.
Based on the above, the visible light control nand gate logic circuit comprises a phototransistor through a substrate, a photosensitive layer made of a two-dimensional material and electrodes at two ends; the substrate is used as a grid electrode of the photoelectric transistor, the two-dimensional material is used as a channel of the photoelectric transistor, electrodes at two ends are respectively used as a source electrode and a drain electrode of the photoelectric transistor, and the width of the channel can be adjusted through the distance between the source electrode and the drain electrode, and is specifically 2-3 μm.
Specifically, the first substrate 1, the first photosensitive layer 2, the first electrode 3, and the second electrode 4 constitute a first phototransistor; the first substrate 1, the first photosensitive layer 2, the second electrode 4 and the third electrode 5 constitute a second phototransistor; the first substrate 1, the first photosensitive layer 2, the third electrode 5 and the fourth electrode 6 constitute a third phototransistor; the second substrate 8, the second photosensitive layer 9, the fifth electrode 10 and the sixth electrode 11 constitute a fourth phototransistor; wherein the first substrate 1 serves as a gate of the first phototransistor, the second phototransistor, and the third phototransistor, and the first photoactive layer 2 serves as a channel of the first phototransistor, the second phototransistor, and the third phototransistor; the first electrode 3 and the second electrode 4 serve as a source and a drain of the first phototransistor, respectively; the second electrode 4 and the third electrode 5 serve as a source and a drain of the second phototransistor, respectively; the third electrode 5 and the fourth electrode 6 function as a source and a drain of the third phototransistor, respectively; the second substrate 8 serves as the gate of the fourth phototransistor, the second photoactive layer 9 serves as the channel of the fourth phototransistor, and the fifth electrode 10 and the sixth electrode 11 serve as the source and the drain, respectively, of the fourth phototransistor.
Further, the first phototransistor, the second phototransistor, and the third phototransistor are connected in series by connecting the first electrode 3, the second electrode 4, the third electrode 5, and the fourth electrode 6. The third phototransistor and the fourth phototransistor are connected in parallel through the connecting wire 7 of the third electrode 5 and the sixth electrode 11, and the connecting wire 7 of the fourth electrode 6 and the fifth electrode 10. The first electrode 3 is a ground terminal GND, the third electrode 5 is an output terminal VOUT, and the fourth electrode 6 is a bias voltage terminal VDD.
When the visible light signal is input into the third phototransistor and the fourth phototransistor in the form of light source spots, the output terminal VOUT outputs a bias voltage VDD, that is, a logic output 1; when a visible light signal is input into the first phototransistor and the fourth phototransistor in the form of a light source spot, the output terminal VOUT outputs a bias voltage VDD, that is, a logic output 1; when the visible light signal is input into the second phototransistor and the third phototransistor in the form of light source spots, the output terminal VOUT outputs a bias voltage VDD, i.e., a logic output 1; when the visible light signal is input to the first phototransistor and the second phototransistor in the form of a light source spot, the output terminal VOUT outputs a ground signal GND, i.e., a logic output 0. Specifically, the truth table of the visible light-controlled nand gate logic circuit is shown in table 1.
TABLE 1 truth table of visible light-controlled NAND gate logic circuit
Two, visible light control NOR gate logic circuit
As shown in fig. 1, the visible light-controlled nor logic circuit includes a first substrate 1 and a second substrate 8, wherein a first photosensitive layer 2, a first electrode 3, a second electrode 4, a third electrode 5 and a fourth electrode 6 are integrated on the first substrate 1; a second photosensitive layer 9, a fifth electrode 10 and a sixth electrode 11 are integrated on the second substrate 8; the first photosensitive layer 2 and the second photosensitive layer 9 are both two-dimensional materials, and specifically, in the visible light control nor logic circuit, the two-dimensional material selected is molybdenum disulfide; the material can realize photoelectric induction of visible light wave band. Under the action of visible light signals, photon-generated carriers can be generated, and the photon-generated carriers move directionally under the action of bias voltage to generate photocurrent, so that the level of an output level is changed, and logic operation is realized. And the substrate is an insulating substrate, the lowest layer of the substrate is silicon, the upper layer of the substrate is silicon dioxide, the first electrode 3, the second electrode 4, the third electrode 5, the fourth electrode 6, the connecting lead 7, the fifth electrode 9 and the sixth electrode 10 are all made of gold metal, the thickness of the first photosensitive layer 2 and the thickness of the second photosensitive layer 9 are 3nm-30nm, and the length of the first photosensitive layer and the second photosensitive layer is 20 mu m-30 mu m.
Based on the above, the visible light control nor gate logic circuit comprises a phototransistor through a substrate, a photosensitive layer made of a two-dimensional material and electrodes at two ends; the substrate is used as a grid electrode of the photoelectric transistor, the two-dimensional material is used as a channel of the photoelectric transistor, electrodes at two ends are respectively used as a source electrode and a drain electrode of the photoelectric transistor, and the width of the channel can be adjusted through the distance between the source electrode and the drain electrode, and is specifically 2-3 μm.
Specifically, the first substrate 1, the first photosensitive layer 2, the first electrode 3, and the second electrode 4 constitute a first phototransistor; the first substrate 1, the first photosensitive layer 2, the second electrode 4 and the third electrode 5 constitute a second phototransistor; the first substrate 1, the first photosensitive layer 2, the third electrode 5 and the fourth electrode 6 constitute a third phototransistor; the second substrate 8, the second photosensitive layer 9, the fifth electrode 10 and the sixth electrode 11 constitute a fourth phototransistor; wherein the first substrate 1 serves as a gate of the first phototransistor, the second phototransistor, and the third phototransistor, and the first photoactive layer 2 serves as a channel of the first phototransistor, the second phototransistor, and the third phototransistor; the first electrode 3 and the second electrode 4 serve as a source and a drain of the first phototransistor, respectively; the second electrode 4 and the third electrode 5 serve as a source and a drain of the second phototransistor, respectively; the third electrode 5 and the fourth electrode 6 function as a source and a drain of the third phototransistor, respectively; the second substrate 8 serves as the gate of the fourth phototransistor, the second photoactive layer 9 serves as the channel of the fourth phototransistor, and the fifth electrode 10 and the sixth electrode 11 serve as the source and the drain, respectively, of the fourth phototransistor.
Further, the first phototransistor, the second phototransistor, and the third phototransistor are connected in series by connecting the first electrode 3, the second electrode 4, the third electrode 5, and the fourth electrode 6. The third phototransistor and the fourth phototransistor are connected in parallel through the connecting wire 7 of the third electrode 5 and the sixth electrode 11, and the connecting wire 7 of the fourth electrode 6 and the fifth electrode 10. The fourth electrode 6 is a ground GND, the third electrode 5 is an output terminal VOUT, and the first electrode 3 is a bias voltage terminal VDD.
When a visible light signal is input into the first phototransistor and the second phototransistor in the form of a light source spot, the output terminal VOUT outputs a bias voltage VDD, that is, a logic output 1; when a visible light signal is input into the second phototransistor and the fourth phototransistor in the form of a light source spot, the output end VOUT outputs a ground GND, namely a logic output 0; when a visible light signal is input into the first phototransistor and the third phototransistor in the form of a light source spot, the output end VOUT outputs a ground GND, namely a logic output 0; when the visible light signal is input to the third phototransistor and the fourth phototransistor in the form of a light source spot, the output terminal VOUT outputs a ground signal GND, i.e., a logic output 0. Specifically, the truth table of the visible light-controlled nor gate logic circuit is shown in table 2.
TABLE 2 truth table of visible light-controlled NOR gate logic circuit
Three, infrared light regulation NOR gate logic circuit
As shown in fig. 1, the infrared light-regulating nor gate logic circuit includes a first substrate 1 and a second substrate 8, wherein a first photosensitive layer 2, a first electrode 3, a second electrode 4, a third electrode 5 and a fourth electrode 6 are integrated on the first substrate 1; a second photosensitive layer 9, a fifth electrode 10 and a sixth electrode 11 are integrated on the second substrate 8; the first photosensitive layer 2 and the second photosensitive layer 9 are both two-dimensional materials, and specifically, in the infrared light regulating nor gate logic circuit, the two-dimensional material selected is molybdenum ditelluride; the material can realize photoelectric induction of infrared bands. Under the action of the infrared light signal, photon-generated carriers can be generated, and the photon-generated carriers move directionally under the action of bias voltage to generate photocurrent, so that the level of an output level is changed, and logic operation is realized. And the substrate is an insulating substrate, the lowest layer of the substrate is silicon, the upper layer of the substrate is silicon dioxide, the first electrode 3, the second electrode 4, the third electrode 5, the fourth electrode 6, the connecting lead 7, the fifth electrode 9 and the sixth electrode 10 are all made of gold metal, the thickness of the first photosensitive layer 2 and the thickness of the second photosensitive layer 9 are 3nm-30nm, and the length of the first photosensitive layer and the second photosensitive layer is 20 mu m-30 mu m.
Based on the above, the infrared light regulating nor gate logic circuit comprises a phototransistor through a substrate, a photosensitive layer made of a two-dimensional material and electrodes at two ends; the substrate is used as a grid electrode of the photoelectric transistor, the two-dimensional material is used as a channel of the photoelectric transistor, electrodes at two ends are respectively used as a source electrode and a drain electrode of the photoelectric transistor, and the width of the channel can be adjusted through the distance between the source electrode and the drain electrode, and is specifically 2-3 μm.
Specifically, the first substrate 1, the first photosensitive layer 2, the first electrode 3, and the second electrode 4 constitute a first phototransistor; the first substrate 1, the first photosensitive layer 2, the second electrode 4 and the third electrode 5 constitute a second phototransistor; the first substrate 1, the first photosensitive layer 2, the third electrode 5 and the fourth electrode 6 constitute a third phototransistor; the second substrate 8, the second photosensitive layer 9, the fifth electrode 10 and the sixth electrode 11 constitute a fourth phototransistor; wherein the first substrate 1 serves as a gate of the first phototransistor, the second phototransistor, and the third phototransistor, and the first photoactive layer 2 serves as a channel of the first phototransistor, the second phototransistor, and the third phototransistor; the first electrode 3 and the second electrode 4 serve as a source and a drain of the first phototransistor, respectively; the second electrode 4 and the third electrode 5 serve as a source and a drain of the second phototransistor, respectively; the third electrode 5 and the fourth electrode 6 function as a source and a drain of the third phototransistor, respectively; the second substrate 8 serves as the gate of the fourth phototransistor, the second photoactive layer 9 serves as the channel of the fourth phototransistor, and the fifth electrode 10 and the sixth electrode 11 serve as the source and the drain, respectively, of the fourth phototransistor.
Further, the first phototransistor, the second phototransistor and the third phototransistor are connected in series through the connection of the first electrode 3, the second electrode 4, the third electrode 5 and the fourth electrode 4. The third phototransistor and the fourth phototransistor are connected in parallel through the connecting wire 7 of the third electrode 5 and the sixth electrode 11, and the connecting wire 7 of the fourth electrode 6 and the fifth electrode 10. The fourth electrode 6 is a ground GND, the third electrode 5 is an output terminal VOUT, and the first electrode 3 is a bias voltage terminal VDD.
When an infrared optical signal is input into the first phototransistor and the second phototransistor in the form of a light source spot, the output terminal VOUT outputs a bias voltage VDD, namely, a logic output 1; when an infrared optical signal is input into the second phototransistor and the fourth phototransistor in the form of a light source spot, the output end VOUT outputs a ground GND, namely a logic output 0; when an infrared optical signal is input into the first phototransistor and the third phototransistor in the form of a light source spot, the output end VOUT outputs a ground GND, namely a logic output 0; when the infrared light signal is input to the third phototransistor and the fourth phototransistor in the form of a light source spot, the output terminal VOUT outputs the ground signal GND, i.e., the logic output 0. Specifically, the truth table of the ir nor gate logic circuit is shown in table 3.
TABLE 3 truth table of infrared light regulating NOR gate logic circuit
Four, infrared light regulation and control NOT gate logic circuit
As shown in fig. 2, the infrared light regulating not gate logic circuit is composed of a first substrate 1, and a first photosensitive layer 2, a first electrode 3, a second electrode 4 and a third electrode 5 integrated on the first substrate 1; the first photosensitive layer 2 is a two-dimensional material, and specifically, in the infrared light control not gate logic circuit, the two-dimensional material selected is molybdenum ditelluride; the material can realize photoelectric induction of infrared wave bands. Under the action of the infrared light signal, photon-generated carriers can be generated, and the photon-generated carriers move directionally under the action of bias voltage to generate photocurrent, so that the level of an output level is changed, and logic operation is realized. In the infrared light control NOT gate logic circuit, the substrate is an insulating substrate, the lowest layer of the substrate is silicon, the upper layer of the substrate is provided with a layer of silicon dioxide, the first electrode 3, the second electrode 4 and the third electrode 5 are all gold metal electrodes, the thickness of the first photosensitive layer 2 is 3nm-30nm, and the length of the first photosensitive layer is 20 micrometers-30 micrometers.
Based on the above, in the infrared light-regulating not gate logic circuit, the first substrate 1, the first photosensitive layer 2, the second electrode 4, and the third electrode 5 form a phototransistor T; the first substrate 1, the first photosensitive layer 2 and the second electrode 4, the first electrode 3 form a resistor R. Wherein the first substrate 1 serves as a gate of the phototransistor T; the first photosensitive layer 2 serves as a channel for the phototransistor T and the resistor R; the second electrode 4, the third electrode 5 serve as the source and the drain of the phototransistor T, respectively, and the second electrode 4, the first electrode 3 serve as the both-end electrodes of the resistor R, respectively. The third electrode 5 is a ground terminal GND, the second electrode 4 is an output terminal VOUT, and the first electrode 3 is a bias voltage terminal VDD. When an infrared optical signal is input into the phototransistor T in the form of a light source spot, the output end VOUT outputs the ground GND, namely the logic output is 0; when no infrared light signal is input to the phototransistor T, the output terminal VOUT outputs the bias voltage VDD, i.e., the logic output 1. Specifically, the truth table of the ir nor logic circuit is shown in table 4.
Table 4 truth table of infrared light regulating not gate logic circuit
| T | | Logic value | |
| 1 | GND | 0 | |
| 0 | |
1 |
In summary, the present embodiment utilizes a two-dimensional material, an insulating substrate, and a gold metal electrode to prepare a mid-infrared phototransistor for logic operation in mid-infrared band; a visible light photoelectric transistor is prepared by utilizing a two-dimensional material, a silicon/silicon dioxide substrate and a gold metal electrode and is used for logic operation of a visible light waveband. The multiple phototransistors are connected in series-parallel connection, so that the two-dimensional material can generate a photon-generated carrier under the action of an optical signal, the photon-generated carrier moves directionally under the action of bias voltage to generate photocurrent, the level of an output level is changed, the signal is transmitted and output, finally, the signal output of the photoelectric integration and the light-operated logic circuit is realized, the preparation process is simplified, the size of the device is reduced, and the device is suitable for large-scale integration.
Moreover, it is noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
Finally, it should be noted that while the above describes a preferred embodiment of the invention, it will be appreciated by those skilled in the art that, once the basic inventive concepts have been learned, numerous changes and modifications may be made without departing from the principles of the invention, which shall be deemed to be within the scope of the invention. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Claims (8)
1. The two-dimensional material light-operated logic gate is characterized by comprising a first substrate and a second substrate, wherein a first photosensitive layer, a first electrode, a second electrode, a third electrode and a fourth electrode are integrated on the first substrate; a second photosensitive layer, a fifth electrode and a sixth electrode are integrated on the second substrate; wherein the first and second photosensitive layers are both made of a two-dimensional photosensitive material;
the first substrate, the first photosensitive layer, the first electrode and the second electrode form a first phototransistor; the first substrate, the first photosensitive layer, the second electrode and the third electrode form a second phototransistor; the first substrate, the first photosensitive layer, the third electrode and the fourth electrode form a third phototransistor; the second substrate, the second photosensitive layer, the fifth electrode and the sixth electrode form a fourth phototransistor;
the first substrate serves as a gate of the first, second and third phototransistors, and the first photoactive layer serves as a channel of the first, second and third phototransistors; the first electrode and the second electrode are used as a source electrode and a drain electrode of the first phototransistor, respectively; the second electrode and the third electrode serve as a source and a drain of the second phototransistor, respectively; the third electrode and the fourth electrode serve as a source and a drain of a third phototransistor, respectively; the second substrate serves as a gate of the fourth phototransistor, the second photoactive layer serves as a channel of the fourth phototransistor, and the fifth and sixth electrodes serve as a source and a drain of the fourth phototransistor, respectively;
the first phototransistor, the second phototransistor, and the third phototransistor are connected in series; the third phototransistor is connected in parallel with the fourth phototransistor.
2. The two-dimensional material photo-controlled logic gate of claim 1, wherein the channel widths of the first phototransistor, the second phototransistor, the third phototransistor, and the fourth phototransistor are each from 2 μ ι η to 3 μ ι η.
3. The two-dimensional material light control logic gate of claim 1, wherein the third electrode and the sixth electrode, and the fourth electrode and the fifth electrode are respectively connected by connecting wires.
4. The two-dimensional material light operated logic gate of claim 3, wherein the connecting wire is a gold metal wire.
5. The two-dimensional material light operated logic gate of claim 1, wherein the first photosensitive layer and the second photosensitive layer each have a thickness of 3nm to 30nm and a length of 20 to 30 μm.
6. A two-dimensional material light operated logic gate as claimed in claim 1 wherein the lowermost layer of the first substrate is silicon with a layer of silicon dioxide above the silicon.
7. A two-dimensional material light operated logic gate as claimed in claim 6 wherein the lowermost layer of the second substrate is silicon with a layer of silicon dioxide above the silicon.
8. The two-dimensional material light operated logic gate of claim 1, wherein the first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode, and the sixth electrode are all gold metal electrodes.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129112A (en) * | 2016-07-04 | 2016-11-16 | 华为技术有限公司 | A kind of electronic device based on two-dimensional semiconductor and manufacture method thereof |
| CN108281454A (en) * | 2018-01-29 | 2018-07-13 | 杭州紫元科技有限公司 | A kind of charge coupling device based on two-dimensional material film/insulating layer/semiconductor structure |
| CN109300911A (en) * | 2018-09-11 | 2019-02-01 | 北京大学 | Based on two-dimensional semiconductor hetero-junctions and/or logic gates and its realization and preparation method |
| CN109347469A (en) * | 2018-10-11 | 2019-02-15 | 西安电子科技大学 | Light-controlled switching circuit based on crystal of molybdenum disulfide pipe |
| CN109638152A (en) * | 2018-11-27 | 2019-04-16 | 北京科技大学 | A kind of transition metal family sulfide logical-arithmetic unit and its construction method |
| CN110504297A (en) * | 2018-05-17 | 2019-11-26 | 中国科学院苏州纳米技术与纳米仿生研究所 | Two-dimensional material transistor, preparation method and application based on two-dimensional electron gas regulation backgate |
| WO2019245990A1 (en) * | 2018-06-18 | 2019-12-26 | The Regents Of The University Of California | General solution-processable approach to high-quality two-dimensional ink materials for printable high-performance large-area and low-cost devices |
| CN111463290A (en) * | 2020-04-13 | 2020-07-28 | 华中科技大学 | Based on MoS2Homojunction field effect transistor and preparation method thereof |
| CN112542473A (en) * | 2020-11-26 | 2021-03-23 | 北京科技大学 | Two-dimensional logic switch driven by optical signal and preparation method thereof |
-
2021
- 2021-05-24 CN CN202110566411.7A patent/CN113315507A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129112A (en) * | 2016-07-04 | 2016-11-16 | 华为技术有限公司 | A kind of electronic device based on two-dimensional semiconductor and manufacture method thereof |
| CN108281454A (en) * | 2018-01-29 | 2018-07-13 | 杭州紫元科技有限公司 | A kind of charge coupling device based on two-dimensional material film/insulating layer/semiconductor structure |
| CN110504297A (en) * | 2018-05-17 | 2019-11-26 | 中国科学院苏州纳米技术与纳米仿生研究所 | Two-dimensional material transistor, preparation method and application based on two-dimensional electron gas regulation backgate |
| WO2019245990A1 (en) * | 2018-06-18 | 2019-12-26 | The Regents Of The University Of California | General solution-processable approach to high-quality two-dimensional ink materials for printable high-performance large-area and low-cost devices |
| CN109300911A (en) * | 2018-09-11 | 2019-02-01 | 北京大学 | Based on two-dimensional semiconductor hetero-junctions and/or logic gates and its realization and preparation method |
| CN109347469A (en) * | 2018-10-11 | 2019-02-15 | 西安电子科技大学 | Light-controlled switching circuit based on crystal of molybdenum disulfide pipe |
| CN109638152A (en) * | 2018-11-27 | 2019-04-16 | 北京科技大学 | A kind of transition metal family sulfide logical-arithmetic unit and its construction method |
| CN111463290A (en) * | 2020-04-13 | 2020-07-28 | 华中科技大学 | Based on MoS2Homojunction field effect transistor and preparation method thereof |
| CN112542473A (en) * | 2020-11-26 | 2021-03-23 | 北京科技大学 | Two-dimensional logic switch driven by optical signal and preparation method thereof |
Non-Patent Citations (2)
| Title |
|---|
| LI GAO, ET., AL.: "Defect-Engineered Atomically Thin MoS2 Homogeneous Electronics for Logic Inverters", ADVANCED MATERIAL, pages 7 * |
| 李卫胜;周健;王瀚宸;汪树贤;于志浩;黎松林;施毅;王欣然: "二维半导体过渡金属硫化物的逻辑集成器件", 物理学报 * |
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