CN113300712A - Dual capacitor digital-to-analog converter - Google Patents

Abstract

The present application relates to a dual capacitor digital-to-analog converter. A dual capacitor digital to analog converter circuit having circuitry to compensate for unwanted capacitance is disclosed. The converter is configured to generate an average voltage over two capacitors for a sequence of bits in a digital word such that when the last bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltages on the two capacitors using different modes to minimize the effect of capacitor mismatch and switch capacitance on conversion accuracy. The converter includes a buffer amplifier whose input capacitance can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged from the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.

Description

Dual capacitor digital-to-analog converter

Cross Reference to Related Applications

This application claims priority to united states provisional application serial No. 62/979,472 filed on 21/2/2020 and united states provisional application serial No. 62/979,474 filed on 21/2/2020.

Technical Field

The present disclosure relates to integrated analog and digital circuits, and more particularly, to a circuit for digital-to-analog conversion and method thereof.

Background

Electronic systems may require digital-to-analog converters (DACs) to convert digital signals to corresponding analog signals. For example, a DAC may allow a digital word to set an output voltage level. In particular, the DAC may be configured to receive each binary bit (b) of an N-bit binary word₀、b₁、...、b_N-1) And a reference voltage (V)_REF) And outputs an output voltage (V)_O). In other words, the DAC may be configured to divide the range defined by the reference voltage into a plurality of levels, each level corresponding to a possible digital word within a range of possible digital words of a given resolution. To achieve this, the DAC may contain a network of resistors or capacitors coupled by switches. The switch may be controlled on/off by bits of the binary word to output voltages of different levels. Capacitor networks are superior to resistor networks due to their lower losses, but are limited by their large size and low accuracy at high resolution (N ≧ 10). Therefore, there is a need for a DAC that utilizes a capacitor network with improved size and accuracy. It is in such circumstances that embodiments of the present disclosure have emerged.

Disclosure of Invention

In at least one aspect, the present disclosure generally describes a dual capacitor digital-to-analog converter circuit (i.e., 2C-DAC). The 2C-DAC circuit includes a phase and mode controller configured to set an active bit in a digital word, select a mode condition of the active bit, and configure a switch according to a first mode or a second mode of a conversion process based on a value of the active bit and the selected mode condition. The 2C-DAC circuit further includes a redistribution switch configured to couple the first capacitor and the second capacitor together during an averaging phase of the conversion process to generate an average voltage. The 2C-DAC circuit further includes a buffer amplifier having an input capacitance at an input. The buffer amplifier is configured to generate an output voltage based on the average voltage. The 2C-DAC further includes a capacitance compensation circuit that includes a replica input capacitance. The capacitance compensation circuit is configured to couple a reference voltage or ground to the replica input capacitance based on the value of the active bit during an input phase of the conversion process. The capacitance compensation circuit is further configured to couple the replica input capacitance to the input capacitance to adjust the average voltage during the averaging phase of the conversion process.

In another aspect, the present disclosure generally describes a digital-to-analog conversion method. The method includes receiving a digital word, setting an active bit of the digital word, selecting a mode condition of the active bit, and determining a first mode or a second mode of the active bit based on a value of the active bit and the selected mode condition. The method further includes executing an input stage, the input stage including a first mode and a second mode. In a first mode of the input phase, charging or discharging a first capacitor and a replica input capacitance in accordance with the value of the active bit. In a second mode of the input stage, charging or discharging a second capacitor and a replica input capacitance in accordance with the value of the active bit. The method further includes performing an averaging phase that includes coupling the first capacitor and the second capacitor together to generate an average voltage of the active bit. The averaging stage further includes coupling the average voltage to a buffer amplifier having an input capacitance, and coupling the replica input capacitance and input capacitance together to produce an adjusted average voltage of the active bit at an input of the buffer amplifier.

In another aspect, the present disclosure generally describes a digital-to-analog conversion system. The system includes a stage and mode controller configured to receive bits of a digital word and output a switching signal according to an input stage, an averaging stage, or an output stage of a conversion process and according to a first mode or a second mode determined for each bit of the digital word received at an input of the system. The system further includes an averaging circuit including a first capacitor and a second capacitor. The averaging circuit is configured to charge or discharge the first capacitor or the second capacitor during an input phase and is configured to couple the first capacitor and the second capacitor together during an averaging phase to produce an average voltage. The system further includes an output circuit including an input capacitance. The output circuit is configured to generate an output voltage based on the average voltage received from the averaging circuit and to couple the output voltage to an output of the system during the output phase. The system further includes a capacitance compensation circuit including a replica input capacitance substantially equal to the input capacitance. The capacitance compensation circuit is configured to couple the replica input capacitance and the input capacitance together during an averaging phase to adjust the average voltage to compensate for the input capacitance.

The foregoing illustrative summary, as well as other exemplary objects and/or advantages of the present disclosure, and the manner of attaining them, is further explained in the following detailed description and the accompanying drawings thereof.

Drawings

Fig. 1A is a schematic diagram of an example dual-capacitor DAC, according to a possible implementation of the present disclosure.

Fig. 1B is a diagram of the output voltages of the dual-capacitor DAC of fig. 1A for possible digital words.

Fig. 2 is a schematic diagram of a dual capacitor DAC (i.e., 2C-DAC) according to a first possible embodiment of the present disclosure.

Fig. 3 is a table of possible pattern conditions for each possible bit combination of a 5-bit binary word (i.e., a digital word) according to an example implementation of the present disclosure.

Fig. 4 illustrates a process of mode condition selection and mode determination based on the possible mode condition table shown in fig. 3.

Fig. 5 is a schematic diagram of a dual capacitor DAC (i.e., 2C-DAC) including reset and output circuitry according to a possible embodiment of the present disclosure.

Fig. 6 is a graph of input capacitance versus average voltage for a buffer amplifier according to a possible embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a dual capacitor DAC (i.e., 2C-DAC) including input capacitance compensation according to a possible implementation of the present disclosure.

Fig. 8 is a flow diagram of a digital-to-analog conversion method according to a possible embodiment of the present disclosure.

Fig. 9 is a block diagram of a digital-to-analog conversion system according to an embodiment of the present disclosure.

The components shown in the figures are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the different views.

Detailed Description

The present disclosure describes a dual capacitor DAC that can provide high resolution conversion of low bandwidth signals with high accuracy. The disclosed DAC can be fabricated in a smaller area of an integrated circuit than other capacitor network based DACs, such as binary weighted capacitor network DACs or ladder capacitor network (i.e., C-2C network) DACs, and does not require calibration to obtain high resolution accurate performance. In addition, the disclosed DAC provides alternative modes of operation and circuitry to compensate for inaccuracies arising from practical implementations.

The binary-weighted capacitor network DAC includes banks of capacitors (each bank having a particular capacitance) that can be on/off coupled to a reference voltage according to a binary input to generate a particular output voltage. One problem with this approach is the number of capacitors required for high resolution (N ≧ 10) applications. A large number of capacitors may create a network that is too complex or too large to be practical for implementation. In addition, problems with the number of capacitors in the network, such as leakage, mismatch, etc., may also limit the resolution of binary weighted capacitors that can be practically implemented. The disclosed DAC uses only two capacitors and thus may be physically smaller than a corresponding binary-weighted capacitor DAC. Additionally, the two capacitors may be nominally the same capacitance (e.g., a 1:1 ratio); thus, the range between the largest capacitor in the network and the smallest capacitor in the network (i.e., the capacitor arrangement) may be smaller. Furthermore, capacitor mismatch can be effectively eliminated in the disclosed DAC due to charge redistribution between the two capacitors in its network. Accordingly, the disclosed DAC may also have less capacitor mismatch than a binary-weighted capacitor network and thus may be more accurate (e.g., linear, monotonic).

The C-2C network DAC may be simpler and smaller than a binary-weighted capacitor network DAC, but it may still be complex and large in order to provide linear performance at high resolution. The linearity of the C-2C network DAC is affected by the parasitic capacitance at the nodes of the ladder network. To compensate for parasitic capacitance, the C-2C DAC may require memory (e.g., RAM) to store and recall digital correction terms (e.g., obtained by calibration), and/or may require self-calibration of the trim capacitor array. In both cases, circuitry to compensate for parasitic effects may make the C-2C DAC more complex and larger. The disclosed DAC uses only two capacitors and can therefore be physically smaller than a corresponding C-2C network DAC. Furthermore, non-linearities due to parasitic capacitances can be effectively eliminated in the disclosed DAC due to charge redistribution between the two capacitors in its network. Thus, the disclosed DAC may not require calibration or trimming of the capacitor array to achieve high resolution linear performance.

The advantages of the disclosed DAC capacitor network may come at the expense of its speed. For a binary weighted capacitor DAC or C-2C DAC, bits of a digital word may be applied in parallel to a capacitor network to obtain a corresponding output signal. However, in the disclosed DAC capacitor network, the bits of the digital word are applied sequentially (serially) and all bits from the Least Significant Bit (LSB) to the Most Significant Bit (MSB) have to be processed before the corresponding output signal is obtained.

For applications that do not require high speed conversion, the tradeoff between performance and speed is acceptable. For example, some biomedical applications (e.g., glucose monitoring sensing) may require a DAC as part of a programmable bias circuit. These applications may require accurate and low power consuming DACs, but may not require high speed DACs. The disclosed DAC is well suited for these applications because it can operate at high resolution (e.g., ≧ 10 bits), has low power consumption, has a simple (i.e., small) layout, is highly linear (e.g., integral or differential nonlinearity ≦ 1LSB), and can provide rail-to-rail output.

To explain its ideal operation, a simplified dual capacitor DAC is shown in fig. 1A. Capacitor (C)₁、C₂) May be substantially the same capacitance and thus the ratio of capacitances may be about 1: 1. For conversion, the dual capacitor DAC is configured to sequentially receive each bit (B) of the digital word (B) from LSB to MSB_i). An average voltage (V) may be generated for each bit in the sequence_AVG) Such that the final average voltage of the sequence is the output voltage (V) corresponding to the analog level of the digital word (B)_O). The average voltage is a voltage generated by redistributing a charge difference between capacitors charged to different voltages. When the redistribution is equal, the voltage on the capacitors after redistribution is the average of the voltage on each capacitor before redistribution. It is in this case that the term "average" is used herein, but the present disclosure recognizes that variations may exist (e.g., if the redistribution is not uniform, etc.). Thus, the average voltage generated for each bit (i.e., the redistribution voltage) may generally refer to the voltage between the voltages on each capacitor before redistribution (e.g., intermediate frequency, offset intermediate frequency, weighted average, etc.), rather than a specific mathematical relationship. Each average voltage of the sequence is calculated using two phases: an input phase and an averaging phase (i.e., a reassignment phase). After calculating the final average voltage of the sequence, an output phase occurs. The switching state table for each stage is shown in table 1 below.

Table 1: switch state examples for simple dual capacitor DAC

Phases	S0	S1	SAVG	SOUT
					Input (b)i＝0)	Is connected to	Disconnect	Disconnect	Disconnect
Input (b)i＝1)	Disconnect	Is connected to	Disconnect	Disconnect
					Average	Disconnect	Disconnect	Is connected to	Disconnect
Output of	Disconnect	Disconnect	Disconnect	Is connected to

When inputting bit (b)_i) Logic 1, high input switch (i.e. one switch (S)₁) May be configured to couple the first capacitor (C)₁) Coupled to a reference voltage (V)_REF) When the bit (b) is inputted_i) Logic 0, then the low input switch (i.e., zero switch (S)₀) May be configured to couple the first capacitor (C)₁) Coupled to a ground voltage (e.g., 0V). A switch (S)₁) And zero switch (S)₀) Switching in a complementary manner such that when a switch (S)₁) When closed, zero switch (S)₀) Open and vice versa. Based on the state of the switch, the first capacitor (C) is applied during the input phase of the DAC conversion process₁) Charging or discharging is performed. Averaging the switches (S) during the averaging phase of the DAC conversion process_AVG) (i.e. redistribution switch) is configured to connect the first capacitor (C)₁) And a second capacitor (C)₂) Coupled together so that the total stored charge in the capacitor is equally redistributed. The input phase and the averaging phase are repeated for each bit of the digital word before the output phase. In the output phase of the DAC conversion process, the output switch (S)_OUT) Configured to couple the second buffer amplifier 110 to the output of the DAC. Second capacitor (C)₂) The redistributed charge (i.e., the average voltage) produces an input voltage at the input of the buffer amplifier 110, which is configured to produce an output voltage (V) at the output (i.e., the dual capacitor DAC output)_O). The buffer amplifier may be a unity gain amplifier such that the average voltage (V)_AVG) Becomes the output voltage (V) of the dual capacitor DAC in the output stage_O)。

FIG. 1B shows the output voltage (V) of the dual capacitor DAC shown in FIG. 1A_AVG) Shown is a binary word 101 (i.e., 5) ranging from 000 (i.e., 0) to 111 (i.e., 7) binary words. For LSB (i.e. b)₀) Charging the first capacitor to a reference voltage (V) during the input phase_REF). Next, in the averaging phase, the charge is split equally between the capacitors, so that b₀Average voltage (V) of_AVG) Is a V_REF/2 (i.e., 4/8V)_REF). For the next valid bit (b)₁) In the input stage, the first capacitor (C)₁) Discharge to ground. Next, in the averaging phase, the remaining charge is split equally between the capacitors, so that the average voltage (V) is_AVG) Discharge to between V_REFVoltage between/2 and ground (i.e., 2/8V)_REF). For the most significant bit (b)₂) A first capacitor (C)₁) Charging to V_REF. Next, in the averaging phase, the charge is split equally between the capacitors, so that the average voltage (V) is_AVG) Charging to the previous output voltage and V_REFHalf the voltage in between (i.e., 5/8V)_REF). Therefore, the average voltage advances at an output voltage (V) corresponding to a digital value by a bit from LSB to MSB_O) And finishing the process. Thus, the entire digital word can be processed sequentially to obtain the appropriate converted analog value.

The performance (e.g., accuracy) of a dual capacitor DAC can be characterized by its integral non-linearity and its differential non-linearity. The integral non-linearity (INL) is the difference between the actual DAC output of the digital input and the ideal DAC output. Differential Nonlinearity (DNL) is the difference between the actual step size and the ideal step size between the digital inputs (e.g., a step size between 000 and 001). In some applications, INL and DNL are preferably less than + -1 LSB. When these conditions are satisfied, the DAC can be said to be monotonic. In addition to capacitor mismatch, a practical implementation of the dual-capacitor DAC shown in fig. 1A may have additional (i.e., unwanted) capacitance that may lead to performance degradation. Furthermore, the additional capacitance may limit the rail-to-rail operation of the dual capacitor DAC. The disclosed dual capacitor DAC utilizes methods and circuitry to reduce or eliminate additional capacitance to improve performance such that the dual capacitor DAC is monotonic and can operate rail-to-rail.

One additional source of capacitance comes from the switch used in the input stage (e.g. S)₀、S₁) Practical embodiment of (1). For example, the first switch (S) of the dual capacitor DAC shown in FIG. 1A₁) Can be implemented as a transistor (e.g., MOSFET) that includes a small capacitance (e.g., gate capacitance C) that is charged during operation_GS). During the input phase, the charge stored in this small capacitor can be changed (e.g. by changing the chargeReduced) stored in the capacitor (C)₁) Of the charge of (1). For short binary words (e.g. N)<10) The change in charge may be relatively small, so that at the end of the sequence of binary bits, the final output voltage does not change significantly from its ideal level. In other words, the performance is not significantly degraded. However, for long binary words (i.e., high resolution), the cumulative effect of the charge variations caused by the switched capacitances can degrade the performance of the dual-capacitor DAC. The disclosed dual capacitor DAC utilizes methods and circuitry to mitigate the effects of switched capacitance to improve performance.

Another additional source of capacitance in a practical implementation is a buffer amplifier 110. The buffer amplifier 110 may be implemented as an operational amplifier (i.e., opamp) having an input capacitance. For example, an input stage of a buffer amplifier (e.g., an operational amplifier) may include a transistor (e.g., a MOSFET) having a capacitance (e.g., a gate capacitance C) associated with its operation_GS). The input capacitance may change (e.g., decrease) the charge level of the two capacitor outputs. Thus, the output voltage (V) at the output of the dual capacitor DAC_O) Can be reduced by the input capacitance of the buffer amplifier and the first capacitor C₁And a second capacitor C₂Is determined. The precision of the dual capacitor DAC may vary according to the binary word input because the input capacitance may vary according to the voltage at the input of the buffer amplifier 110. The disclosed dual capacitor DAC utilizes methods and circuitry to mitigate the effects of buffer amplifier input capacitance and its variations to improve performance.

Fig. 2 is a schematic diagram of a dual capacitor DAC (i.e., 2C-DAC) circuit according to a first possible embodiment of the present disclosure. The 2C-DAC circuit 200 (i.e., the circuit) includes a plurality of switches that configure the circuit for the digital conversion process. As described previously, by calculating the average voltage (V) of each bit_AVG) To perform a digital conversion of a binary (i.e., digital) word. For example, the first average voltage may be calculated based on the least significant bits of the binary word and then continuously updated until all bits of the digital word have been processed (i.e., until the MSB). The final average voltage is at a level corresponding to the digital word and is taken as outputVoltage (V)_O) Coupled to the output of the DAC. The average voltage obtained for each bit is calculated using the input phase and the averaging phase. The 2C-DAC circuit is configured for each stage of the conversion process by control of the plurality of switches. The switches may be implemented as transistor devices (e.g., NMOS transistors and/or PMOS transistors).

The 2C-DAC comprises a first set of input switches (S)_{1_C1}、S_{0_C1}) Which can be configured to couple the first capacitor (C) during the input phase₁) Charging/discharging is performed. The configuration of the switches is based on the bits of the binary word. For example, if the bit of the digital word is 1, the switch S_{1_C1}Is turned on (i.e., turned on) and the switch S_{0_C1}Off (i.e., non-conductive) when the current bit is zero, and vice versa. The 2C-DAC further comprises a second set of input switches (S)_{1_C2}、S_{0_C2}) Which may be configured to charge/discharge the second capacitor during the input phase. The configuration of the second set of switches may also be based on bits of a binary word. For example, if the bit is 1, then switch S_{1_C2}Is turned on and the switch S_{0_C1}Open, when the bit is zero, and vice versa.

During the input phase, only one set of input switches is active for each bit of the digital word. For example, some bits of a digital word may use a first set of input switches (S)_{1_C1}、S_{0_C1}) Input, and other bits of the digital word may use a second set of input switches (S)_{1_C2}、S_{0_C2}) And (4) inputting. The selection of the first or second set of input stages is determined by the mode of the 2C-DAC circuit.

The 2C-DAC circuit is operable in one of two modes. In a first mode (i.e., mode 1), a first set of input switches (S) is used_{1_C1}、S_{0_C1}) And in a second mode (i.e., mode 2), a second set of input switches (S) is used_{1_C2}、S_{0_C2}). The 2C-DAC further comprises a set of coupling switches (S)_{C_C1}、S_{C_C2}) Which can be configured to couple the first capacitor (C) during the input phase₁) Or a second capacitor (C)₂) Coupled to a buffer amplifier 210. The first capacitor coupling switch (S) may be determined according to a mode of a switching process_{C_C1}) Or secondCapacitor coupling switch (S)_{C_C2}) Selection of (2). For example, in the first mode (i.e., mode 1), the first capacitor (C)₁) Can be charged during the input phase, while the second capacitor (C)₂) May be coupled to the buffer amplifier 210 during the input stage. In the second mode (i.e., mode 2), the second capacitor (C)₂) Can be charged during the input phase, while the first capacitor (C)₁) May be coupled to the buffer amplifier 210 during the input stage. Switching in this manner can alternate the capacitors that are charged/discharged during the input phase and that are coupled to the buffer amplifier 210 during the input phase. By alternating coupling in this manner, the effects of capacitor mismatch may be reduced and the performance (e.g., accuracy, linearity) of the DAC conversion may be improved. Table 2 shows example switch states of an input phase according to a possible embodiment of the present disclosure. Other switches not mentioned in table 2 may be open during the input phase.

Table 2: example switch states for input phases

	1, mode 1	bi is 0, mode 1	bi 1, mode 2	bi is 0, mode 2
					S1_C1	Is connected to	Disconnect	Disconnect	Disconnect
S0_C1	Disconnect	Is connected to	Disconnect	Disconnect
					S1_C2	Disconnect	Disconnect	Is connected to	Disconnect
S0_C2	Disconnect	Disconnect	Disconnect	Is connected to
					SC_C1	Disconnect	Disconnect	Is connected to	Is connected to
SC_C2	Is connected to	Is connected to	Disconnect	Disconnect

The 2C-DAC further comprises an averaging switch (i.e. a redistribution switch). A first capacitor (C) during the input phase₁) Or a second capacitor (C)₂) After the charge/discharge of the electric power,the averaging phase may begin. In the averaging phase, averaging switch S_AVGMay be turned on and the input switch may be turned off. The averaging switch can be used for the averaging phase, independent of the mode. When averaging switch S_AVGWhen switched on, the first capacitor (C)₁) And a second capacitor (C)₂) The charges in (1) can be equalized to an average value. Thus, at the end of the averaging phase, the voltage across each capacitor may be substantially the same (e.g., equal).

The set of coupled switches (S)_{C_C1}、S_{C_C2}) Can be configured to average the first capacitor (C)₁) And a second capacitor (C)₂) Coupled to the buffer amplifier. For example, in the first mode (i.e., mode 1), the first capacitor (C)₁) Can be charged during the input phase and the first capacitor (C) during the averaging phase₁) And a second capacitor (C)₂) May be coupled together and to buffer amplifiers. In the second mode (i.e., mode 2), the second capacitor (C)₂) Can be charged during the input phase and the first capacitor (C) during the averaging phase₁) And a second capacitor (C)₂) May be coupled together and to buffer amplifiers. In this way, capacitors that can be alternately charged/discharged in the input phase are switched, and the capacitors are all coupled to the buffer amplifier in the averaging phase. By switching in this manner, the effect of capacitor mismatch may be reduced and the performance (e.g., accuracy, linearity) of the DAC conversion may be improved. Table 3 shows example switch states for the averaging phase according to a possible embodiment of the present disclosure. Other switches not mentioned in table 3 may be open during the averaging phase.

Table 3: example switch states of the averaging phase

	Mode 1	Mode 2
			SAVG	Is connected to	Is connected to
SC_C1	Is connected to	Is connected to
			SC_C2	Is connected to	Is connected to

The 2C-DAC may further include a buffer amplifier 110 implemented as an operational amplifier 210 (i.e., opamp). The operational amplifier 210 may be configured for unity gain such that during the output phase, the voltage (V) is output_O) May be approximately equal to the average voltage of the charge after it has been redistributed between the first capacitor and the second capacitor. Output voltage (V) of operational amplifier_O) May be a voltage within a range determined by the upper and lower rail voltages supplied to the operational amplifier. In one possible implementation, the operational amplifier may be configured for rail-to-rail operation such that the output voltage (V) is_O) May be between ground voltage and reference voltage (V)_REF) Within the range of (1).

By alternating the pattern during the transition, the capacitor charged/discharged during the input phase can be varied. Such variations can minimize the effect of capacitor mismatch and unwanted capacitance (e.g., switched capacitance) to avoid V for a given location_OThe accuracy of (a) has a negative impact. Thus, the disclosed 2C-DAC may improve accuracy. This improved accuracy is particularly important for high resolution (high bit depth) applications, where the output voltage range is subdivided into sub-ranges to represent each possible bit combination in the digital word. Example (b)For example, a rail-to-rail output voltage range of 0-5V must be divided into 32 sub-ranges to represent a 5-bit digital word, with each possible bit providing only a sub-range of approximately 156 mV. As the number of bits of a digital word increases, higher precision is required. The disclosed 2C-DAC can provide precision for handling high resolution (N-bit words, N ≧ 10).

The mode selection may be based on a mode condition of each bit of the digital word. For example, the mode condition may be one of two possible mode conditions for each bit in the digital word. The mode condition may be a rule, as shown in the following equation.

The mode condition may be based on a bit position in the digital word. For example, the LSB (i ═ 0) may have a first mode condition, the next more significant bit (i.e., i ═ 1) may have a second mode condition, the next more significant bit (i.e., i ═ 2) may have a first mode condition, and so on to the MSB. Thus, when the bits are sequentially clocked into the DAC, the mode condition may change (e.g., alternate) between the first mode condition (i.e., mode condition _1) and the second mode condition (i.e., mode condition _ 2).

Fig. 3 is a table of possible pattern conditions and patterns for each possible bit combination of a 5-bit binary word (i.e., a digital word) according to an example embodiment of the present disclosure. Each possible digital word has a unique pattern combination based on (i) the pattern condition for each bit position and (ii) the bit value for each bit position. For the digital word 00000, the pattern for each bit from LSB to MSB is alternating because the pattern condition for each bit position is alternating, while the bit value for each bit position is not. Also for the digital word 11111, the pattern for each bit from LSB to MSB is alternating because the pattern conditions for each bit position are alternating, while the bit value for each bit position is not. The patterns for the digital words 00000 and 11111 are complementary. For digital word 01010, the pattern for each bit from the LSB to the MSB is the same (i.e., pattern 1) because the pattern conditions for each bit position alternate, and the bit values for each bit position also alternate. Also for the digital word 10101, the pattern for each bit from the LSB to the MSB is the same (i.e., pattern 2), because the pattern conditions for each bit position alternate, and the bit values for each bit position also alternate. The choice of which mode condition to use for the LSB of the 00000 word may be the first mode condition or the second mode condition, as long as the mode conditions for each bit position are alternating (i.e., in the horizontal direction of the table).

The 2C-DAC includes circuitry (not shown) configured to sequentially feed bits of the digital word (i.e., clock bits) into the 2C-DAC, select a mode condition based on the significance of the bit (i.e., its bit position in the sequentially fed bits), and select a mode (i.e., mode 1, mode 2) based on the value of the bit applied to the selected mode condition. For example, the 2C-DAC may contain logic circuitry that activates either the first mode (mode 1) or the second mode (mode 2) based on the table shown in FIG. 3. Alternatively, the 2C-DAC may contain logic circuitry that activates either the first mode (mode 1) or the second mode (mode 2) based on a table similar to that shown in fig. 3 when there are more or less than 5 bits in the digital word.

The mode condition may be implemented using a bit select signal (i.e., bit _ select). The bit select signal may alternate based on the significance of the bit. For example, the bit select signal may be zero for the LSB bit (data [0]), one for the next valid bit (data [1]), zero for the next valid bit (data [2]), and so on to the MSB. The mode may be selected by comparing the value of the bit (i.e., bit _ value) to a bit select signal. For example, mode 1 may be selected when the bit selection signal is 0 and the value of the bit is 0, and mode 2 may be selected when the bit selection signal is 0 and the value of the bit is 1. Likewise, mode 2 may be selected when the bit selection signal is 1 and the value of the bit is 0, and mode 1 may be selected when the bit selection signal is 1 and the value of the bit is 1.

Fig. 4 illustrates a process of mode condition selection and mode determination based on the possible mode condition table shown in fig. 3. The process is based on the example 5-bit digital word 01100. The process starts with a 5-bit digital word 01100The LSB of (1) begins. As can be seen from the table shown in FIG. 3, for LSB (data [0]]) Is the first mode condition (bit _ select is 0). Therefore, when the bit value (b) of LSB₀0) is applied to the mode condition, mode 1 is selected. In other words, the bit selection signal (i.e., 0) of the bit matches the bit value (i.e., 0), thus selecting mode 1. As a result, the 2C-DAC shown in fig. 2 can use the switches specified for mode 1 for the input, averaging and output phases.

The process continues with a 5-bit digital word 0110The next valid bit of 0. As can be seen from the table shown in FIG. 3, for the next valid bit (data [1]]) Is a second mode condition (bit _ select is 1). Therefore, the bit value (b) of the next valid bit₁0) is applied to the mode condition, mode 2 is selected. In other words, the bit selection signal (i.e., 1) of the bit does not match the bit value (i.e., 0), and thus mode 2 is selected. As a result, the 2C-DAC shown in fig. 2 can perform the input, averaging and output phases using the switches specified for mode 2.

The process continues with processing the 5-bit digital word 011The next significant bit of 00. As can be seen from the table shown in FIG. 3, for the next valid bit (data [2]]) Is the first mode condition (bit _ select is 0). Therefore, the bit value (b) of the next valid bit₂1) when applied to the mode condition, mode 2 is selected. In other words, the bit select signal (i.e., 0) does not match the bit value (i.e., 1), and thus mode 2 is selected. As a result, the 2C-DAC shown in fig. 2 can perform the input, averaging and output phases using the switches specified for mode 2.

The process continues with processing the 5-bit digital word 01100, the next valid bit. As can be seen from the table shown in FIG. 3, for the next valid bit (data [3 ]]) Is a second mode condition (bit _ select is 1). Therefore, the bit value (b) of the next valid bit₃1) when applied to the mode condition, mode 1 is selected. In other words, the bit selection signal (i.e., 1) of the bit matches the bit value (i.e., 1) becauseThis selects mode 1. As a result, the 2C-DAC shown in fig. 2 can use the switches specified for mode 1 for the input, averaging and output phases.

The process is based on 5-bit digital words0The MSB of 1100 ends. As can be seen from the table shown in FIG. 3, for the next valid bit (data [4 ]]) Is the first mode condition (bit _ select is 0). Therefore, when the bit value (b) of the MSB₄0) is applied to the mode condition, mode 1 is selected. In other words, the bit selection signal (i.e., 0) of the bit matches the bit value (i.e., 0), thus selecting mode 1. As a result, the 2C-DAC shown in fig. 2 can use the switches specified for mode 1 for the input, averaging and output phases.

It is observed that the process changes modes when the sequential bit values are unchanged. This can prevent the same capacitor from being repeatedly charged or discharged in sequence. Preventing the same capacitor from being repeatedly charged/discharged in a bit sequence can prevent the same switch from being repeatedly used, and thus can prevent charging/discharging errors caused by the capacitance of the switch. On the other hand, when the sequential bit value changes due to at least charging and discharging the capacitor using different switches, the process does not change modes. By preventing repeated charging/discharging of the same capacitor (i.e., repeated use of the same switch), the performance (e.g., accuracy, linearity) of the DAC conversion may be improved.

At the end of the process, the output voltage (V) at the output of the buffer shown in FIG. 2_O) May be at a voltage corresponding to the number 01100 (i.e., 12). Output Voltage at the end of Process (V) for 2C-DAC output Voltage range of 0V to 1V_O) May be 12/31V. The process shown in fig. 4 operates on binary words and may be repeated for additional binary words. For example, binary words may be sequentially input to the 2C-DAC to produce a time-varying output voltage. The rate at which the output voltage may be varied may depend on the speed at which the process shown in figure 4 may be performed. Thus, a higher resolution (i.e., a longer digital word) results in a slower transition than a lower resolution (i.e., a shorter digital word).

FIG. 5 is a dual capacitor including reset and output circuitry according to a possible implementation of the present disclosureSchematic diagram of a DAC (i.e., 2C-DAC). The 2C-DAC circuit 500 is similar to the embodiment of fig. 2, with the addition of a sample-and-hold circuit 510 at the output of the operational amplifier 210. The sample-and-hold circuit 510 includes a switch (S) coupled to an output_OUT) Sample-and-hold capacitor (C)_SH). When the output switch is turned on, the sample-and-hold capacitor (C)_SH) Is configured to be charged to the output voltage (V) of the operational amplifier 210_O). Sample-and-hold capacitor (C)_SH) Coupled to the output of the DAC (i.e. OUT)_DAC) So that even when the switch (S) is output_OUT) The output voltage can also be sampled and held by a sample-and-hold capacitor (C) when switched off_SH) Held at the output of the DAC (i.e., OUT)_DAC)。

The 2C-DAC circuit 500 further includes a reset switch coupled to each capacitor of the circuit. First reset switch (S)_{RES_C1}) Coupled in parallel to a first capacitor (C)₁) Between the positive terminal of (a) and ground. The first reset switch may be configured to couple the first capacitor (C) in an ON condition₁) And (4) discharging. Second reset switch (S)_{RES_C2}) Coupled in parallel to a second capacitor (C)₂) Between the positive terminal of (a) and ground. The second reset switch may be configured to couple the second capacitor (C) in the on condition₂) And (4) discharging. Sample-and-hold reset switch (S)_{RES_CSH}) Coupled in parallel to a sample-and-hold capacitor (C)_SH) Between the positive terminal of (a) and ground. Sample-and-hold reset switch (S)_{RES_CSH}) Can be configured to sample and hold the capacitor (C) under the condition of switching on_SH) And (4) discharging. The reset switches may be controlled together or individually. For example, the reset switch may be turned on at the end of a digital word so that no residual charge alters the calculation of the next digital word.

The operational amplifier 210 of the 2C-DAC circuit 500 may have an input capacitance (C) that may affect (e.g., reduce) the accuracy of the digital-to-analog conversion_IN). For example, the input stage of the operational amplifier may comprise a differential pair of transistors. One or more transistors in the differential pair may have a capacitance associated with a control terminal (e.g., a gate terminal). In this example, the input capacitance (C) of the operational amplifier_IN) May be connected to the gate terminal (i.e., C)_GS) An associated capacitance.If a slave capacitor (C) is used₁、C₂) A portion of the coupled charge charges the input capacitance of the operational amplifier, then V_OThere may be an error associated with this portion of the charge used to charge the input capacitance of the operational amplifier. Calibration of this portion may be difficult or impossible because the input capacitance may vary.

Fig. 6 is a diagram of input capacitance of an operational amplifier configured as a buffer amplifier. The figure contains an inset 610 showing a buffer amplifier comprising a capacitor having an input capacitance C_INThe operational amplifier 210. As shown, the input capacitance may vary the average input voltage (Vaverage) in a complex manner (e.g., non-linear, non-monotonic, etc.)_AVG). As previously described, the average voltage may vary during the transition (see, e.g., fig. 1B). Thus, the switching error caused by the input capacitance may vary for each possible bit combination. This may result in unpredictable errors in the conversion of the binary word. The disclosed dual capacitor DAC utilizes methods and circuitry to mitigate the effects of buffer amplifier input capacitance and its variations in order to improve performance (e.g., linearity, monotonicity, accuracy).

Fig. 7 is a schematic diagram of a dual capacitor DAC (i.e., 2C-DAC) circuit including a capacitance compensation circuit according to a possible implementation of the present disclosure. The 2C-DAC circuit 700 is similar to the 2C-DAC implementation of FIG. 5 by the addition of the capacitance compensation circuit 710. The capacitance compensation circuit 710 includes an input capacitor (C) having an operational amplifier 720_IN) Duplicate input capacitors (C) of similar capacitance (e.g. equivalent capacitance)_{IN_REP}) (i.e., duplicate input capacitance). For example, an input capacitor (C)_IN) And replica input capacitor (C)_{IN_REP}) May have the same variation as the average voltage (see, e.g., fig. 6).

The capacitance compensation circuit 710 may further include a pair of compensation input switches (S)₁、S₀). The compensated input switches may be configured to be based on controlling a first set of input switches (S)_{1_C1}、S_{0_C1}) Or a second group of input switches (S)_{1_C2}、S_{0_C2}) Is operated on by the data of. For example, when S_{1_C1}Or S_{1_C2}When one is turned on, the first compensation input switch (S)_{1_CINREP}) Can be switched on and when S_{0_C1}Or S_{0_C2}When one is turned on, the second compensation input switch (S)_{0_CINREP}) Can be switched on. When the first compensation input switch (S)_{1_CINREP}) When switched on, the second compensation input switch (S)_{0_CINREP}) May be disconnected and vice versa. In other words, in the input stage of mode 1 or mode 2, when the bit value is 1, the first compensation input switch (S)_{1_CINREP}) On, or when the bit value is zero, the second compensating input switch (S)_{2_CINREP}) And (4) switching on. In this way, the input capacitor (C) is duplicated_{IN_REP}) Charging or discharging may be performed during the input phase.

The capacitance compensation circuit 710 may further include a first compensation switch (S)_{COMP_C1}) And a second compensation switch (S)_{COMP_C2}) They are configured to operate according to a mode during the averaging phase. Accordingly, when averaging switch (S)_AVG) And S_{C_C1}Or S_{C_C2}When turned on, can turn on S_{COMP_1}Or S_{COMP_2}. For example, during the averaging phase of the conversion process in mode 1, the first compensation switch (S) may be switched on_{COMP_C1}) To be stored in C_{IN_REP}Is coupled to node 1 of the 2C-DAC circuit 700. During the averaging phase of the switching process in mode 2, the second compensation switch (S) can be switched on_{COMP_C2}) To be stored in C_{IN_REP}Is coupled to node 2 of the 2C-DAC circuit 700. Thus, the averaging stage of the conversion process has two aspects. The first aspect (i.e. conversion-averaging) is contained in C₁And C₂Redistribute charge therebetween, the second aspect (i.e., replica-average) being embodied in C_{IN_REP}And C_INTo redistribute the charge between them.

During the averaging phase of the conversion process (i.e. replica-average), the input capacitance C may be used_INRedistribution C_{IN_REP}By the charge on, by C₂(C₁) Redistribution C₁(C₂) The charges on are the same. Thus, a portion of the charge is added to compensate for the charge consumed by the input capacitance. Replica input capacitor (C)_{IN_REP}) Heyu (Chinese character) transfusion systemInto a capacitor (C)_IN) With the same average voltage and average capacitance. In a possible implementation, the replica input capacitor is a replica of a portion of the operational amplifier 720 (not shown). For example, the capacitance compensation circuit 710 may include transistors configured to substantially match the transistors of the operational amplifier 720 coupled to the output of the 2C-DAC. Table 4 shows example switch states for the averaging phase according to a possible embodiment of the present disclosure. Other switches not mentioned in table 4 may be open during the averaging phase.

Table 4: example switch states of the averaging phase

	Mode 1	Mode 2
			SAVG	Is connected to	Is connected to
SC_C1	Is connected to	Is connected to
			SC_C2	Is connected to	Is connected to
SCOMP_1	Is connected to	Disconnect
			SCOMP_2	Disconnect	Is connected to

Fig. 8 is a flow diagram of a digital-to-analog conversion method according to a possible embodiment of the present disclosure. The method 800 includes receiving 810 a binary word (B) (i.e., digital word) including binary bits (i.e., digital bits, bits). For example, receiving a binary word may include receiving bits sequentially from a Least Significant Bit (LSB) to a Most Significant Bit (MSB). Thus, the method includes setting 820 LSBs to the active bits in the binary word. The method further includes selecting 830 a mode condition (e.g., 0-mode 1, 1-mode 2) based on an active bit in the binary word. The method then includes determining 835 a mode based on the value of the active bit (e.g., 0, 1) and the selected mode condition. The method then enters the input phase of the conversion process.

The converter may include a phase and mode controller for loading data into the converter, determining the mode of each bit, and outputting a switching signal to a switch in the 2C-DAC circuit. For example, the stage and mode controller may include a shift register for sequentially feeding bits into the 2C-DAC circuit. The phase and mode controller may also include logic configured to determine a mode condition and a mode for each bit. The logic may be further configured to output a switching signal based on the mode condition and the mode of each bit.

During an input phase of the conversion process, the method includes controlling a set of input switches to charge or discharge a capacitor. In mode 1, the method includes controlling 841 a first set of input switches (S)_{0_C1}、S_{1_C1}) To the first capacitor (C)₁) Charging/discharging (and turning on S)_{C_C2}). In mode 2, the method includes controlling 842 a second set of input switches (S)_{0_C2}、S_{1_C2}) To the second capacitor (C)₂) Charging/discharging (and turning on S)_{C_C1}). In addition, in the input phase, the method includes controlling840A set of compensation input switches (S)_{1_CINREP}、S_{0_CINREP}) To duplicate the input capacitor (C)_{IN_REP}) Charging/discharging is performed. The control of the compensation input switch may be mode independent. For example, when bi is 1, S may be turned on_{1_CINREP}To C is paired_{IN_REP}Charging is performed, and when bi is 0, S can be turned on_{0_CINREP}To C is paired_{IN_REP}A discharge is performed, independent of the determined mode. After the input phase, the method enters the averaging phase of the conversion process.

In the averaging phase of the conversion process, the method comprises controlling 850 an averaging switch (S)_AVG) To mix C with₁Is coupled to C₂To redistribute (i.e., average) charge between the capacitors (and turn on S)_{C_C1}And S_{C_C2}). The method further includes controlling the switch to duplicate the input capacitance (C) at the buffer amplifier_{IN_REP}) And an input capacitance (C)_IN) Redistribute the charge between them to produce an adjusted average voltage. In mode 1, the method includes controlling 851 a coupling switch (S)_{C_C1}) And a coupling switch (S)_{C_C2}) And a compensation switch (S)_{COMP_1}) To mix C with_{IN_REP}Is coupled to C_IN. In mode 2, the method includes controlling 852 a coupling switch (S)_{C_C1}) And a coupling switch (S)_{C_C2}) And a compensation switch (S)_{COMP_2}) To mix C with_{IN_REP}Is coupled to C_IN。

After the averaging phase, the method may repeat the input phase and the averaging phase, or enter the output phase depending on the bit position of the active bit. Thus, the method includes checking 860 whether the active bit is the last bit (e.g., MSB) of the digital word. If the active bit is not the last bit of the digital word, the next most significant bit is set 870 to be the active bit and the process conversion process is repeated for the new active bit. If the active bit is the last bit of the digital word, the method enters the output phase.

In the output phase of the conversion process, the method comprises controlling 880 the output switch (S)_OUT) To couple the output of the buffer amplifier to the output of the DAC (i.e., OUT)_DAC). Buffer amplificationOutput voltage (V) of the device_O) Is the average voltage (V) at the input of the buffer amplifier_AVG) A buffered version of (a). After the output is generated for the digital word, the first capacitor, the second capacitor and the duplicate input capacitance may be discharged and a new digital word may be received. After receiving the new digital word, the above process may be repeated to obtain the output voltage of the new digital word.

Fig. 9 is a block diagram of a digital-to-analog conversion system according to an embodiment of the present disclosure. The system includes a 2C-DAC 910 that is configurable by the phase and mode controller 901 in mode 1 or mode 2 versions of the input phase, the averaging phase, and the output phase. For example, the phase and mode controller 901 may comprise a digital shift register for reading (i.e., clocking) the bit values of the digital word from the least significant bit to the most significant bit. Phase and mode controller 901 may also contain logic (see, e.g., fig. 3) configured to determine mode conditions and modes (i.e., mode 1, mode 2) based on the position of the bit and the value of the bit. The phase and mode controller 901 may output a switching signal coupled to a switch in the 2C-DAC. The switches may be configured according to the mode (i.e., mode 1, mode 2) and the stage of the transition (i.e., input, average, output).

The 2C-DAC may also include an averaging circuit 940. The averaging circuit 940 may include a first capacitor (C)₁) And a second capacitor (C)₂). The averaging circuit 940 may be configured by switching signals to charge or discharge the first capacitor or the second capacitor during the input phase. The averaging circuit 940 may be further configured by the switching signal to couple the first capacitor and the second capacitor together during the averaging phase to average (i.e., redistribute) the added or remaining charge during the averaging phase. The averaging circuit 940 may be further configured to average the first capacitor (C) during an averaging phase₁) (e.g., for mode 2) or a second capacitor (C)₂) (e.g., for mode 1) to output circuitry 950.

The 2C-DAC further includes an output circuit 950 that is coupled to the output of the 2C-DAC 910 during an output stage. The output circuit 950 may include a buffer amplifier for buffering the input from the averaging circuit 940The average voltage received to generate the output voltage (V) of the 2C-DAC_O). The output circuit may have an input capacitance (C)_IN) The input capacitance may prevent a portion of the charge (i.e., voltage) from reaching the output, which is based on the average voltage at the input.

To compensate for C_INFor output voltage (V)_O) The 2C-DAC 910 includes a capacitance compensation circuit 930. The capacitance compensation circuit comprises a replica input capacitance (C)_{IN_REP}). The replica input capacitance may be the input capacitance (C) of the buffer amplifier_IN) A replica (i.e., a duplicate) of (i.e., a duplicate) that has the same variation as the input voltage. The capacitance compensation circuit 930 may be configured by switching signals to charge or discharge the replica input capacitance during the input phase. The capacitance compensation circuit may be further configured to couple the replica input capacitance to the input capacitance during an averaging phase to average the added or remaining charge during the averaging phase to compensate the input capacitance versus the output voltage (V)_O) The influence of (c).

The disclosed 2C-DAC circuit may have advantages over digital-to-analog conversion circuits. For example, the disclosed 2C-DAC circuit may be low power, since only two capacitors are required for the conversion process. The disclosed 2C-DAC circuit may be highly accurate, at least due to its compensation for switched capacitances, capacitor mismatches, and input capacitances that otherwise may affect the accuracy of the conversion process. Which may occupy a small area in a silicon integrated circuit. For example, a 2C-DAC circuit using 4 picoFarad (pF) or 8pF capacitors and switches may require an area of 50 micrometers (μm) by 70 μm. Since the required custom layout is only for two capacitors, switches, buffer amplifiers and output capacitors, it is expected that design time will be minimized. The rest of the design is in the digital domain. Although the conversion process has a delay associated with serially processing each bit, this delay may be suitable for applications where there is no requirement for speed and high accuracy may be required for rail-to-rail conversion. For example, biomedical applications may have slowly varying conditions that can be processed by the disclosed 2C-DAC.

In the description and/or drawings, exemplary embodiments are disclosed. The present disclosure is not limited to these exemplary embodiments. The use of the term "and/or" includes any and all combinations of one or more of the associated listed items. The figures are schematic and therefore not necessarily drawn to scale. Unless otherwise indicated, the use of specific terms is intended in a generic and descriptive sense only and not for purposes of limitation.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. The term "comprising" and variants thereof, as used herein, are synonymous with the term "comprising" and variants thereof, and are open, non-limiting terms. The terms "optional" or "optionally" as used herein mean that the subsequently described feature, event, or circumstance may or may not occur, and that the description includes instances where said feature, event, or circumstance occurs and instances where it does not. Ranges can be expressed herein as from "about" one particular value, and/or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.

Some embodiments may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), silicon-on-insulator (SOI), fully depleted SOI (fdsoi), and the like.

While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It is to be understood that they have been presented by way of example only, and not limitation, and various changes in form and details may be made. Any portions of the apparatus and/or methods described herein can be combined in any combination, except mutually exclusive combinations. The embodiments described herein may include various combinations and/or subcombinations of the functions, components and/or features of the different embodiments described.

It will be understood that in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it can be directly on, connected to, or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, there are no intervening elements present. Although terms that are directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements illustrated as directly on, directly connected, or directly coupled may be referred to as such elements. The claims of this application, if any, may be modified to recite the exemplary relationships described in the specification or shown in the drawings.

As used in this specification, the singular forms "a", "an", and "the" may include the plural forms unless the context clearly dictates otherwise. Spatial relationship terms (e.g., above, over, upper, below, beneath, below, lower, etc.) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relational terms above and below may include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

Claims (13)

1. A dual capacitor digital to analog converter circuit, comprising:

a phase and mode controller configured to set an active bit in a digital word, select a mode condition of the active bit, and configure a switch according to a first mode or a second mode of a conversion process based on a value of the active bit and the selected mode condition;

a redistribution switch configured to couple the first capacitor and the second capacitor together to generate a redistribution voltage during a redistribution phase of the conversion process;

a buffer amplifier configured to generate an output voltage based on the redistributed voltage, the buffer amplifier having an input capacitance at an input; and

a capacitance compensation circuit comprising a replica input capacitance, the capacitance compensation circuit configured to:

coupling a reference voltage or ground to the replica input capacitance based on the value of the active bit during an input phase of the conversion process, and

coupling the replica input capacitance to the input capacitance to adjust the redistribution voltage during the redistribution phase of the conversion process.

2. The dual capacitor digital to analog converter circuit of claim 1, further comprising:

a first set of input switches configured to couple a first capacitor to a reference voltage or ground based on the value of the active bit during an input phase of the conversion process in the first mode; and

a second set of input switches configured to couple a second capacitor to the reference voltage or the ground based on the value of the active bit during the input phase of the conversion process in the second mode.

3. The dual capacitor digital to analog converter circuit of claim 1, further comprising:

an output switch configured to couple the output voltage to an output of the dual capacitor digital to analog converter circuit during an output phase of the conversion process.

4. The dual capacitor digital to analog converter circuit of claim 1, wherein said replica input capacitance is coupled to said input capacitance to adjust said redistribution voltage to reduce an effect of said input capacitance on said output voltage.

5. The dual capacitor digital to analog converter circuit of claim 1, wherein the capacitance compensation circuit comprises:

a first compensation input switch configured to couple the replica input capacitance to a reference voltage when the value of the active bit is one during the input phase of the conversion process in the first mode or the second mode;

a second compensation input switch configured to couple the replica input capacitance to ground when the value of the active bit is zero during the input phase of the conversion process in the first mode or the second mode;

a first compensation switch configured to capacitively couple the replica input to a positive terminal of the first capacitor during the redistribution phase of the conversion process in the first mode;

a second compensation switch configured to couple the replica input capacitance to a positive terminal of the second capacitor during the redistribution phase of the conversion process in the second mode;

a first capacitor coupling switch configured to couple the positive terminal of the first capacitor to the input capacitance at the input of the buffer amplifier during the input phase of the conversion process in the second mode; and

a second capacitor coupling switch configured to couple the positive terminal of the second capacitor to the input capacitance at the input of the buffer amplifier during the input phase of the conversion process in the first mode.

6. The dual capacitor digital to analog converter circuit of claim 1, wherein:

the buffer amplifier is an operational amplifier configured for unity gain and rail-to-rail operation, the input capacitance is present at an input of the operational amplifier, and

the capacitance compensation circuit includes a transistor configured to replicate the input capacitance of the operational amplifier.

7. The dual capacitor digital to analog converter circuit of claim 1, further comprising:

a sample-and-hold capacitor coupled to an output of the buffer amplifier; and

a first reset switch configured to discharge the first capacitor after the conversion process, a second reset switch configured to discharge the second capacitor after the conversion process, and a sample-and-hold reset switch configured to discharge the sample-and-hold capacitor after the conversion process.

8. A method of digital to analog conversion, the method comprising:

a mode condition that selects an active bit of the digital word;

determining a first mode or a second mode of the active bit based on the value of the active bit and the selected mode condition;

executing an input phase, the input phase comprising:

in a first mode, charging or discharging a first capacitor and a replica input capacitance according to the value of the active bit, an

In a second mode, charging or discharging a second capacitor and the replica input capacitance according to the value of the active bit; and

performing an averaging phase, the averaging phase comprising:

coupling the first capacitor and the second capacitor together to produce an average voltage of the active bit,

coupling the average voltage to a buffer amplifier having an input capacitance, an

The replica input capacitance and the input capacitance are coupled together to produce an adjusted average voltage of the active bit at the input of the buffer amplifier.

9. The digital-to-analog conversion method of claim 8, further comprising:

repeating the selecting, the determining, the performing the input phase, and the performing the averaging phase to obtain an adjusted average voltage for each bit of the digital word in the sequence;

outputting from the buffer amplifier an adjusted average voltage of a last bit of the digital word in the sequence as an output voltage, the output voltage corresponding to an analog conversion of the digital word;

discharging the first capacitor, the second capacitor, and the replica input capacitance;

receiving a new digital word;

repeating the selecting, the determining, the performing the input phase, and the performing the averaging phase to obtain an adjusted average voltage for each bit of the new digital word in the sequence; and

outputting the adjusted average voltage of the last bit of the digital words in the sequence as the output voltage, the output voltage corresponding to an analog conversion of the new digital word.

10. The digital to analog conversion method of claim 8, wherein selecting the mode condition of the active bit comprises:

determining a bit position of the active bit, the bit position ranging from a least significant bit, LSB, to a most significant bit, MSB; and

selecting a first mode condition or a second mode condition based on the bit position, the first mode condition and the second mode condition alternating sequentially for each bit position from the LSB to the MSB, wherein the first mode condition includes determining a first mode when a bit value of the active bit is zero and determining a second mode when the bit value of the active bit is one; and the second mode condition includes determining a second mode when the bit value of the active bit is zero and determining a first mode when the bit value of the active bit is one.

11. The digital-to-analog conversion method of claim 8, wherein coupling the average voltage to a buffer amplifier having an input capacitance during the averaging phase comprises:

in the first mode, coupling a positive terminal of the first capacitor and a positive terminal of the second capacitor to the input of the buffer amplifier; and

in the second mode, a positive terminal of the first capacitor and a positive terminal of the second capacitor are coupled to the input of the buffer amplifier.

12. A digital-to-analog conversion system, comprising:

a phase and mode controller configured to receive bits of a digital word and to output a switching signal according to an input phase, an averaging phase or an output phase of a conversion process and according to a first mode or a second mode determined for each bit of the digital word received at an input of the system;

an averaging circuit comprising a first capacitor and a second capacitor, the averaging circuit configured to charge or discharge the first capacitor or the second capacitor during an input phase and configured to couple the first capacitor and the second capacitor together during an averaging phase to produce an average voltage;

an output circuit including an input capacitance, the output circuit configured to generate an output voltage based on the average voltage received from the averaging circuit and configured to couple the output voltage to an output of the system during the output phase; and

a capacitance compensation circuit comprising a replica input capacitance substantially equal to the input capacitance, the capacitance compensation circuit configured to couple the replica input capacitance and the input capacitance together during an averaging phase to adjust the average voltage to compensate for the input capacitance.

13. The digital to analog conversion system of claim 12, wherein:

the stage and mode controller is configured to receive each bit of the digital word in sequence and to generate a switching signal according to a first mode condition or a second mode condition, the first mode condition and the second mode condition alternating for each bit in the sequence;

the output circuit includes an operational amplifier configured for unity gain, the operational amplifier having the input capacitance at an input of the operational amplifier, and

the capacitance compensation circuit includes a transistor configured to replicate the input capacitance of the operational amplifier.

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