CN113299683B

CN113299683B - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN113299683B
Application number: CN202110402587.9A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2022-09-06
Anticipated expiration: 2041-04-14
Also published as: CN113299683A

Abstract

The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises: at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a plurality of first address lines, a plurality of first phase change memory units, a plurality of second address lines, a plurality of second phase change memory units, a plurality of third address lines, a plurality of third phase change memory units, a plurality of fourth address lines, a plurality of fourth phase change memory units and a plurality of fifth address lines, wherein the first address lines, the first phase change memory units, the second address lines, the second phase change memory units, the third address lines, the third phase change memory units, the fourth address lines, the fourth phase change memory units and the fifth address lines are stacked and extend along a first direction; the first direction is vertical to the second direction; the lengths of the first address line, the third address line and the fifth address line along the first direction are basically the same as the lengths of the second address line and the fourth address line along the second direction, and the resistances of the first address line, the third address line and the fifth address line are basically the same as the resistances of the second address line and the fourth address line.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.

Background

Three-dimensional cross-point memories, such as Phase Change Memories (PCM), are a Memory technology that uses chalcogenides as the storage medium to store data by using the difference in resistance of the materials in different states. PCM has the advantages of bit-addressable, no data loss after power-off, high storage density, fast read-write speed, etc., and is considered as the most promising next-generation memory.

However, in the related art, three-dimensional cross-point memories also present various challenges.

Disclosure of Invention

In order to solve the related technical problems, an embodiment of the invention provides a three-dimensional memory.

An embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block;

the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units, a second address line layer, a plurality of second phase change memory units, a third address line layer, a plurality of third phase change memory units, a fourth address line layer, a plurality of fourth phase change memory units and a fifth address line layer which are arranged in a stacked mode; wherein the content of the first and second substances,

the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are parallel to each other; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the third address line layer comprises a plurality of third address lines which extend along the first direction; the fourth address line layer includes a plurality of fourth address lines each extending in a second direction; the fifth address line layer comprises a plurality of fifth address lines each extending in a first direction; the first direction is perpendicular to the second direction; the first phase change memory cell, the second phase change memory cell, the third phase change memory cell and the fourth phase change memory cell are vertical to the first address line, the second address line, the third address line, the fourth address line and the fifth address line; the third address line is overlapped with the projection part of the first address line on the first plane; the fourth address wire is overlapped with the projection part of the second address wire on the first plane; the fifth address line is coincident with a projection of the first address line on a first plane; the first plane is perpendicular to the stacking direction;

the lengths of the first address line, the third address line and the fifth address line along the first direction are basically the same as the lengths of the second address line and the fourth address line along the second direction, and the resistances of the first address line, the third address line and the fifth address line are basically the same as the resistances of the second address line and the fourth address line.

In the above scheme, the first address line includes a first sub-address line and a second sub-address line which are arranged in a stacked manner, and the materials of the first sub-address line and the second sub-address line are the same or different; the third address line comprises a fifth sub-address line and a sixth sub-address line which are arranged in a stacked mode, and the materials of the fifth sub-address line and the sixth sub-address line are the same or different; the fifth address line comprises a ninth sub-address line and a tenth sub-address line which are arranged in a stacked mode, and the materials of the ninth sub-address line and the tenth sub-address line are the same or different;

and/or the presence of a gas in the gas,

the second address line comprises a third sub-address line and a fourth sub-address line which are arranged in a stacked mode, and the materials of the third sub-address line and the fourth sub-address line are the same or different; the fourth address line comprises a seventh sub address line and an eighth sub address line which are arranged in a stacked mode, and the materials of the seventh sub address line and the eighth sub address line are the same or different.

In the above solution, the three-dimensional memory further includes: functional devices of the peripheral circuit;

the functional devices include a first functional device connected to the first address line, a second functional device connected to the second address line, a third functional device connected to the third address line, a fourth functional device connected to the fourth address line;

the fifth address line is connected with the first address line;

the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area; the third functional device is arranged on the seventh area and the eighth area; the fourth functional device is arranged on the ninth area, the tenth area, the eleventh area and the twelfth area;

the projection of the first area and the second area in the second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the seventh area and the eighth area have a common endpoint in the projection of the second direction; the ninth area and the tenth area have a common end point in the projection of the ninth area and the tenth area in the first direction, the tenth area and the eleventh area have a common end point in the projection of the eleventh area and the twelfth area in the first direction, and the eleventh area and the twelfth area have a common end point in the projection of the eleventh area in the first direction; the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area, the eighth area, the ninth area, the tenth area, the eleventh area and the twelfth area in the second direction is equal to the projection length of the first area and the second area in the second direction, and the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area, the eighth area, the ninth area, the tenth area, the eleventh area and the twelfth area in the first direction is equal to the projection length of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In the above solution, the pitches of the first address lines in the second direction are the same; the pitch of each second address line in the plurality of second address lines along the first direction is the same; the pitches of all third address lines in the plurality of third address lines along the second direction are the same; the pitches of the fourth address lines in the first direction are the same; and the pitches of the fifth address lines in the second direction are the same.

In the above solution, the three-dimensional memory further includes: a first connection in contact with the first address line, a second connection in contact with the second address line, a third connection in contact with the third address line, a fourth connection in contact with the fourth address line, and a fifth connection in contact with the fifth address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block by respective first connecting portions, the second functional devices are respectively connected to all second address lines in the memory cell array block by respective second connecting portions, the third functional devices are respectively connected to all third address lines in the memory cell array block by respective third connecting portions, the fourth functional devices are respectively connected to all fourth address lines in the memory cell array block by respective fourth connecting portions, and the fifth connecting portions are connected to the first address lines;

the first connecting part is contacted with the geometric center of the first address wire; the third connecting part is contacted with the geometric center of the third address line;

and/or the presence of a gas in the gas,

the second connection portion is in contact with a geometric center of the second address line; the fourth connection portion is in contact with a geometric center of the fourth address line.

In the above scheme, the three-dimensional memory further includes an interconnection layer, and the functional devices are connected to the corresponding connection portions through the interconnection layer.

In the above scheme, the functional device includes a decoder.

In the above scheme, one memory cell includes a phase change memory PCM element, a gate element, and a plurality of electrodes, which are stacked.

The embodiment of the invention also provides a manufacturing method of the three-dimensional memory, which comprises the following steps:

a plurality of first address lines forming a first address line layer, the plurality of first address lines each extending in a first direction;

forming a plurality of first phase change memory cells on the first address line layer;

forming a plurality of second address lines of a second address line layer on the plurality of first phase change memory cells, the plurality of second address lines each extending in a second direction perpendicular to the first direction; the first phase change memory cell is perpendicular to both the first address line and the second address line;

forming a plurality of second phase change memory cells on the second address line layer;

a plurality of third address lines forming a third address line layer on the plurality of second phase change memory cells, the plurality of third address lines each extending in the first direction; the second phase change memory unit is vertical to the second address line and the third address line;

forming a plurality of third phase change memory cells on the third address line layer;

a plurality of fourth address lines forming a fourth address line layer on the plurality of third phase change memory cells, the plurality of fourth address lines each extending in the second direction; the third phase change memory unit is vertical to the third address line and the fourth address line;

forming a plurality of fourth phase change memory cells on the fourth address line layer;

forming a plurality of fifth address lines of a fifth address line layer on the plurality of fourth phase change memory cells, the plurality of fifth address lines each extending in the first direction; the fourth phase change memory unit is vertical to the fourth address line and the fifth address line;

In the above-mentioned scheme, the first step of the method,

the step of forming each of the plurality of first address lines of the first address line layer includes: forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different; the step of forming each of a plurality of third address lines of the third address line layer includes: forming a fifth sub-address line on the second phase change memory unit, and forming a sixth sub-address line covering the fifth sub-address line on the fifth sub-address line; the materials of the fifth sub address line and the sixth sub address line are the same or different; the step of forming each fifth address line of the plurality of fifth address lines of the fifth address line layer includes: forming a ninth sub-address line on the fourth phase change memory unit, and forming a tenth sub-address line on the ninth sub-address line to cover the ninth sub-address line; the materials of the ninth sub address line and the tenth sub address line are the same or different;

and/or the presence of a gas in the gas,

the step of forming each of a plurality of second address lines of the second address line layer includes: forming a third sub-address line on the first phase change memory cell, and forming a fourth sub-address line on the third sub-address line to cover the third sub-address line; the materials of the third sub-address line and the fourth sub-address line are the same or different; the step of forming each of a plurality of fourth address lines of the fourth address line layer includes: forming a seventh sub-address line on the third phase change memory unit, and forming an eighth sub-address line on the seventh sub-address line to cover the seventh sub-address line; the materials of the seventh sub-address line and the eighth sub-address line are the same or different.

The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises:

at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units, a second address line layer, a plurality of second phase change memory units, a third address line layer, a plurality of third phase change memory units, a fourth address line layer, a plurality of fourth phase change memory units and a fifth address line layer which are arranged in a stacked mode; the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are parallel to each other; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the third address line layer includes a plurality of third address lines each extending in a first direction; the fourth address line layer comprises a plurality of fourth address lines each extending in a second direction; the fifth address line layer comprises a plurality of fifth address lines each extending in a first direction; the first direction is perpendicular to the second direction; the first phase change memory unit, the second phase change memory unit, the third phase change memory unit and the fourth phase change memory unit are vertical to the first address line, the second address line, the third address line, the fourth address line and the fifth address line; the third address line is overlapped with the projection part of the first address line on the first plane; the fourth address wire is overlapped with the projection part of the second address wire on the first plane; the projection of the fifth address line and the first address line on the first plane is coincident; the first plane is perpendicular to the stacking direction; the lengths of the first address line, the third address line and the fifth address line in the first direction are basically the same as the lengths of the second address line and the fourth address line in the second direction, and the resistances of the first address line, the third address line and the fifth address line are basically the same as the resistances of the second address line and the fourth address line. The lengths of the first address line, the third address line and the fifth address line in the first direction of the three-dimensional memory provided by the embodiment of the invention are equal to the lengths of the second address line and the fourth address line in the second direction, so that the number of phase change memory cells in a single memory cell array block is increased, the occupied space size of the single memory cell array block is also increased, namely the layout area of functional devices of a peripheral circuit corresponding to the single memory cell array block is also increased, and the increased area can better adapt to the requirements of the next generation chip size and circuit complexity.

Drawings

Fig. 1 is a schematic diagram of a memory cell array of a three-dimensional phase change memory observed by a scanning electron microscope provided in the related art;

FIG. 2a is a partial three-dimensional schematic diagram of a three-dimensional phase change memory having four layers of memory cells according to the related art;

FIG. 2b is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having four stacked memory cells according to the related art;

FIG. 2c is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having four stacked memory cells according to the related art;

FIG. 2d is a schematic diagram of a three-dimensional phase change memory cell array having four stacked memory cells according to the related art;

FIG. 2e is a partial horizontal schematic diagram illustrating a distribution of an area for disposing a functional device in a peripheral circuit of a three-dimensional phase change memory having four stacked memory cells according to the related art;

FIG. 3a is a partial three-dimensional schematic diagram of a three-dimensional phase change memory having four layers of memory cells according to an embodiment of the present invention;

FIG. 3b is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having four stacked memory cells according to an embodiment of the present invention;

FIG. 3c is a partial horizontal schematic diagram of a memory cell array of a three-dimensional phase change memory having four stacked memory cells according to an embodiment of the present invention;

fig. 4a to fig. 4g are schematic diagrams illustrating several different distribution situations of a setting region of a functional device corresponding to a memory cell block of a three-dimensional phase change memory having four stacked memory cells according to an embodiment of the present invention;

FIG. 5a is a diagram illustrating an exemplary distribution of placement areas of functional devices corresponding to 4 adjacent memory cell blocks in a three-dimensional phase change memory having four layers of memory cells according to an embodiment of the present invention;

FIG. 5b is a distribution of the first address line and the fifth address line based on FIG. 5 a;

FIG. 5c is a distribution of second address lines based on FIG. 5 a;

FIG. 5d is a distribution of third address lines based on FIG. 5 a;

FIG. 5e is a distribution of fourth address lines based on FIG. 5 a;

fig. 6a to fig. 6v are schematic diagrams illustrating an implementation process of a method for manufacturing a three-dimensional phase change memory according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.

The three-dimensional Memory according to the embodiment of the present invention may include a three-dimensional Memory including a bit line, a word line and a Memory cell, which are staggered horizontally and vertically, and includes but is not limited to a PCM, a Ferroelectric Memory (FeRAM), a magnetic Memory (MRAM), a Resistive Random Access Memory (RRAM), and a Resistive Random Access Memory (RRAM). Hereinafter, only PCM will be described as an example.

Fig. 1 is a partial cross-sectional view of a three-dimensional phase change memory cell array in the related art observed by a scanning electron microscope. As can be seen from fig. 1, the three-dimensional phase change memory chip is composed of a plurality of small memory cell array blocks having bit lines, word lines, and memory cells. Three-dimensional phase change memories generally include a top bit line, a word line, a bottom bit line, and a memory cell located at the intersection of the bit line and the word line. In practice, the word lines, the top bit lines and the bottom bit lines are generally formed of a constant line width (L/S) of 20nm/20nm formed after the patterning process.

To more clearly illustrate the scheme of the embodiment of the present invention, a three-dimensional phase change memory is introduced first, specifically:

the three-dimensional phase change memory comprises a memory cell array and a peripheral circuit (which can be simply called CMOS); wherein the memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, that is, they are formed on different planes. For example, the memory cell array may be formed over peripheral circuits to reduce the chip size.

In practice, the peripheral circuitry may include any suitable digital, analog, and/or mixed-signal circuitry for facilitating various operations of the PCM in performing read operations, write operations, erase operations, and the like. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers, and read/write circuits, among others. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated by the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data, and the data interaction is carried out with the outside through the data buffer.

In practical applications, the memory cell array is mainly used for storing data. In some embodiments, the architecture of the memory cell array may include memory cells having a one-layer stack, memory cells having a two-layer stack, memory cells having a four-layer stack, and the like.

In practical applications, each layer of memory cells may include a plurality of memory cells, and each memory cell in a memory cell layer may include a stacked PCM element, a gate element, and a plurality of electrodes. Heating or quenching the PCM element by the electrode through conduction of the gating element to realize switching between the crystalline state and the amorphous state of the PCM element; the storage of data is achieved by switching between the crystalline and amorphous states of the PCM element. In practice, the material of the PCM element comprises a chalcogenide based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the material of the gating element may comprise any suitable OTS material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, or the like; the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.

Fig. 2a to 2e are architecture diagrams illustrating a three-dimensional phase change memory having four layers of memory cells according to the related art. FIG. 2a is a partial three-dimensional schematic view of the three-dimensional phase change memory; FIG. 2b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y-direction; FIG. 2c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X-direction; FIG. 2d is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction; fig. 2e is a partial horizontal schematic view of a region of a peripheral circuit of the three-dimensional phase change memory, where a functional device of the peripheral circuit is disposed, as viewed in the Z direction.

It is understood that the three-dimensional phase-change memory cell array is placed in front, the Z direction is understood as a top view direction (a direction viewed from the top bit line to the bottom bit line), the Y direction is understood as a left view direction (a direction in which the bit lines extend), the X direction is understood as a front view direction (a direction in which the word lines extend), and the partial isometric view of the three-dimensional phase-change memory cell array shown in fig. 2a is an isometric view viewed from the left view direction.

With reference to fig. 2a to 2d, the three-dimensional phase change memory with four layers of memory cells includes: memory cell arrays and CMOS; wherein the memory cell array includes: a plurality of parallel first bit lines 41, a plurality of parallel first word lines 43, a plurality of parallel second bit lines 45, a plurality of parallel second word lines 47, a plurality of parallel third bit lines 49, a plurality of first memory cells 42 between the plurality of first bit lines 41 and the plurality of first word lines 43, a plurality of second memory cells 44 between the first word lines 43 and the second bit lines 45, a plurality of third memory cells 46 between the plurality of second bit lines 45 and the plurality of second word lines 47, and a plurality of fourth memory cells 48 between the second word lines 47 and the third bit lines 49. That is, the three-dimensional phase change memory includes three layers of bit lines, two layers of word lines, and four layers of memory cells. Wherein the first word line 43 includes a third sub-address line 43-1 and a fourth sub-address line 43-2 arranged in a cascade, and the second word line 47 includes a seventh sub-address line 47-1 and an eighth sub-address line 47-2 arranged in a cascade.

Wherein there is an offset between the second bit line 45 and the corresponding first bit line 41 (the one first bit line located below the second bit line). In practice, the offset here may refer to the offset shown in fig. 2b, which shows half the bit line length along the Y direction. The projections of the third bit line 49 and the corresponding first bit line 41 (one first bit line located below the third bit line) overlap in a first plane, where the first plane includes any plane perpendicular to the Z-axis. There is an offset between the second word line 47 and the corresponding first word line 43 (one first word line located below the second word line). In practice, the offset here may refer to the offset shown in fig. 2c, which shows half the word line length along the X direction. The first bit line 41, the second bit line 45, and the third bit line 49 are perpendicular to the first word line 43 and the second word line 47.

The first memory cell 42 is perpendicular to both the first bit line 41 and the first word line 43, the second memory cell 44 is perpendicular to both the first word line 43 and the second bit line 45, the third memory cell 46 is perpendicular to both the second bit line 45 and the second word line 47, and the fourth memory cell 48 is perpendicular to both the second word line 47 and the third bit line 49; each memory cell may include a stacked first electrode 401, a PCM element 402, a second electrode 403, a gate element 404, and a third electrode 405. In practical applications, the up-down positional relationship between the PCM element 402 and the gating element 404 is not limited.

The three-dimensional phase change memory with the four layers of memory cells further comprises: a third bit line connection 491 (here, the english language of the connection can be expressed as Contact, and the connection can also be called as Contact) which is in Contact with the third bit line 49 and is connected with the first bit line 41, and is used for connecting the third bit line 49 with a functional device of a peripheral circuit, such as a decoder; a second word line connection portion 471 which is in contact with the second word line 47 and extends from between the adjacent two second bit lines 45, the adjacent two first word lines 43, and the adjacent two first bit lines 41, and is used for connecting the second word line 47 with a functional device of a peripheral circuit, such as a decoder; a second bit line connecting portion 451 which is in contact with the second bit line 45 and extends between the adjacent two first word lines 43 and the adjacent two first bit lines 41, for connecting the second bit line 45 to a functional device of a peripheral circuit, such as a decoder; a first word line connection portion 431 which is in contact with the first word line 43 and extends from between two adjacent first bit lines 41, for realizing connection of the first word line 43 with a functional device of a peripheral circuit, such as a decoder; a first bit line connection portion 411 in contact with the first bit line 41 for implementing connection of the first bit line 41 to a functional device of a peripheral circuit, such as a decoder.

It should be noted that there may be no offset or a small offset along the X direction between the first bit line 41, the corresponding second bit line 45, and the corresponding third bit line 49, and in fig. 2d, in order to completely show the bit lines of each layer, there is an offset along the X direction between the first bit line 41, the corresponding second bit line 45, and the corresponding third bit line 49; the word line aspect also provides an offset between the first word line 43 and the corresponding second word line 47 in the Y direction for ease of illustration.

In the three-dimensional phase change memory having four layers of memory cells shown in fig. 2a to 2d, each bit line connection portion and each word line connection portion penetrate vertically (in the Z direction) from the memory cell array portion into the peripheral circuit portion. In order to ensure that the contact areas of the bit line connection portions and the word line connection portions with the decoders in the functional devices of the peripheral circuits are large enough to achieve sufficient contact, the contact positions of the adjacent first bit line connection portions 411 and the corresponding first bit lines 41 have a certain offset in the Y direction, the contact positions of the adjacent first word line connection portions 431 and the corresponding first word lines 43 have a certain offset in the X direction, the contact positions of the adjacent second bit line connection portions 451 and the corresponding second bit lines 45 have a certain offset in the Y direction, the contact positions of the adjacent second word line connection portions 471 and the corresponding second word lines 47 have a certain offset in the X direction, and the contact positions of the adjacent third bit line connection portions 491 and the corresponding third bit lines 49 have a certain offset in the Y direction.

Fig. 2e shows the distribution of the setting areas of the functional devices of the peripheral circuit corresponding to the architecture of fig. 2 d. The distribution of the layout areas of the functional devices of the peripheral circuits corresponding to one block of memory cells is shown in each of the dashed boxes in fig. 2 e. The memory cell array block herein is a minimum unit in a memory cell array of the three-dimensional memory, and the memory cell array is arranged to extend in the X direction and the Y direction, respectively, on the basis of the minimum unit to form the memory cell array of the three-dimensional memory. The functional devices of the peripheral circuit include a first bit line functional device (third bit line functional device), a first word line functional device, a second bit line functional device, and a second word line functional device; wherein the respective bit line functional devices are respectively connected to all bit lines in the memory cell array block through the respective bit line connections and are capable of selectively activating the respective bit lines; the respective word line function devices are respectively connected to all word lines in the memory cell array block through respective word line connection portions, and are capable of selectively activating the respective word lines.

It should be noted that, in practical applications, the number of memory cell blocks of the three-dimensional phase change memory having four layers of memory cells is not limited to 6 shown in fig. 2 d; the number of arrangement regions of the functional device of the three-dimensional phase change memory having four layers of memory cells is also not limited to 6 shown in fig. 2 e.

In the three-dimensional phase change memory having four layers of memory cells shown in fig. 2a to 2d, the thicknesses of the first bit line 41, the second bit line 45, and the third bit line 49 are all about half the thickness of the first word line 43 and the second word line 47, and in order to ensure that the resistances of the first bit line 41, the second bit line 45, and the third bit line 49 are all equivalent to the resistances of the first word line 43 and the second word line 47, the lengths of the first bit line 41, the second bit line 45, and the third bit line 49 in the first direction are all about half the lengths of the first word line 43 and the second word line 47 in the second direction, such that the number of bit lines in a single memory cell array block is twice the number of word lines. In practical applications, because the bit line functional devices corresponding to the first bit line 41, the second bit line 45, and the third bit line 49 and the word line functional devices corresponding to the first word line 43 and the second word line 47 must be located below the cell array block, when the occupied space size of a single memory cell array block is small, the CMOS area corresponding to the single memory cell array block is also very limited (i.e., the projection area on the plane formed by the single memory cell array block along the X and Y directions is limited), and the limited area may not meet the requirements of the next generation of chip size and circuit complexity.

Based on this, an embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block;

the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units, a second address line layer, a plurality of second phase change memory units, a third address line layer, a plurality of third phase change memory units, a fourth address line layer, a plurality of fourth phase change memory units and a fifth address line layer which are arranged in a stacked mode; wherein, the first and the second end of the pipe are connected with each other,

the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are parallel to each other; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the third address line layer includes a plurality of third address lines each extending in a first direction; the fourth address line layer comprises a plurality of fourth address lines each extending in a second direction; the fifth address line layer includes a plurality of fifth address lines each extending in a first direction; the first direction is perpendicular to the second direction; the first phase change memory unit, the second phase change memory unit, the third phase change memory unit and the fourth phase change memory unit are vertical to the first address line, the second address line, the third address line, the fourth address line and the fifth address line; the third address line is overlapped with the projection part of the first address line on the first plane; the fourth address line coincides with a projected portion of the second address line on a first plane; the projection of the fifth address line and the first address line on the first plane is coincident; the first plane is perpendicular to the stacking direction;

Fig. 3 a-3 c are architecture diagrams of a three-dimensional phase change memory having four layers of memory cells according to an embodiment of the present invention. FIG. 3a is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Y direction; FIG. 3b is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the X-direction; FIG. 3c is a partial horizontal schematic view of the memory cell array of the three-dimensional phase change memory viewed along the Z-direction.

Here, the second address line layer and the fourth address line layer have the same address line type, and may both include a word line layer or a bit line layer; the fifth address line layer, the third address line layer and the first address line layer comprise the same address line type, and can comprise word line layers or bit line layers. The first, third, and fifth address line layers must include different types of address lines than the second and fourth address line layers. Illustratively, the first address line layer may include a word line layer, and the third and fifth address line layers include a word line layer, and the second and fourth address line layers include a bit line layer; alternatively, the first address line layer may include a bit line layer, and the third and fifth address line layers may include a bit line layer, and the second and fourth address line layers may include a word line layer, respectively. In the embodiment of the invention, the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are all parallel to each other.

Here, the first address line, the second address line, the third address line, the fourth address line, and the fifth address line may include a plurality of word lines or bit lines, but the fifth address line and the third address line must be the same as the first address line, the second address line must be the same as the fourth address line, and the first address line, the third address line, and the fifth address line must be different from the second address line and the fourth address line. Illustratively, the first address line may include a plurality of word lines, the third address line and the fifth address line correspondingly also include a plurality of word lines, and the second address line and the fourth address line correspondingly include a plurality of bit lines; alternatively, the first address line may include a plurality of bit lines, the third address line and the fifth address line may include a plurality of bit lines, and the second address line and the fourth address line may include a plurality of word lines.

Here, the first direction is a direction in which the first address line, the third address line and the fifth address line extend, the second direction is a direction in which the second address line and the fourth address line extend, and the first direction is perpendicular to the second direction, that is, the first address line, the third address line and the fifth address line are all perpendicular to the second address line and the fourth address line. In practical applications, for convenience of understanding, an example will be described in which the first direction is a Y direction, the second direction is an X direction, the first address line is a first bit line, the second address line is a first word line, the third address line is a second bit line, the fourth address line is a second word line, and the fifth address line is a third bit line.

Here, the first plane may include a plane parallel to a plane formed by the first direction and the second direction, that is, a plane parallel to a plane formed by the X, Y direction. The projection of the third address lines and the projection of the first address lines on the first plane are overlapped, which may be understood as that each third address line and the corresponding first address line have an offset in the first plane and along the Y direction, and the offset may be the length of half of the first address line, or may be another amount. The projection parts of the fourth address lines and the second address lines on the first plane are overlapped, which can be understood that each fourth address line and the corresponding second address line have an offset in the first plane and along the projection of the X direction, and the offset can be the length of half of the second address line, or other quantities. The fifth address lines are coincident with the projections of the first address lines on the first plane, and each fifth address line is overlapped with the projection of the corresponding first address line on the first plane and along the Y direction.

Here, each memory cell of the plurality of first memory cells located between the first address line layer and the second address line layer is perpendicular to the respective first address line and the second address line; each memory cell of the plurality of second memory cells located between the second address line layer and the third address line layer is perpendicular to the respective second address line and third address line; each memory cell of the plurality of third memory cells located between the third address line layer and the fourth address line layer is perpendicular to the respective third address line and fourth address line; each memory cell of the plurality of fourth memory cells located between the fourth address line layer and the fifth address line layer is perpendicular to the respective fourth address line and the fifth address line. The specific structure of each memory cell has been described above, and is not described herein again.

Here, the lengths of the first address line, the third address line and the fifth address line in the first direction are all substantially the same as the lengths of the second address line and the fourth address line in the second direction, which may be understood as that the lengths of the first address line, the third address line and the fifth address line in the Y direction are equal to the lengths of the second address line and the fourth address line in the X direction, but a certain difference is allowed within a certain error range. Specifically, the error range of the length may include a fine design error range that is allowed to exist between the first address line, the second address line, the third address line, the fourth address line, and the fifth address line on the premise that the first address line, the second address line, the third address line, the fourth address line, and the fifth address line can be coupled with the same number of memory cells; the length error range may also include error differences due to manufacturing. The length error range includes, but is not limited to, the above two cases.

The resistances of the first address line, the third address line and the fifth address line are basically the same as the resistances of the second address line and the fourth address line, and the resistances of the first address line, the third address line and the fifth address line can be equal to the resistances of the second address line and the fourth address line, but a certain difference is allowed within a certain error range. Specifically, the resistance error range may include a small design error range that does not affect the electrical performance of the first address line, the second address line, the third address line, the fourth address line, and the fifth address line on the premise that the first address line, the second address line, the third address line, the fourth address line, and the fifth address line can be coupled to the same number of memory cells. The resistance error range may also include manufacturing-induced error variations. The resistance error range includes, but is not limited to, the above two cases.

It can be understood that, on the basis of the related art, the lengths of the first address line, the third address line and the fifth address line in the embodiment of the present invention along the Y direction are increased by about one time, so that the memory cells in a single memory cell array block are increased by about two times in the related art, that is, the size of the space occupied by the single memory cell array block is also increased by about one time, the area in which the functional devices of the peripheral circuit corresponding to the single memory cell array block can be arranged is also increased by about one time, and the increased area can better meet the requirements of the next generation of chip size and circuit complexity.

Here, in order to make the resistances of the first address line, the third address line and the fifth address line equal to the resistances of the second address line and the fourth address line, the thicknesses and materials of the first address line, the third address line, the fifth address line and/or the second address line and the fourth address line can be adjusted accordingly.

In some embodiments, the first address line comprises a first sub-address line and a second sub-address line which are arranged in a stacked mode, and the materials of the first sub-address line and the second sub-address line are the same or different; the third address line comprises a fifth sub address line and a sixth sub address line which are arranged in a stacked mode, and the materials of the fifth sub address line and the sixth sub address line are the same or different; the fifth address line comprises a ninth address sub-line and a tenth address sub-line which are arranged in a stacked mode, and the materials of the ninth address sub-line and the tenth address sub-line are the same or different;

and/or the presence of a gas in the atmosphere,

In practical applications, as shown in FIGS. 3 a-3 c, the first address line may be configured as a two-layer structure including the first sub-address line 41-1 and the second sub-address line 41-2, the second address line may be configured as a two-layer structure including the third sub-address line 43-1 and the fourth sub-address line 43-2, the third address line may be configured as a two-layer structure including the fifth sub-address line 45-1 and the sixth sub-address line 45-2, the fourth address line may be configured as a two-layer structure including the seventh sub-address line 47-1 and the eighth sub-address line 47-2, and the fifth address line may be configured as a two-layer structure including the ninth sub-address line 49-1 and the tenth sub-address line 49-2.

Here, the materials constituting the first sub-address line 41-1, the second sub-address line 41-2, the third sub-address line 43-1 and the fourth sub-address line 43-2, the fifth sub-address line 45-1, the sixth sub-address line 45-2, the seventh sub-address line 47-1, the eighth sub-address line 47-2, the ninth sub-address line 49-1, the tenth sub-address line 49-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto.

It is to be understood that the first sub-address line 41-1 and the second sub-address line 41-2 are in parallel, the third sub-address line 43-1 and the fourth sub-address line 43-2 are in parallel, the fifth sub-address line 45-1 and the sixth sub-address line 45-2 are in parallel, the seventh sub-address line 47-1 and the eighth sub-address line 47-2 are in parallel, and the ninth sub-address line 49-1 and the tenth sub-address line 49-2 are also in parallel. The sub-address lines are arranged so that the resistance of the address lines can be adjusted more precisely. The materials of the first sub-address line 41-1, the second sub-address line 41-2, the third sub-address line 43-1, the fourth sub-address line 43-2, the fifth sub-address line 45-1, the sixth sub-address line 45-2, the seventh sub-address line 47-1, the eighth sub-address line 47-2, the ninth sub-address line 49-1 and the tenth sub-address line 49-2 can be selected in various ways according to different requirements of the phase change memory, and in order to ensure that the resistances of the first address line, the third address line and the fifth address line are equal to the resistances of the second address line and the fourth address line, the first sub-address line 41-1, the second sub-address line 41-2, the third sub-address line 43-1, the fourth sub-address line 43-2 and the fifth sub-address line 45-1 can be selected according to the selected materials, The thicknesses of the sixth sub-address line 45-2, the seventh sub-address line 47-1, the eighth sub-address line 47-2, the ninth sub-address line 49-1 and the tenth sub-address line 49-2 are adjusted accordingly.

Illustratively, when the materials of the first address line, the second address line, the third address line, the fourth address line and the fifth address line are the same, the first address line, the second address line, the third address line, the fourth address line and the fifth address line may be provided with a considerable thickness to ensure that the lengths of the first address line, the second address line, the third address line, the fourth address line and the fifth address line are the same and the resistances are comparable.

Illustratively, when the material of the first sub-address line 41-1 and the material of one of the second sub-address lines 41-2 are the same as the material of the second address line, and the material of the first sub-address line 41-1 and the material of the second sub-address line 41-2 are different, the resistances of the first sub-address line 41-1 and the second sub-address line 41-2 with the same thickness are different, and then the first address line and the second address line should be set with different thicknesses according to the relationship between the material thickness and the resistance to ensure that the lengths of the first address line and the second address line are the same and the resistances are equivalent.

In some embodiments, one memory cell includes a phase change memory PCM element, a gating element, and a plurality of electrodes arranged in a stack.

As can be seen from fig. 2d, since first bit line connection portion 411, first word line connection portion 431, second bit line connection portion 451, and second word line connection portion 471 vertically enter the peripheral circuits, based on this, in one memory cell array block, a first vertical stripe area of fig. 2d is left between two first bit lines 41 located in the middle in order to avoid the first word line connection portion 431 corresponding to first word line 43 extending into the peripheral circuits. Meanwhile, a second vertical bar region dedicated to the placement of the second word line connection part 471 is also set free between two adjacent memory cell array blocks. It can be seen that no bit lines and memory cells are provided in the first and second vertical stripe regions for data storage. The first vertical bar corresponds to a dedicated area of the wordline function device, shown as

areas

3 and 4 in fig. 2e, and the second vertical bar corresponds to a dedicated area of the wordline function device, shown as

areas

9 and 10 in fig. 2 e. Meanwhile, in one memory cell array block, the middle two first word lines 43 also give up a third vertical stripe region corresponding to a dedicated region dedicated to the placement of a third bit line functional device (first bit line functional device), which includes the illustrated

regions

1 and 2 in fig. 2 e. At the same time, between two adjacent memory cell array blocks, a fourth vertical stripe region corresponding to a dedicated region dedicated to the placement of a second bit line functional device is also created, which includes the illustrated region 7 and region 8 in fig. 2 e.

It is understood that the vertical bars provided to extend the word line connection portions and the bit line connection portions occupy a large portion of the area of the substrate, but do not provide any word line, bit line or memory cell for data storage, and thus, the presence of the vertical bars reduces the array efficiency, i.e., the three-dimensional phase change memory having four layers of memory cells has a problem of low array efficiency.

Based on this, in some embodiments, the three-dimensional memory further comprises: functional devices of peripheral circuits;

the fifth address line is connected with the first address line;

the first functional device is arranged on the first area and the second area; the second functional device is arranged on the third area, the fourth area, the fifth area and the sixth area; the third functional device is arranged on the seventh area and the eighth area; the fourth functional device is disposed on the ninth region, the tenth region, the eleventh region, and the twelfth region;

the projection of the first area and the second area in a second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the seventh area and the eighth area have a common endpoint in the projection of the second direction; the ninth area and the tenth area have a common end point in the projection of the ninth area and the tenth area in the first direction, the tenth area and the eleventh area have a common end point in the projection of the eleventh area and the twelfth area in the first direction, and the eleventh area and the twelfth area have a common end point in the projection of the eleventh area in the first direction; the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area, the eighth area, the ninth area, the tenth area, the eleventh area and the twelfth area in the second direction is equal to the projection length of the first area and the second area in the second direction, and the projection length of the first area, the second area, the third area, the fourth area, the fifth area, the sixth area, the seventh area, the eighth area, the ninth area, the tenth area, the eleventh area and the twelfth area in the first direction is equal to the projection length of the third area, the fourth area, the fifth area and the sixth area in the first direction.

In some embodiments, the functional device comprises a decoder.

Here, the three-dimensional memory includes functional devices of peripheral circuits in addition to the memory cell array block; wherein the memory cell array includes at least one memory cell array block, and the functional device of the peripheral circuit includes at least one decoder. In practical applications, in order to avoid insufficient driving force or excessive line loss, one memory cell array block corresponds to one decoder, that is, one decoder is responsible for controlling activation of all word lines and bit lines in one memory cell array block. In the embodiment of the invention, the architecture of the memory cell array is at least provided with four layers of memory cells.

Here, since the fifth address line is connected to the first address line, that is, the first bit line and the third bit line are connected together in the CMOS, the first bit line and the third bit line are controlled by the same functional device. The functional devices include a first functional device (first bit line functional device) connected to a first address line and a fifth address line, a second functional device (first word line functional device) connected to a second address line, a third functional device (second bit line functional device) connected to a third address line, and a fourth functional device (second word line functional device) connected to a fourth address line. In the embodiment of the invention, the area where the first word line function device corresponding to one memory cell array is located is divided into four parts and is shifted, the area where the first bit line function device corresponding to one memory cell array is located is divided into two parts and is shifted, the area where the second bit line function device corresponding to one memory cell array is located is divided into two parts and is shifted, and the area where the second word line function device corresponding to one memory cell array is located is divided into four parts and is shifted, so that bit lines, word lines and memory cells are allowed to be introduced above the area where the word line function device is located and the area where the corresponding bit line function device is located, and thus, the array efficiency of the three-dimensional memory is greatly improved.

The specific distribution of the areas where the word line functional devices and the bit line functional devices corresponding to one memory cell array are located will be described in detail below.

Fig. 4a to 4g are several different distribution situations of the setting region of the functional device corresponding to one memory cell block in the three-dimensional memory having four layers of memory cells according to the embodiment of the present invention. The dashed black lines in fig. 4 a-4 g represent the substrate area occupied by the placement area of one functional device in an embodiment of the present invention.

In connection with fig. 4 a-4 g, it can be understood that in the embodiment of the present invention, the first functional device is disposed on the first region (region 1 shown in fig. 4 a-4 g) and the second region (region 2 shown in fig. 4 a-4 g), and the second functional device is disposed on the third region (region 3 shown in fig. 4 a-4 g), the fourth region (region 4 shown in fig. 4 a-4 g), the fifth region (region 5 shown in fig. 4 a-4 g), the sixth region (region 6 shown in fig. 4 a-4 g). The third functional device is provided on a seventh region (region 7 shown in fig. 4a to 4 g) and an eighth region (region 8 shown in fig. 4a to 4 g), and the fourth functional device is provided on a ninth region (region 9 shown in fig. 4a to 4 g), a tenth region (region 10 shown in fig. 4a to 4 g), an eleventh region (region 11 shown in fig. 4a to 4 g), a twelfth region (region 12 shown in fig. 4a to 4 g). In practical application, the first region, the second region, the third region, the fourth region, the fifth region, the sixth region, the seventh region, the eighth region, the ninth region, the tenth region, the eleventh region and the twelfth region are all square regions and are located at positions which are not overlapped with each other in the same plane.

Here, the end point may be understood as an end point of a projection line segment formed by projecting each region in the corresponding direction. The projection of the first region in the second direction and the projection of the second region in the second direction have a common endpoint may be understood as follows: the first region and the second region are seamlessly connected along the second direction, so that the occupied size of a functional device arrangement region along the second direction can be reduced relative to that of fig. 2 e. The projection of the third region in the first direction and the projection of the fourth region in the first direction have a common end point, which may be understood as seamless connection between the third region and the fourth region in the first direction, the projection of the fourth region in the first direction and the projection of the fifth region in the first direction have a common end point, which may be understood as seamless connection between the fourth region and the fifth region in the first direction, and the projection of the fifth region in the first direction and the projection of the sixth region in the first direction have a common end point, which may be understood as seamless connection between the fifth region and the sixth region in the first direction, so that, with respect to fig. 2e, the size of one functional device arrangement region in the first direction may be reduced. Meanwhile, the projection of the seventh area in the second direction and the projection of the eighth area in the second direction have a common end point, which can be understood as that the seventh area and the eighth area are seamlessly connected along the second direction, so that, compared with fig. 2e, the size of one functional device installation area along the second direction can be reduced. The projection of the ninth area in the first direction and the projection of the tenth area in the first direction have a common end point which can be understood as seamless connection between the ninth area and the tenth area along the first direction, the projection of the tenth area in the first direction and the projection of the eleventh area in the first direction have a common end point which can be understood as seamless connection between the tenth area and the eleventh area along the first direction, and the projection of the eleventh area in the first direction and the projection of the twelfth area in the first direction have a common end point which can be understood as seamless connection between the eleventh area and the twelfth area along the first direction, so that the size occupied by one functional device arrangement area along the first direction can be reduced relative to fig. 2 e.

Here, the projection lengths of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth regions in the second direction are equal to the projection lengths of the first and second regions in the second direction, and it can be understood that the length of the arrangement region of the functional device corresponding to a single memory cell array block in the second direction is the total length of the first and second regions in the second direction. The projection length of the first region, the second region, the third region, the fourth region, the fifth region, the sixth region, the seventh region, the eighth region, the ninth region, the tenth region, the eleventh region and the twelfth region in the first direction is equal to the projection length of the third region, the fourth region, the fifth region and the sixth region in the first direction, and it can be understood that the length of the setting region of the functional device corresponding to a single memory cell array block in the first direction is the total length of the third region, the fourth region, the fifth region and the sixth region in the first direction.

In some embodiments, the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitches of the second address lines in the first direction are the same; the pitches of all third address lines in the plurality of third address lines along the second direction are the same; the pitches of the fourth address lines in the first direction are the same; and the pitches of the fifth address lines in the second direction are the same.

In the embodiment of the present invention, no relevant vacancy needs to be left between the two bit lines in the middle, and no relevant vacancy needs to be left between the two word lines in the middle. That is, the pitches of the first address lines in the second direction are the same; the pitches of the second address lines in the first direction in the second address lines are the same; the pitches of all third address lines in the plurality of third address lines along the second direction are the same; the pitches of the fourth address lines in the first direction are the same; and the pitches of the fifth address lines in the second direction are the same.

To further explain the arrangement of the first address line, the second address line, the third address line, the fourth address line, and the fifth address line in the embodiment of the present invention, a detailed description will be given below by taking the distribution of the setting area of the functional device corresponding to one memory cell block shown in fig. 4a as an example.

Fig. 5a is a distribution of the layout areas of the functional devices corresponding to 4 adjacent memory cell blocks in the three-dimensional memory having four layers of memory cells according to the embodiment of the present invention; FIG. 5b is a distribution of the first address line and the fifth address line based on FIG. 5 a; FIG. 5c is a distribution of second address lines based on FIG. 5 a; FIG. 5d is a distribution of third address lines based on FIG. 5 a; fig. 5e shows a distribution of the fourth address lines based on fig. 5 a.

In some embodiments, the three-dimensional memory further comprises: a first connection in contact with the first address line, a second connection in contact with the second address line, a third connection in contact with the third address line, a fourth connection in contact with the fourth address line, and a fifth connection in contact with the fifth address line; wherein the first functional devices are respectively connected to all first address lines in the memory cell array block by respective first connecting portions, the second functional devices are respectively connected to all second address lines in the memory cell array block by respective second connecting portions, the third functional devices are respectively connected to all third address lines in the memory cell array block by respective third connecting portions, the fourth functional devices are respectively connected to all fourth address lines in the memory cell array block by respective fourth connecting portions, and the fifth connecting portions are connected to the first address lines;

and/or the presence of a gas in the gas,

In practice, the first functional device is connected to all the first address lines and the fifth address lines in the memory cell array block through corresponding first connecting portions contacting the first address lines, the second functional device is connected to all the second address lines in the memory cell array block through corresponding second connecting portions contacting the second address lines, the third functional device is connected to all the third address lines in the memory cell array block through corresponding third connecting portions contacting the third address lines, and the fourth functional device is connected to all the fourth address lines in the memory cell array block through corresponding fourth connecting portions contacting the fourth address lines. It is understood that the first connection portion contacts with the geometric center of the first address line, the third connection portion contacts with the geometric center of the third address line, and the fifth connection portion contacts with the geometric center of the fifth address line; and/or when the second connecting part is contacted with the geometric center of the second address wire and the fourth connecting part is contacted with the geometric center of the fourth address wire, the whole structure is more uniform and symmetrical, the interconnection wiring difficulty is lower, and the parasitic series resistance of the bit line is lower.

In some embodiments, the three-dimensional memory further includes an interconnect layer through which the functional devices are connected with the respective connections.

In practical application, when the first connection part contacts with the geometric center of the first address line, the third connection part contacts with the geometric center of the third address line, and the fifth connection part contacts with the geometric center of the fifth address line; and/or when the second connecting part contacts with the geometric center of the second address wire and the fourth connecting part contacts with the geometric center of the fourth address wire, the first connecting part, the second connecting part, the third connecting part and the fourth connecting part cannot directly land on the arrangement area of the corresponding functional device when vertically downwards so as to be connected with the corresponding functional device. At this time, the first and second connection portions, the third connection portion, and the fourth connection portion may be connected to the corresponding functional devices through the interconnection layer.

An embodiment of the present invention provides a three-dimensional memory, including: at least one memory cell array block; the memory cell array block includes at least: the phase change memory comprises a first address line layer, a plurality of first phase change memory units, a second address line layer, a plurality of second phase change memory units, a third address line layer, a plurality of third phase change memory units, a fourth address line layer, a plurality of fourth phase change memory units and a fifth address line layer which are arranged in a stacked mode; the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are parallel to each other; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the third address line layer includes a plurality of third address lines each extending in a first direction; the fourth address line layer comprises a plurality of fourth address lines each extending in a second direction; the fifth address line layer includes a plurality of fifth address lines each extending in a first direction; the first direction is perpendicular to the second direction; the first phase change memory unit, the second phase change memory unit, the third phase change memory unit and the fourth phase change memory unit are vertical to the first address line, the second address line, the third address line, the fourth address line and the fifth address line; the third address line is overlapped with the projection part of the first address line on the first plane; the fourth address wire is overlapped with the projection part of the second address wire on the first plane; the projection of the fifth address line and the first address line on the first plane is coincident; the first plane is perpendicular to the stacking direction; the lengths of the first address line, the third address line and the fifth address line along the first direction are basically the same as the lengths of the second address line and the fourth address line along the second direction, and the resistances of the first address line, the third address line and the fifth address line are basically the same as the resistances of the second address line and the fourth address line. The lengths of the first address line, the third address line and the fifth address line in the three-dimensional memory provided by the embodiment of the invention along the first direction are all equal to the lengths of the second address line and the fourth address line along the second direction, so that the number of phase change memory cells in a single memory cell array block is increased, the occupied space size of the single memory cell array block is also increased, namely the layout area of functional devices of a peripheral circuit corresponding to the single memory cell array block is also increased, and the increased area can better adapt to the requirements of the next generation of chip size and circuit complexity.

Based on the three-dimensional memory, the embodiment of the invention also provides a manufacturing method of the three-dimensional memory, which comprises the following steps:

forming a plurality of third address lines of a third address line layer on the plurality of second phase change memory cells, the plurality of third address lines each extending in the first direction; the second phase change memory unit is vertical to the second address line and the third address line;

forming a plurality of fifth address lines of a fifth address line layer on the plurality of fourth phase change memory cells, the plurality of fifth address lines each extending in the first direction; the fourth phase change memory cell is perpendicular to both the fourth address line and the fifth address line;

In some embodiments of the present invention, the,

the step of forming each of the plurality of first address lines of the first address line layer includes: forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different; the step of forming each of a plurality of third address lines of the third address line layer includes: forming a fifth sub-address line on the second phase change memory unit, and forming a sixth sub-address line on the fifth sub-address line to cover the fifth sub-address line; the materials of the fifth sub address line and the sixth sub address line are the same or different; the step of forming each of a plurality of fifth address lines of the fifth address line layer includes: forming a ninth sub-address line on the fourth phase change memory unit, and forming a tenth sub-address line on the ninth sub-address line to cover the ninth sub-address line; the materials of the ninth sub address line and the tenth sub address line are the same or different;

and/or the presence of a gas in the gas,

In some embodiments, the method further comprises:

forming a first functional device connected to the first address line on the first area and the second area;

forming a second functional device connected to the second address line over the third region, the fourth region, the fifth region, and the sixth region;

forming a third functional device connected to the third address line on a seventh area and an eighth area;

forming a fourth functional device connected to a fourth address line on the ninth area, the tenth area, the eleventh area, and the twelfth area;

In some embodiments, the method further comprises:

forming a first connection portion contacting a first address line before forming the first address line;

forming a second connection portion contacting the second address line before forming the second address line;

forming a third connection portion contacting a third address line before forming the third address line;

forming a fourth connection portion in contact with a fourth address line before forming the fourth address line;

forming a fifth connection portion in contact with a fifth address line before forming the fifth address line; wherein, the first and the second end of the pipe are connected with each other,

and/or the presence of a gas in the gas,

the second connection portion is in contact with a geometric center of the second address line.

The following describes the method for manufacturing the three-dimensional memory in the embodiment of the invention in detail with reference to fig. 6a to 6 v.

As shown in fig. 6a to 6b, the first bit line connection 411 is formed. Forming a plurality of first bit lines 41 on the first bit line connection parts 411, the first bit lines 41 including two parts: the first sub-address line 41-1 and the second sub-address line 41-2 are formed by, as shown in fig. 6 c-6 d, first forming the first sub-address line 41-1 on the first bit line connecting portion 411, where the first sub-address line 41-1 is formed by first depositing a material for forming the first sub-address line 41-1, and then removing a portion of the material for forming the first sub-address line 41-1 by etching or the like, so as to form the first sub-address line 41-1, or by first depositing a dielectric material, and then removing a portion of the dielectric material by etching to form a trench, and filling the material for forming the first sub-address line 41-1 in the trench, so as to form the first sub-address line 41-1. As shown in fig. 6e-6f, the second sub-address line 41-2 is formed on the first sub-address line 41-1; and a first phase change memory cell layer 42' is formed on the second sub-address line 41-2. As shown in FIGS. 6g-6h, a first phase change memory cell 42 is formed on the second sub-address line 41-2. Forming a first word line 43 on the first phase change memory cell 42, the first word line 43 comprising two portions: the third sub-address line 43-1 and the fourth sub-address line 43-2, as shown in FIGS. 6g-6h, form the third sub-address line 43-1 on the first phase-change memory cell 42, and form the first word line connection 431 before forming the third sub-address line 43-1; as shown in fig. 6i-6j, the fourth sub-address line 43-2 is formed on the third sub-address line 43-1. Through the manufacturing process, the three-dimensional memory with the layer of memory cells is formed.

The dielectric material includes, but is not limited to, silicon nitride and silicon oxide

Here, the method of forming the second sub-address line 41-2, the third sub-address line 43-1 and the fourth sub-address line 43-2 is similar to the method of forming the first sub-address line 41-1, and two methods may be included, which are not described herein again.

Here, the materials constituting the first sub-address line 41-1, the second sub-address line 41-2, the third sub-address line 43-1, and the fourth sub-address line 43-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto. And the constituent materials of the first sub-address line 41-1 and the second sub-address line 41-2 may be the same or different, and the constituent materials of the third sub-address line 43-1 and the fourth sub-address line 43-2 may be the same or different.

On the basis of the above-described three-dimensional memory in which memory cells are stacked in one layer, as shown in fig. 6i to 6j, the second phase change memory cell 44 is formed on the fourth sub-address line 43-2, and the second bit line connection portion 451 is formed. Forming a second bit line 45 on the second phase change memory cell 44, the second bit line 45 comprising two portions: the fifth sub-address line 45-1 and the sixth sub-address line 45-2, as shown in fig. 6k-6l, form the fifth sub-address line 45-1 on the second phase change memory unit 44; as shown in fig. 6m-6n, a sixth sub-address line 45-2 is formed on the fifth sub-address line 45-1, and a third phase change memory cell layer 46' is formed on the sixth sub-address line 45-2. As shown in fig. 6o-6p, a third phase change memory cell 46 is formed on the sixth sub-address line 45-2. Forming a second word line 47 on the third phase change memory cell 46, the second word line 47 comprising two portions: the seventh sub-address line 47-1 and the eighth sub-address line 47-2, as shown in FIGS. 6o-6p, form the seventh sub-address line 47-1 on the third phase change memory cell 46, and form the second word line connection 471 before forming the seventh sub-address line 47-1; as shown in fig. 6q-6r, an eighth sub-address line 47-2 is formed on the seventh sub-address line 47-1, and a fourth phase change memory cell 48 is formed on the eighth sub-address line 47-2. Forming a third bit line 49 over a fourth phase change memory cell 48, the third bit line 49 comprising two parts: ninth sub-address line 49-1 and tenth sub-address line 49-2, as shown in FIGS. 6s-6t, ninth sub-address line 49-1 is formed on fourth phase change memory cell 48, and third bit line connection 491 is formed before ninth sub-address line 49-1 is formed; as shown in FIGS. 6u-6v, a tenth sub-address line 49-2 is formed over the ninth sub-address line 49-1. Through the manufacturing process, the three-dimensional memory with the four-layer stacked memory cells is formed.

Here, the method of forming the fifth sub-address line 45-1, the sixth sub-address line 45-2, the seventh sub-address line 47-1, the eighth sub-address line 47-2, the ninth sub-address line 49-1 and the tenth sub-address line 49-2 is similar to the aforementioned method of forming the first sub-address line 41-1, and two methods may be included, which will not be described again.

Here, the materials constituting the fifth sub-address line 45-1, the sixth sub-address line 45-2, the seventh sub-address line 47-1, the eighth sub-address line 47-2, the ninth sub-address line 49-1, and the tenth sub-address line 49-2 may include: tungsten (W), cobalt (Co), copper (Cu), but not limited thereto. And the composition materials of the fifth sub-address line 25-1 and the sixth sub-address line 25-2 can be the same or different, the composition materials of the seventh sub-address line 47-1 and the eighth sub-address line 47-2 can be the same or different, and the composition materials of the ninth sub-address line 49-1 and the tenth sub-address line 49-2 can be the same or different.

In practical applications, methods for forming the corresponding connection portion, the address line, and the memory cell are mature in the related art, and are not described herein again.

It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A three-dimensional memory, comprising: at least one memory cell array block;

the first address line layer, the second address line layer, the third address line layer, the fourth address line layer and the fifth address line layer are parallel to each other; the first address line layer includes a plurality of first address lines each extending in a first direction; the second address line layer includes a plurality of second address lines each extending in a second direction; the third address line layer includes a plurality of third address lines each extending in a first direction; the fourth address line layer includes a plurality of fourth address lines each extending in a second direction; the fifth address line layer includes a plurality of fifth address lines each extending in a first direction; the first direction is perpendicular to the second direction; the first phase change memory unit, the second phase change memory unit, the third phase change memory unit and the fourth phase change memory unit are vertical to the first address line, the second address line, the third address line, the fourth address line and the fifth address line; the third address line is overlapped with the projection part of the first address line on the first plane; the fourth address wire is overlapped with the projection part of the second address wire on the first plane; the projection of the fifth address line and the first address line on the first plane is coincident; the first plane is perpendicular to the stacking direction;

2. The three-dimensional memory according to claim 1, wherein the first address lines comprise a first sub address line and a second sub address line which are arranged in a stacked manner, and the materials of the first sub address line and the second sub address line are the same or different; the third address line comprises a fifth sub-address line and a sixth sub-address line which are arranged in a stacked mode, and the materials of the fifth sub-address line and the sixth sub-address line are the same or different; the fifth address line comprises a ninth sub-address line and a tenth sub-address line which are arranged in a stacked mode, and the materials of the ninth sub-address line and the tenth sub-address line are the same or different;

and/or the presence of a gas in the gas,

3. The three-dimensional memory according to claim 1, further comprising: functional devices of the peripheral circuit;

the fifth address line is connected with the first address line;

the projection of the first area and the second area in the second direction have a common endpoint; the third area and the fourth area have a common end point in the projection of the third area and the fourth area in the first direction, the fourth area and the fifth area have a common end point in the projection of the fifth area in the first direction, and the fifth area and the sixth area have a common end point in the projection of the sixth area in the first direction; the seventh area and the eighth area have a common endpoint in the projection of the second direction; the ninth area and the tenth area have a common end point in the projection of the ninth area and the tenth area in the first direction, the tenth area and the eleventh area have a common end point in the projection of the eleventh area and the twelfth area in the first direction, and the eleventh area and the twelfth area have a common end point in the projection of the eleventh area in the first direction; the projection lengths of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth areas in the second direction are equal to the projection lengths of the first and second areas in the second direction, and the projection lengths of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth areas in the first direction are equal to the projection lengths of the third, fourth, fifth and sixth areas in the first direction.

4. The three-dimensional memory according to claim 3, wherein the first address lines of the plurality of first address lines are equally spaced along the second direction; the pitches of the second address lines in the first direction are the same; the pitches of all third address lines in the plurality of third address lines along the second direction are the same; the pitches of the fourth address lines in the first direction are the same; and the pitches of the fifth address lines in the second direction are the same.

5. The three-dimensional memory according to claim 3, further comprising: a first connection in contact with the first address line, a second connection in contact with the second address line, a third connection in contact with the third address line, a fourth connection in contact with the fourth address line, and a fifth connection in contact with the fifth address line; wherein the first functional devices are connected to all first address lines in the memory cell array block by respective first connection portions, the second functional devices are connected to all second address lines in the memory cell array block by respective second connection portions, the third functional devices are connected to all third address lines in the memory cell array block by respective third connection portions, the fourth functional devices are connected to all fourth address lines in the memory cell array block by respective fourth connection portions, and the fifth connection portions are connected to the first address lines;

and/or the presence of a gas in the gas,

6. The three-dimensional memory according to claim 5, further comprising an interconnect layer through which the functional devices are connected with respective connections.

7. The three-dimensional memory according to claim 3, wherein the functional device comprises a decoder.

8. The three-dimensional memory according to any one of claims 1 to 7, wherein one memory cell comprises a stacked Phase Change Memory (PCM) element, a gating element and a plurality of electrodes.

9. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

a plurality of fourth address lines forming a fourth address line layer on the plurality of third phase change memory cells, the plurality of fourth address lines each extending in the second direction; the third phase change memory cell is perpendicular to the third address line and the fourth address line;

10. The method of claim 9, wherein the three-dimensional memory is formed by a three-dimensional memory,

the step of forming each of the plurality of first address lines of the first address line layer includes: forming a first sub-address line, and forming a second sub-address line on the first sub-address line to cover the first sub-address line; the materials of the first sub-address line and the second sub-address line are the same or different; the step of forming each of a plurality of third address lines of the third address line layer includes: forming a fifth sub-address line on the second phase change memory unit, and forming a sixth sub-address line on the fifth sub-address line to cover the fifth sub-address line; the materials of the fifth sub address line and the sixth sub address line are the same or different; the step of forming each fifth address line of the plurality of fifth address lines of the fifth address line layer includes: forming a ninth sub-address line on the fourth phase change memory unit, and forming a tenth sub-address line on the ninth sub-address line to cover the ninth sub-address line; the ninth sub address line and the tenth sub address line are made of the same or different materials;

and/or the presence of a gas in the gas,

the step of forming each of a plurality of second address lines of the second address line layer includes: forming a third sub-address line on the first phase change memory cell, and forming a fourth sub-address line on the third sub-address line to cover the third sub-address line; the materials of the third sub-address line and the fourth sub-address line are the same or different; the step of forming each fourth address line of the plurality of fourth address lines of the fourth address line layer includes: forming a seventh sub-address line on the third phase change memory unit, and forming an eighth sub-address line on the seventh sub-address line to cover the seventh sub-address line; the seventh sub-address line and the eighth sub-address line are made of the same or different materials.