CN112271191A - Three-dimensional memory with four-layer stack - Google Patents
Three-dimensional memory with four-layer stack Download PDFInfo
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
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Abstract
An embodiment of the present invention provides a three-dimensional memory with four layers of stacks, including: at least one memory cell array block; the memory cell array block includes: the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom and are mutually parallel; the bit lines of each bit line layer are parallel to each other, and the projection parts of the bit lines of each bit line layer on the first plane are overlapped; a first word line layer located between the first bit line layer and the second bit line layer; a second wordline layer located between the second bitline layer and the third bitline layer; the word lines of each word line layer are parallel to each other, and the projection of the word lines of each word line layer on the first plane is vertical to the projection of the bit lines of the first bit line layer on the first plane; and four memory cell layers respectively positioned between the two adjacent bit line layers and the word line layer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory with four layers of stacks.
Background
Phase Change Memory (PCM) is a Memory technology that uses chalcogenides as the storage medium, using the difference in resistance of materials in different states to hold data. PCM has the advantages of bit-addressable, no data loss after power-off, high storage density, fast read-write speed, etc., and is considered as the most promising next-generation memory.
In the related art, the mainstream architecture of the three-dimensional phase change memory comprises two stacked memory cells. However, the two-layer stacked Memory cell architecture cannot provide sufficient bit density and cannot compete with the mainstream Dynamic Random Access Memory (DRAM) and NAND type Memory. In order to improve the competitiveness of the three-dimensional phase change memory, it is necessary to increase the bit density of the three-dimensional phase change memory to reduce the bit cost.
Disclosure of Invention
To solve the related art problems, an embodiment of the invention provides a three-dimensional memory with a four-layer stack.
An embodiment of the present invention provides a three-dimensional memory with four layers of stacks, including: at least one memory cell array block; wherein the memory cell array block includes:
the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom; the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other; the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other, and the projections of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are partially overlapped;
a first word line layer located between the first bit line layer and the second bit line layer; a second word line layer located between the second bit line layer and a third bit line layer; the first word line layer and the second word line layer are parallel to each other; the projections of the word lines of the first word line layer and the word lines of the second word line layer on the first plane are both perpendicular to the projections of the bit lines of the first bit line layer on the first plane;
a plurality of first memory cells located between the first bit line layer and the first word line layer; a plurality of second memory cells located between the first word line layer and a second bit line layer; a plurality of third memory cells located between the second bit line layer and the second word line layer; a plurality of fourth memory cells located between the second word line layer and the third bit line layer.
In the above solution, each bit line of the first bit line layer coincides with a projection part of a corresponding bit line of the second bit line layer on the first plane; each bit line of the first bit line layer coincides with a projection of a corresponding bit line of the third bit line layer on the first plane;
each word line of the first word line layer coincides with a projection of a corresponding word line of the second word line layer on the first plane.
In the above scheme, the memory cell array block further includes: a first bit line connection part contacting a bit line of the first bit line layer; a second bit line connection part contacting a bit line of the second bit line layer; a first word line connection part contacting a word line of the first word line layer; a second word line connection part contacting a word line of the second word line layer; wherein the content of the first and second substances,
the first bit line connecting part is connected with a corresponding bit line of the third bit line layer; and the interval between two adjacent bit lines in the third bit line layer is provided with the second bit line connecting part, the first word line connecting part or the second word line connecting part which extends out.
In the above scheme, the memory cell array block further includes: a third bit line connection part contacting a bit line of the third bit line layer;
the projections of the first bit line connecting parts and the corresponding third bit line connecting parts on the first plane are overlapped;
the second bit line connecting parts are arranged in the third bit line layer along the first direction, and extend out of the intervals between two adjacent bit lines;
the first word line connecting part or the second word line connecting part extends out of the third bit line layer and is arranged along the second direction, and the interval between two adjacent bit lines is provided with the first word line connecting part or the second word line connecting part;
wherein the first direction is perpendicular to the second direction.
In the above solution, the three-dimensional memory further includes a bit line decoder; the bit line decoders are disposed on two bit line decoder regions of the memory cell array block; the two bit line decoder regions comprise regions where projections of the second bit line connecting part and the third bit line connecting part on a second plane are respectively located; wherein the bit line decoders are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
In the above scheme, the three-dimensional memory further comprises a word line decoder; the word line decoders are disposed on two word line decoder regions of the memory cell array block; the two word line decoder areas comprise areas where the projections of the first word line connecting part and the second word line connecting part on a second plane are respectively located; wherein the word line decoders are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
In the above scheme, the three-dimensional memory further comprises a bit line driver; the bit line drivers are disposed on two bit line driver regions of the memory cell array block; the two bit line driver regions comprise regions where projections of the second bit line connecting part and the third bit line connecting part are respectively located on a third plane; wherein the bit line drivers are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
In the above scheme, the three-dimensional memory further comprises a word line driver; the word line drivers are disposed on two word line driver regions of the memory cell array block; the two word line driver areas comprise areas where the projections of the first word line connecting part and the second word line connecting part on a third plane are respectively located; wherein the word line drivers are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
In the above scheme, the first bit line connection part contacts with the geometric center of the bit line of the first bit line layer; the second bit line connection part is in contact with the geometric center of a bit line of the second bit line layer;
and/or the presence of a gas in the gas,
the first word line connection is in contact with a geometric center of a word line of the first word line layer; the second word line connection contacts a geometric center of a word line of the second word line layer.
In the above scheme, one memory cell includes a stacked phase change memory PCM element, a selector, and a plurality of electrodes.
An embodiment of the present invention provides a three-dimensional memory with four layers of stacks, including: at least one memory cell array block; wherein the memory cell array block includes: the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom; the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other; the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other, and the projections of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are partially overlapped; a first word line layer located between the first bit line layer and the second bit line layer; a second word line layer located between the second bit line layer and a third bit line layer; the first word line layer and the second word line layer are parallel to each other; the projections of the word lines of the first word line layer and the word lines of the second word line layer on the first plane are both perpendicular to the projections of the bit lines of the first bit line layer on the first plane; a plurality of first memory cells located between the first bit line layer and the first word line layer; a plurality of second memory cells located between the first word line layer and a second bit line layer; a plurality of third memory cells located between the second bit line layer and the second word line layer; a plurality of fourth memory cells located between the second word line layer and the third bit line layer. The three-dimensional memory with the four-layer stacked memory cells provided by the embodiment of the invention greatly improves the bit density of the three-dimensional memory.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional phase-change memory cell array observed by a scanning electron microscope according to an embodiment of the present invention;
FIG. 2a is a partial three-dimensional schematic diagram of a three-dimensional phase-change memory cell array having two stacked layers of memory cells according to an embodiment of the present invention;
FIG. 2b is a partial horizontal schematic diagram of a three-dimensional phase-change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 2c is a partial horizontal schematic diagram of a three-dimensional phase-change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 2d is a partial horizontal schematic diagram of a three-dimensional phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 3a is a partial three-dimensional schematic diagram of a three-dimensional phase-change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 3b is a partial horizontal view of another three-dimensional phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 3c is a partial horizontal view of another three-dimensional phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 3d is a partial horizontal schematic diagram of a three-dimensional phase change memory cell array having four stacked memory cells according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the distribution of word line decoder regions and bit line decoder regions of a three-dimensional phase shifter having four stacked memory cells according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the distribution of word line driver regions and bit line driver regions of a three-dimensional phase shifter having four stacked memory cells according to an embodiment of the present invention.
Description of reference numerals:
201-electrode (in a two-layer memory cell stack architecture); 202-PCM elements (in a two-level cell stack architecture); 203-electrodes (in a two-layer memory cell stack architecture); 204-selector (in two-layer memory cell stack architecture); 205-electrode (in a two-layer memory cell stack architecture); 21-an upper storage unit; 22-a lower memory cell; 23-top bit line; 231-top bit line connections; 24-bottom bit line; 241-bottom bit line connections; 25-word line; 251-word line connection; 301-electrodes (in a four-layer memory cell stack architecture); 302-PCM element (in a four-layer memory cell stack architecture); 303-electrodes (in a four-layer memory cell stack architecture); 304-selector (in a four-level memory cell stack architecture); 305-electrodes (in a four-layer memory cell stack architecture); 31-bit lines of the first bit line layer; 311-first bit line connections; 32-bit lines of the second bit line layer; 321-a second bit line connection; bit lines 33 of the third bit line layer; 331-third bit line connection; 34-word lines of the first word line layer; 341-first word line connection; 35-word lines of the second word line layer; 351-a second word line connection; 36-a first storage unit; 37-a second storage unit; 38-a third storage unit; 39-fourth memory cell.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 1 is a schematic diagram of a three-dimensional phase-change memory cell array observed by a scanning electron microscope. As can be seen from fig. 1, a three-dimensional phase change memory chip is composed of a plurality of small memory cell array blocks having a single bit line, word line, and memory cell. Three-dimensional phase change memories generally include a top bit line, a word line, a bottom bit line, and a memory cell located at the intersection of the bit line and the word line. In practical applications, the word lines, the top bit lines and the bottom bit lines are usually formed by a constant line width (L/S) of 20nm/20nm formed after the patterning process.
To more clearly illustrate the scheme of the embodiment of the present invention, a three-dimensional phase change memory is introduced first, specifically:
the three-dimensional phase change memory comprises a memory cell array and a peripheral circuit; wherein the memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., they are formed on different planes. For example, the memory cell array may be formed over peripheral circuits to reduce the chip size.
In some embodiments, the peripheral circuitry includes any suitable digital, analog, and/or mixed-signal circuitry for facilitating phase change memory operations. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers, and read/write circuits, among others. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated by the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data, and the data interaction is carried out with the outside through the data buffer.
In some embodiments, the memory cell array is used primarily for storing data. In practical applications, the memory cell array includes a plurality of memory cells, each of which may include a stacked PCM element 202, a selector 204, and a plurality of electrodes 201, 203, and 205 (as shown in fig. 2 a). The PCM element 202 may utilize the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on the electro-thermal heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material of the PCM element 202 (or at least part of the current path it blocks) between the two phases to store data. A single bit of data may be stored in each memory cell and a single bit may be written or read by varying the voltage applied to the corresponding selector 204, which eliminates the need for a transistor.
Fig. 2 a-2 d are architecture diagrams illustrating a three-dimensional phase-change memory cell array having two stacked memory cells according to an embodiment of the present invention. FIG. 2a is a three-dimensional view of a portion of the three-dimensional array of phase change memory cells; FIG. 2b is a horizontal view of a portion of the three-dimensional array of phase change memory cells viewed along the Y direction; FIG. 2c is a horizontal view of a portion of the three-dimensional array of phase change memory cells viewed along the X direction; FIG. 2d is a horizontal view of a portion of the three-dimensional array of phase change memory cells as viewed along the Z-direction.
It is understood that the three-dimensional phase-change memory cell array is placed in front, the Z direction is understood as a top view direction (a direction viewed from the top bit line to the bottom bit line), the Y direction is understood as a left view direction (a direction in which the bit lines extend), the X direction is understood as a front view direction (a direction in which the word lines extend), and the partial isometric view of the three-dimensional phase-change memory cell array shown in fig. 2a is an isometric view viewed from the left view direction.
With reference to fig. 2 a-2 d, the memory cell array comprises: a plurality of top bit lines 23 in parallel and a plurality of bottom bit lines 24 in parallel; there is an offset between the top bit line 23 and the corresponding bottom bit line 24 (one bottom bit line below the top bit line) (where the offset refers to the offset in the Y direction shown with reference to fig. 2a, there may be no offset or a small offset in the X direction for the top bit line 23 and the corresponding bottom bit line 24); a top bit line connection portion 231 (here, the english language of the connection portion may be expressed as Contact, and the connection portion may also be referred to as a Contact) contacting the top bit line 23 and extending from between two adjacent bottom bit lines 24 for connecting the top bit line 23 and the related device; a bottom bit line connection portion 241 contacting the bottom bit line 24 for enabling connection of the bottom bit line 24 with an associated device; a plurality of word lines 25 between the top bit lines 23 and the bottom bit lines 24; a plurality of word lines 25 are in the same plane and parallel to the top bit lines 23 and the bottom bit lines 24; a word line connection portion 251 in contact with the word line 25 for enabling connection of the word line 25 with an associated device; upper memory cells between the top bit lines 22 and the word lines 25 and connected to the corresponding top bit lines 22 and the word lines 25, the plurality of upper memory cells forming a top memory cell layer; a lower memory cell between the word line 25 and the bottom word line 24, the plurality of lower memory cells forming a bottom memory cell layer.
It will be appreciated that based on the features of the partial architecture shown in fig. 2 a-2 d, extending the partial structure in the X and Y directions, respectively, may result in a memory cell array. That is, two-layer stacked memory cells can be implemented in the architecture of the memory cell array.
An embodiment of the present invention further provides a three-dimensional memory having a four-layer stack, where the three-dimensional memory having the four-layer stack includes: at least one memory cell array block; wherein the memory cell array block includes:
the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom; the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other; the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other, and the projections of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are partially overlapped;
a first word line layer located between the first bit line layer and the second bit line layer; a second word line layer located between the second bit line layer and a third bit line layer; the first word line layer and the second word line layer are parallel to each other; the projections of the word lines of the first word line layer and the word lines of the second word line layer on the first plane are both perpendicular to the projections of the bit lines of the first bit line layer on the first plane;
a plurality of first memory cells located between the first bit line layer and the first word line layer; a plurality of second memory cells located between the first word line layer and a second bit line layer; a plurality of third memory cells located between the second bit line layer and the second word line layer; a plurality of fourth memory cells located between the second word line layer and the third bit line layer.
Here, the three-dimensional memory having the four-layer stack may include a three-dimensional phase change memory having memory cells stacked in four layers, but is not limited to the three-dimensional phase change memory having memory cells stacked in four layers, and the three-dimensional phase change memory having memory cells stacked in four layers is described as an example below.
The memory cell array block of the three-dimensional phase change memory with four layers of stacked memory cells comprises three bit line layers, two word line layers and four memory cell layers; the bit line layer can be understood as a structure formed by a plurality of bit lines located on the same plane; the word line layer can be understood as a structure formed by a plurality of word lines located on the same plane; the memory cell layer can be understood as a structure formed by a plurality of memory cells located on the same plane.
The three bit line layers are sequentially arranged from top to bottom and are parallel to each other. Meanwhile, the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are all parallel, and the projection parts of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are overlapped. Here, the first plane is flat with the plane of the first bit line layer, that is, the projections of the bit lines of each bit line layer on the same plane are partially overlapped.
The two word line layers are respectively positioned between two adjacent bit line layers and are parallel to each other. Meanwhile, the word lines of the first word line layer and the word lines of the second word line layer are perpendicular to the projections of the bit lines of the first bit line layer on the first plane. That is, the word lines of the first word line layer are perpendicular to both the bit lines of the first bit line layer and the bit lines of the second bit line layer; the word lines of the second word line layer are perpendicular to the bit lines of the second bit line layer and the bit lines of the third bit line layer. In some embodiments, the word lines of each word line layer are equidistant from the plane in which the two bit line layers adjacent to the word line layer lie.
The four memory cell layers are respectively positioned between two adjacent bit line layers and word line layers. The first memory cell layer comprises a plurality of first memory cells, and the plurality of first memory cells are positioned between bit lines of the first bit line layer and word lines of the first word line layer and are connected with the bit lines of the corresponding first bit line layer and the word lines of the first word line layer; the second memory cell layer comprises a plurality of second memory cells, and the plurality of second memory cells are positioned between the word lines of the first word line layer and the bit lines of the second bit line layer and are connected with the corresponding word lines of the first word line layer and the corresponding bit lines of the second bit line layer; the third memory cell layer comprises a plurality of third memory cells, and the third memory cells are positioned between the bit lines of the third bit line layer and the word lines of the second word line layer and are connected with the bit lines of the corresponding third bit line layer and the word lines of the second word line layer; the fourth memory cell layer comprises a plurality of fourth memory cells, and the plurality of fourth memory cells are positioned between the word lines of the second word line layer and the bit lines of the third bit line layer and are connected with the corresponding word lines of the second word line layer and the corresponding bit lines of the third bit line layer. In some embodiments, the memory cells of each memory cell layer are perpendicular to the bit line layer and the word line layer, respectively, adjacent to the memory cell layer.
When the three-dimensional memory having the four-layer stack is a three-dimensional phase change memory having memory cells of the four-layer stack, one memory cell includes a stacked phase change memory PCM element, a selector, and a plurality of electrodes. In some embodiments, the material of the PCM element comprises a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or comprises any other suitable phase change material; the selector material may include any suitable OTS material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, and the like; the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.
Fig. 3a to 3d are architecture diagrams illustrating a three-dimensional phase-change memory cell array having four stacked memory cells according to an embodiment of the present invention. FIG. 3a is a three-dimensional view of a portion of the three-dimensional array of phase change memory cells; FIG. 3b is a two-dimensional view of a portion of the three-dimensional array of phase change memory cells viewed along the Y direction; FIG. 3c is a two-dimensional view of a portion of the three-dimensional array of phase change memory cells viewed along the X direction; FIG. 3d is a two-dimensional view of a portion of the three-dimensional array of phase change memory cells as viewed along the Z-direction.
It should be noted that, here, the memory cell array block is a minimum unit in a memory cell array of the three-dimensional memory, and the memory cell array is arranged to extend along the first direction and the second direction respectively based on the minimum unit to form the memory cell array of the three-dimensional memory.
It is understood that the three-dimensional phase change memory cell array is placed in front, the Z direction is understood as a top view direction (a direction viewed from the top bit line to the bottom bit line), the Y direction is understood as a left view direction (a direction in which the bit lines extend), the X direction is understood as a front view direction (a direction in which the word lines extend), and the partial isometric view of the three-dimensional phase change memory cell array shown in fig. 3a is an isometric view viewed from the left view direction.
It should be noted that fig. 3 a-3 d are only used to provide an illustration of a three-dimensional memory with a four-layer stack, and are not used to limit the scheme of the three-dimensional memory provided by the present invention. For example, in practical applications, the number of memory cells connected to each bit line is not limited to the 6 shown in fig. 3a to 3d, and may be adjusted according to practical situations, and accordingly, the number of bit lines and word lines in each memory cell array block is not limited to the number shown in fig. 3a to 3 d.
The three-dimensional memory of four-layer stacked memory cells provided by the embodiment of the invention is described in detail below with reference to fig. 3a to 3 d.
In some embodiments, each bit line of the first bit line layer coincides with a projected portion of a corresponding bit line of the second bit line layer on the first plane; each bit line of the first bit line layer coincides with a projection of a corresponding bit line of the third bit line layer on the first plane;
each word line of the first word line layer coincides with a projection of a corresponding word line of the second word line layer on the first plane.
Here, at least one bit line is included in the first bit line layer, the bit line 31 of the first bit line layer may also be referred to as a top bit line, and the bit line 31 of the first bit line layer extends in the Y direction; when the first bit line layer includes a plurality of bit lines, the bit lines 31 of the plurality of first bit line layers have the same length and are aligned in parallel along the X direction. In some embodiments, the bit lines 31 of the first bit line layers are aligned in a column in parallel along the X-direction (as shown in fig. 3 d). The second bit line layer includes at least one bit line, the bit line 32 of the second bit line layer may also be referred to as a middle bit line, and the bit line 32 of the second bit line layer extends along the Y direction; when the second bit line layer includes a plurality of bit lines, the bit lines 32 of the plurality of second bit line layers have the same length and are aligned in parallel along the X direction. In some embodiments, the bit lines 32 of the second bit line layers are aligned in a column in parallel along the X direction (as shown in FIG. 3 d). The third bit line layer includes at least one bit line, the bit line 33 of the third bit line layer may also be referred to as a bottom bit line, and the bit line 33 of the third bit line layer extends along the Y direction; when the third bit line layer includes a plurality of bit lines, the bit lines 33 of the plurality of third bit line layers have the same length and are aligned in parallel in the X direction. In some embodiments, the bit lines 33 of the third bit line layer are aligned in a column in parallel along the X direction (as shown in FIG. 3 d). The length of each bit line of the first bit line layer, the length of each bit line of the second bit line layer, and the length of each bit line of the third bit line layer may all be equal.
Here, the first plane may include a plane parallel to a plane formed by X, Y. Each bit line of the first bit line layer coincides with a projection of a corresponding bit line of the second bit line layer on the first plane, which may be understood as that the bit line 31 of each first bit line layer is offset from the projection of the bit line 32 of the corresponding second bit line layer on the first plane and along the Y direction, and the offset may be about half the length of the bit line 31 of the first bit line layer shown in fig. 3b, or other amounts. The projection of each bit line of the first bit line layer and the corresponding bit line of the third bit line layer on the first plane may be understood as that the bit line 31 of each first bit line layer coincides with the projection of the bit line 31 of the corresponding third bit line layer on the first plane and along the Y direction.
In practical applications, the bit lines 31 of the first bit line layer, the bit lines 32 of the second bit line layer, and the bit lines 33 of the third bit line layer may overlap in the first plane and have projections in the X direction, or may have a small amount of offset, and in fig. 3d, for the sake of easy observation, the bit lines 31 of the first bit line layer and the bit lines 33 of the third bit line layer are slightly offset in the X direction.
Here, the first word line layer includes a plurality of word lines, a plurality of word lines 34 of the first word line layer, the plurality of word lines 34 of the first word line layer extending in the X direction and arranged in a plurality of rows in the Y direction (the number of rows is related to the number of memory cells). The second word line layer includes a plurality of word lines, a plurality of word lines 35 of the second word line layer, and the plurality of word lines 35 of the second word line layer extend in the X direction and are arranged in a plurality of rows in the Y direction (the number of rows is related to the number of memory cells). Each word line of the first word line layer has the same length, each word line of the second word line layer has the same length, and each word line of the first word line layer has the same length as each word line of the second word line layer.
It is understood that the length of each word line (word line 34 of the first word line layer or word line 35 of the second word line layer) may be the same as or different from each bit line (bit line 31 of the first bit line layer, bit line 32 of the second bit line layer or bit line 33 of the third bit line layer), as shown in fig. 3d, and in some embodiments, the length of each word line may be twice the length of each bit line.
Each word line of the first word line layer coincides with a projection of a corresponding word line of the second word line layer on the first plane, which may be understood as that a bit line 34 of each first word line layer is offset from a projection of a corresponding bit line 35 of the second word line layer on the first plane and along the X direction, where the offset may be about half the length of the bit line 34 of the first word line layer shown in fig. 3c, or other amounts.
In practical applications, the projections of the word lines 34 of the first word line layer and the word lines 35 of the second word line layer on the first plane and along the Y direction may overlap, or there may be a small amount of offset, and in fig. 3d, for the sake of convenience of viewing, the word lines 34 of the first word line layer are slightly offset in the Y direction with respect to the word lines 35 of the second word line layer.
Here, four memory cell layers each including a plurality of memory cells are included between adjacent bit line layers and word line layers. In some embodiments, as in fig. 3a, one memory cell comprises a stacked phase change memory PCM element 302, a selector 304 and a plurality of electrodes 301, 303 and 305. In some embodiments, three electrodes 301, 303, and 305 are disposed below the selector 304, between the selector 304 and the PCM element 302, and above the PCM element 302, respectively. It should be understood that in some other embodiments, the relative positions of the selector 304 and the PCM element 302 may be interchanged. It should be understood that the structure, configuration, and materials of the memory cell are not limited to the example in fig. 3a, and may include any suitable structure, configuration, and materials.
It should be noted that, one bit line of the bit line layer may connect a plurality of memory cells, the number of connected memory cells may be adjusted according to practical situations, is not limited to the 6 illustrated in fig. 3a, and the memory cells may be accessed by selectively activating the word lines and bit lines corresponding to the respective memory cells regardless of the number of the memory cells.
In some embodiments, the memory cell array block further includes: a first bit line connection part 311 contacting the bit line 31 of the first bit line layer; a second bit line connection part 321 contacting the bit line 32 of the second bit line layer; a first word line connection 341 in contact with a word line 34 of the first word line layer; a second word line connection portion 351 contacting a word line 35 of the second word line layer; wherein the content of the first and second substances,
the first bit line connection part 311 is connected with a corresponding bit line of the third bit line layer; the second bit line connection portion 321, the first word line connection portion 341, or the second word line connection portion 351 extending from the third bit line layer is disposed in the space between two adjacent bit lines.
Here, the memory cell array block in the three-dimensional memory further includes bit lines and corresponding connection portions of the word lines, and the corresponding connection portions are used to connect the word lines or the bit lines connected to the connection portions with associated devices (e.g., decoders, drivers, etc.). The corresponding connecting parts extend towards the third direction; the third direction includes a direction (Z-direction) in which the top bit lines point to the respective bottom bit lines.
Here, the connection of the first bit line connection portion 311 with the bit line 33 of the corresponding third bit line layer may be understood as that the bit line 31 of each first bit line layer in one memory cell array block is connected with the bit line 33 of one third bit line layer directly below the bit line through the first bit line connection portion 311, that is, the bit line 31 of two corresponding first bit line layers of different layers and the bit line 33 of the third bit line layer are controlled together. The second bit line connection portion 321, the first word line connection portion 341, or the second word line connection portion 351 extending from the space between two adjacent bit lines in the third bit line layer may be understood as each second bit line connection portion 321, each first word line connection portion 341, or each second word line connection portion 351 in one memory cell array block extends from the space between the bit lines 34 of two different adjacent third bit line layers (as shown in fig. 3 d).
Wherein, in some embodiments, the memory cell array block further comprises: a third bit line connection part 331 contacting a bit line of the third bit line layer;
the first bit line connections 311 coincide with respective projections of the third bit line connections 331 on the first plane;
the second bit line connecting parts 321 are arranged in the third bit line layer along the first direction, and extend out of the space between two adjacent bit lines;
the first word line connecting part 341 or the second word line connecting part 351 is arranged in the third bit line layer along the second direction and is extended out of the interval between two adjacent bit lines;
wherein the first direction is perpendicular to the second direction.
In practical applications, the first direction may include the aforementioned X direction; the second direction may include the aforementioned Y direction. Each of the second bit line connecting portions 321 extends downward from the space between the word lines 33 of the two adjacent third word line layers arranged in the Y direction. It should be noted that the bit lines 33 of the two adjacent third bit line layers are located in different memory cell array blocks.
In practical applications, each of the first word line connection portions 341 extends downward from the space between two adjacent bit lines 32 of the second bit line layer, two adjacent word lines 35 of the second word line layer, and two adjacent bit lines 33 of the third bit line layer, which are arranged in the X direction; each of the second word line connecting portions 351 extends downward from the space between the bit lines 33 of two adjacent third bit line layers arranged in the X direction in sequence. Meanwhile, the first bit line connection portion 311 coincides with a projection of the third bit line connection portion 331 corresponding to the bit line 33 of the third bit line layer located right below the bit line on the first plane. It is noted that each first word line connection portion 341 and each second word line connection portion 351 in a memory cell array block extend downward from the spacing of the bit lines 33 of two different adjacent third bit line layers in the memory cell array block (as shown in fig. 3 d).
It should be noted that, the connection portions of adjacent word lines or the connection portions of adjacent bit lines in the same layer may be aligned (the connection lines are straight lines) or staggered (the connection lines are zigzag) like that shown in fig. 3 d. It will be appreciated that the staggered arrangement may reduce the size consumption in the respective directions.
In practice, each first bit line connector 311 contacts the bit line 31 of the corresponding first bit line layer at a first position of the bit line 31 of the corresponding first bit line layer, and each second bit line connector 321 contacts the bit line 32 of the corresponding second bit line layer at a second position of the bit line 32 of the corresponding second bit line layer. The first and second locations herein are not limited to being at the geometric centers of the bit lines 31 of the first bit line layer and the bit lines 32 of the second bit line layer as shown in fig. 3 a-3 d. The distance between the first position on the bit line 31 of the first bit line layer and the second position on the bit line 32 of the corresponding second bit line layer along the X direction is equal to the offset between the bit line 31 of the first bit line layer and the bit line 32 of the corresponding second bit line layer along the X direction, and the distance between the first position and the third position along the X direction is 0, that is, the projection of the first position on the bit line 31 of the first bit line layer and the projection of the third position on the bit line 33 of the corresponding third bit line layer on the first plane may overlap.
In practice, each first word line connection 341 contacts the word line 34 of the corresponding first word line layer at a third location of the bit line 34 of the corresponding first word line layer, and each second word line connection 351 contacts the word line 35 of the corresponding second word line layer at a fourth location of the word line 35 of the corresponding second word line layer. The third and fourth locations herein are not limited to being at the geometric centers of word lines 34 of the first word line layer and word lines 35 of the second word line layer as shown in fig. 3 a-3 d. The distance in the X direction between the third location on sub-line 34 of the first word line layer and the fourth location on word line 35 of the corresponding second word line layer is equal to the offset (D) in the X direction between word line 35 of the first word line layer and word line 35 of the corresponding second word line layer.
It is to be understood that when the first location is at the geometric center of the bit line 31 of the first bit line layer and the second location is the bit line 32 of the second bit line layer; and/or when the third location is at the geometric center of word line 34 of the first word line layer and the fourth location is at the geometric center of word line 35 of the second word line layer, the overall architecture is more uniformly symmetric, interconnect routing difficulties, and bit line parasitic series resistance are less.
Based on this, in some embodiments, the first bit line connection portion 311 contacts at the geometric center of the bit line 31 of the first bit line layer; the second bit line connection 321 contacts the second bit line layer at the geometric center of the bit line 32;
and/or the presence of a gas in the gas,
the first word line connection 341 is in contact with a geometric center of a word line 34 of the first word line layer; the second word line connection 351 is in contact with the geometric center of the word line 35 of the second word line layer.
In practical applications, since the bit line 33 of the third bit line layer is the bottommost bit line layer to be extracted, and there is no other shielding layer below (in the direction extending along the third direction) the bit line 33 of the third bit line layer, the position of each third bit line connection portion 331 on the bit line 33 of the corresponding third bit line layer may not be limited. However, it can be appreciated that when the set position of the third bit line connection 331 on the bit line 33 of the corresponding third bit line layer is at the geometric center of the bit line 33 of the third bit line layer, the overall architecture is more uniformly symmetric, the interconnect routing difficulty is less, and the bit line parasitic series resistance is less.
As mentioned above, in practical applications, the phase change memory further includes a peripheral circuit portion, and based on the change of the architecture of the memory cell array portion, the architectures of the decoder and the driver in the peripheral circuit portion are changed. Specifically, the method comprises the following steps:
in some embodiments, the three-dimensional memory further comprises a bit line decoder; the bit line decoders are disposed on two bit line decoder regions of the memory cell array block; the two bit line decoder regions include regions where the projections of the second bit line connection portion 321 and the third bit line connection portion 331 on the second plane are located, respectively; wherein the bit line decoders are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
In some embodiments, the three-dimensional memory further comprises a word line decoder; the word line decoders are disposed on two word line decoder regions of the memory cell array block; the two word line decoder regions include regions where projections of the first word line connection portion 341 and the second word line connection portion 351 on a second plane are located, respectively; wherein the word line decoders are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
In the embodiment of the invention, the memory cell array and the peripheral circuit form a stacked structure, namely, the memory cell array and the peripheral circuit are formed on different planes. For example, the memory cell array may be formed over peripheral circuits.
In practical applications, the second plane may be the same plane as the first plane or a different plane from the first plane, and the second plane may be a plane parallel to the three bit line layers below the memory cell array. The bit line decoders are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections, and are capable of selectively activating the corresponding bit lines. In the memory cell array architecture, the first bit line connection portion 311 extends toward the bit line 33 of the corresponding third bit line layer and drops on the bit line 33 of the corresponding third bit line layer to connect the two bit lines, and based on this, the decoder controls the bit line 31 of the corresponding first bit line layer simultaneously when the bit line 33 of the third bit line layer is selectively activated. In this way, the bit line connections in each memory cell array block can be concentrated in two regular areas, i.e. only two bit line decoder areas are required in each memory cell array block. It is understood that the area where the projection of the second bit line connection 321 on the second plane is located is the first bit line decoder area, and the area where the projection of the third bit line connection 331 on the second plane is the second bit line decoder area (the first bit line decoder area and the second bit line decoder area are shown in fig. 3 d).
The word line decoders are respectively connected to all word lines in the memory cell array block through corresponding word line connection portions, and are capable of selectively activating the corresponding word lines. In the aforementioned memory cell array architecture, each of the first word line connections 341 contacts the word line 34 of the corresponding first word line layer at a third position of the bit line 34 of the corresponding first word line layer, and each of the second word line connections 351 contacts the word line 35 of the corresponding second word line layer at a fourth position of the word line 35 of the corresponding second word line layer. Since the connection portions of the word lines of the word line layers in each memory cell array block can be concentrated in one regular area, two word line decoder areas are required in each memory cell array block. It is understood that the area where the projection of the first word line connection portion 341 on the second plane is located is a first word line decoder area; the area where the projection of the second word line connecting portion 351 on the second plane is located is a second word line decoder area (the first word line decoder area and the second word line decoder area are shown in fig. 3 d).
In some embodiments, the specific distribution of the two word line decoder regions and the two bit line decoder regions can refer to fig. 4.
In some embodiments, the three-dimensional memory further comprises a bit line driver; the bit line drivers are disposed on two bit line driver regions of the memory cell array block; the two bit line driver regions include regions where the projections of the second bit line connection portion 321 and the third bit line connection portion 331 are located on a third plane, respectively; wherein the bit line drivers are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
In some embodiments, the three-dimensional memory further comprises a word line driver; the word line drivers are disposed on two word line driver regions of the memory cell array block; the two word line driver regions include regions where projections of the first word line connection portion 341 and the second word line connection portion 351 on a third plane are located, respectively; wherein the word line drivers are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
In practical applications, the third plane may be the same plane as the first plane or a different plane from the first plane, and the third plane may be a plane parallel to the three bit line layers and located below the memory cell array. The bit line drivers are respectively connected to all bit lines in the memory cell array block through corresponding bit line connection parts, and are capable of applying preset voltages to the corresponding bit lines (here, the preset voltages are voltage values that set different requirements for word lines and bit lines in different states). In the memory cell array architecture, the first bit line connecting portion 311 extends toward the bit line 33 of the corresponding third bit line layer and drops on the bit line 33 of the corresponding third bit line layer to connect the two bit lines, and based on this, the driver applies a preset voltage to the bit line 33 of the third bit line layer and also applies a preset voltage to the bit line 31 of the corresponding first bit line layer. In this way, the bit line connections in each memory cell array block may be concentrated in two regular areas, i.e. only two bit line driver areas are required in each memory cell array block. It is understood that the area where the projection of the second bit line connection 321 on the third plane is located is the first bit line driver area, and the area where the projection of the third bit line connection 331 on the third plane is located is the second bit line driver area (the first bit line driver area and the second bit line driver area are shown in fig. 3 d).
The word line drivers are respectively connected to all word lines in the memory cell array block through corresponding word line connection portions, and are capable of applying preset voltages to the corresponding word lines (here, the preset voltages are voltage values that set different requirements for word lines and bit lines in different states). In the aforementioned memory cell array architecture, each of the first word line connections 341 contacts the word line 34 of the corresponding first word line layer at a third position of the bit line 34 of the corresponding first word line layer, and each of the second word line connections 351 contacts the word line 35 of the corresponding second word line layer at a fourth position of the word line 35 of the corresponding second word line layer. Since the connection portions of the word lines of the respective word line layers in each memory cell array block can be concentrated in one regular area, two word line driver areas are required in each memory cell array block. It can be understood that the area where the projection of the first word line connection portion 341 on the third plane is located is the first word line driver area; the area of the projection of the second word line connection portion 351 on the third plane is a second word line driver area (the first word line driver area and the second word line driver area are shown in fig. 3 d).
In some embodiments, the specific distribution of the two word line driver regions and the two bit line driver regions can be referred to in fig. 5.
As can be seen from the above description, the projection in the Z direction of the decoder area and the driver area of the peripheral circuit may coincide.
The three-dimensional memory with four-layer stacking provided by the embodiment of the invention comprises at least one memory cell array block; wherein the memory cell array block includes: the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom; the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other; the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other, and the projections of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are partially overlapped; a first word line layer located between the first bit line layer and the second bit line layer; a second word line layer located between the second bit line layer and a third bit line layer; the first word line layer and the second word line layer are parallel to each other; the projections of the word lines of the first word line layer and the word lines of the second word line layer on the first plane are both perpendicular to the projections of the bit lines of the first bit line layer on the first plane; a plurality of first memory cells located between the first bit line layer and the first word line layer; a plurality of second memory cells located between the first word line layer and a second bit line layer; a plurality of third memory cells located between the second bit line layer and the second word line layer; a plurality of fourth memory cells located between the second word line layer and the third bit line layer. The three-dimensional memory with the four-layer stacked memory cells provided by the embodiment of the invention greatly improves the bit density of the three-dimensional memory.
Based on the three-dimensional memory with four-layer stack, an embodiment of the present invention further provides a method for controlling a three-dimensional memory with four-layer stack, including:
when determining that the first word line and the bit line of the first bit line layer are activated, taking the first memory cell as a selected memory cell;
when determining that the bit lines of the first word line and the second bit line layer are activated, taking the second memory cell as a selected memory cell;
when determining that the bit lines of the second word line and the second bit line layer are activated, taking the third memory cell as a selected memory cell;
when determining that the bit lines of the second word line and the third bit line layer are activated, taking the fourth memory cell as a selected memory cell;
when determining that the bit lines of the third word line and the third bit line layer are activated, taking the fifth memory cell as the selected memory cell;
when determining that the bit lines of the third word line layer and the fourth bit line layer are activated, taking the fourth memory cell as a selected memory cell;
the three-dimensional memory with the four-layer stack comprises the three-dimensional memory with the four-layer stack provided by the embodiment of the invention.
In practical application, the intersection of the word line and the bit line is the selected memory cell, each memory cell is uniquely selected according to the method, and then read and write operations are carried out on the memory cells, namely, the word line and the bit line contacted by the memory are selected, so that the memory can be selected.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A three-dimensional memory having a four-layer stack, comprising: at least one memory cell array block; wherein the memory cell array block includes:
the first bit line layer, the second bit line layer and the third bit line layer are sequentially arranged from top to bottom; the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other; the bit lines of the first bit line layer, the second bit line layer and the third bit line layer are parallel to each other, and the projections of the bit lines of the first bit line layer, the second bit line layer and the third bit line layer on the first plane are partially overlapped;
a first word line layer located between the first bit line layer and the second bit line layer; a second word line layer located between the second bit line layer and a third bit line layer; the first word line layer and the second word line layer are parallel to each other; the projections of the word lines of the first word line layer and the word lines of the second word line layer on the first plane are both perpendicular to the projections of the bit lines of the first bit line layer on the first plane;
a plurality of first memory cells located between the first bit line layer and the first word line layer; a plurality of second memory cells located between the first word line layer and a second bit line layer; a plurality of third memory cells located between the second bit line layer and the second word line layer; a plurality of fourth memory cells located between the second word line layer and the third bit line layer.
2. The three-dimensional memory according to claim 1,
each bit line of the first bit line layer is overlapped with a projection part of a corresponding bit line of the second bit line layer on the first plane; each bit line of the first bit line layer coincides with a projection of a corresponding bit line of the third bit line layer on the first plane;
each word line of the first word line layer coincides with a projection of a corresponding word line of the second word line layer on the first plane.
3. The three-dimensional memory according to claim 2, wherein the memory cell array block further comprises: a first bit line connection part contacting a bit line of the first bit line layer; a second bit line connection part contacting a bit line of the second bit line layer; a first word line connection part contacting a word line of the first word line layer; a second word line connection part contacting a word line of the second word line layer; wherein the content of the first and second substances,
the first bit line connecting part is connected with a corresponding bit line of the third bit line layer; and the interval between two adjacent bit lines in the third bit line layer is provided with the second bit line connecting part, the first word line connecting part or the second word line connecting part which extends out.
4. The three-dimensional memory according to claim 3, wherein the memory cell array block further comprises: a third bit line connection part contacting a bit line of the third bit line layer;
the projections of the first bit line connecting parts and the corresponding third bit line connecting parts on the first plane are overlapped;
the second bit line connecting parts are arranged in the third bit line layer along the first direction, and extend out of the intervals between two adjacent bit lines;
the first word line connecting part or the second word line connecting part extends out of the third bit line layer and is arranged along the second direction, and the interval between two adjacent bit lines is provided with the first word line connecting part or the second word line connecting part;
wherein the first direction is perpendicular to the second direction.
5. The three-dimensional memory according to claim 4, further comprising a bit line decoder; the bit line decoders are disposed on two bit line decoder regions of the memory cell array block; the two bit line decoder regions comprise regions where projections of the second bit line connecting part and the third bit line connecting part on a second plane are respectively located; wherein the bit line decoders are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
6. The three-dimensional memory according to claim 4, further comprising a word line decoder; the word line decoders are disposed on two word line decoder regions of the memory cell array block; the two word line decoder areas comprise areas where the projections of the first word line connecting part and the second word line connecting part on a second plane are respectively located; wherein the word line decoders are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
7. The three-dimensional memory according to claim 4, further comprising a bit line driver; the bit line drivers are disposed on two bit line driver regions of the memory cell array block; the two bit line driver regions comprise regions where projections of the second bit line connecting part and the third bit line connecting part are respectively located on a third plane; wherein the bit line drivers are respectively connected to all bit lines in the memory cell array block through corresponding bit line connections.
8. The three-dimensional memory according to claim 4, further comprising a word line driver; the word line drivers are disposed on two word line driver regions of the memory cell array block; the two word line driver areas comprise areas where the projections of the first word line connecting part and the second word line connecting part on a third plane are respectively located; wherein the word line drivers are respectively connected to all word lines in the memory cell array block through corresponding word line connection parts.
9. The three-dimensional memory according to claim 3, wherein the first bit line connection part is in contact with a geometric center of a bit line of the first bit line layer; the second bit line connection part is in contact with the geometric center of a bit line of the second bit line layer;
and/or the presence of a gas in the gas,
the first word line connection is in contact with a geometric center of a word line of the first word line layer; the second word line connection contacts a geometric center of a word line of the second word line layer.
10. The three-dimensional memory according to any one of claims 1 to 9, wherein one memory cell comprises a stacked Phase Change Memory (PCM) element, a selector, and a plurality of electrodes.
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| US20040190360A1 (en) * | 2003-03-31 | 2004-09-30 | Scheuerlein Roy E. | Word line arrangement having multi-layer word line segments for three-dimensional memory array |
| KR20050110706A (en) * | 2005-09-30 | 2005-11-23 | 가부시끼가이샤 도시바 | Phase change memory device |
| CN109768158A (en) * | 2017-11-09 | 2019-05-17 | 三星电子株式会社 | Memory device with cross-point memory array |
| CN110914907A (en) * | 2019-10-14 | 2020-03-24 | 长江存储科技有限责任公司 | Three-dimensional phase change memory device |
| CN111758171A (en) * | 2020-05-12 | 2020-10-09 | 长江先进存储产业创新中心有限责任公司 | Novel distributed array and contact architecture for 4-stack 3D PCM memories |
| CN112119462A (en) * | 2020-08-19 | 2020-12-22 | 长江先进存储产业创新中心有限责任公司 | Programming and read biasing schemes for distributed arrays and CMOS architectures for 2-stack 3D PCM memories |
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| WO2023272556A1 (en) * | 2021-06-30 | 2023-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
| US11935596B2 (en) | 2021-06-30 | 2024-03-19 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices having polysilicon layer and bonded semiconductor structures and methods for forming the same |
| WO2024098366A1 (en) * | 2022-11-11 | 2024-05-16 | Yangtze Advanced Memory Industrial Innovation Center Co., Ltd | A multi-stack three-dimensional phase-change memory and methods for making the same |
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