CN113284947A - Semiconductor transistor epitaxial structure, preparation method thereof and semiconductor transistor - Google Patents

Semiconductor transistor epitaxial structure, preparation method thereof and semiconductor transistor Download PDF

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CN113284947A
CN113284947A CN202110529996.5A CN202110529996A CN113284947A CN 113284947 A CN113284947 A CN 113284947A CN 202110529996 A CN202110529996 A CN 202110529996A CN 113284947 A CN113284947 A CN 113284947A
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barrier layer
layer
semiconductor transistor
epitaxial structure
composition
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CN113284947B (en
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李东昇
贾利芳
肖金平
逯永建
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Azure Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention provides a semiconductor transistor epitaxial structure, a preparation method thereof and a semiconductor transistor, wherein the semiconductor transistor epitaxial structure sequentially comprises the following components from bottom to top: the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer. The epitaxial structure of the semiconductor transistor provided by the invention contains the composite barrier layer, so that the quantum limit of channel two-dimensional electron gas can be enhanced and the electron tunneling probability can be reduced while the crystal quality is ensured, thereby more effectively relieving current collapse and gate leakage current and improving the performance of a transistor device.

Description

Semiconductor transistor epitaxial structure, preparation method thereof and semiconductor transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor transistor epitaxial structure, a preparation method thereof and a semiconductor transistor.
Background
A HEMT (High Electron Mobility Transistor) device has the advantages of High breakdown characteristic, High switching speed, small on-resistance and the like, and thus has a wide application prospect in the fields of power management, wind power generation, solar cells, electric vehicles, radio frequency and the like.
The epitaxial structure of a conventional HEMT device typically includes a substrate and a nucleation layer, a buffer layer, a channel layer, a barrier layer, a P-type layer, and the like, sequentially formed on the substrate. With further deepening of practice and application, the traditional HEMT device is exposed to quality problems such as current collapse, grid leakage current and the like, and the problems seriously restrict the further development and application of the HEMT device. Wherein the current collapse is directly related to the limiting effect of the barrier layer, the crystal quality, the defect state and the like; the gate leakage current is also closely related to the confinement effect of the barrier layer, the crystal quality, the defect state, and the like.
Usually, an AlN insert layer is added between the channel layer and the barrier layer, so that the band gap difference of the heterojunction can be obviously improved, the electron tunneling probability is favorably reduced, the quantum limit of two-dimensional electron gas of the channel is enhanced, and the current collapse and the grid leakage current are relieved to a certain extent. But because the usable growth temperature of the AlN insert layer is lower and the lattice mismatch between the AlN insert layer and the GaN channel layer causes the AlN insert layer to grow about 2 nanometers, and a large amount of defects and dislocations appear when the AlN insert layer is thicker. Therefore, the AlN insertion layer has a limited thickness, and the effect cannot be fully exerted, resulting in a limited improvement effect.
Disclosure of Invention
The invention aims to provide a semiconductor transistor epitaxial structure, a preparation method thereof and a semiconductor transistor, which are used for improving the crystal quality, strengthening the quantum limit of channel two-dimensional electron gas and reducing the electron tunneling probability, so that the current collapse and the grid leakage current are effectively relieved, and the device performance is improved.
In order to achieve the above and other related objects, the present invention provides an epitaxial structure of a semiconductor transistor, the epitaxial structure sequentially including, from bottom to top: the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer.
Optionally, in the epitaxial structure of the semiconductor transistor, the first barrier layer is a high Al composition structure layer, and the second barrier layer has a gradually changing Al composition and includes at least one low Al composition structure layer.
Optionally, in the semiconductor transistor epitaxial structure, the second barrier layer further includes a plurality of high Al component structure layers, and the two-dimensional electron gas concentration is adjusted by setting the low Al component structure layer and the high Al component structure layer in the second barrier layer.
Optionally, in the epitaxial structure of the semiconductor transistor, the Al composition of the second barrier layer is gradually changed in a step-change manner, a linear-change manner, or a combination of the step-change manner and the linear-change manner.
Optionally, in the epitaxial structure of the semiconductor transistor, the thickness of the composite barrier layer is 5nm to 30 nm.
Optionally, in the epitaxial structure of the semiconductor transistor, the thickness of the first barrier layer is 0.5nm to 5nm, and the thickness of the second barrier layer is 4.5nm to 25 nm.
Optionally, in the epitaxial structure of a semiconductor transistor, the composite barrier layer further includes a third barrier layer, and the third barrier layer is located on the second barrier layer.
Optionally, in the epitaxial structure of the semiconductor transistor, a material of the third barrier layer includes AlN.
Optionally, in the epitaxial structure of the semiconductor transistor, the thickness of the third barrier layer is 0.5nm to 2 nm.
Optionally, in the epitaxial structure of the semiconductor transistor, the content of Al in the first barrier layer is 12% to 40%.
Optionally, in the epitaxial structure of the semiconductor transistor, the content of Al in the second barrier layer is 2% to 30%.
Optionally, in the epitaxial structure of the semiconductor transistor, the first barrier layer and the second barrier layer are made of any one or a combination of two or more of AlGaN, AlInGaN, and AlInN.
Optionally, in the epitaxial structure of the semiconductor transistor, an insertion layer is further included between the channel layer and the composite barrier layer.
Optionally, in the epitaxial structure of the semiconductor transistor, a material of the insertion layer includes AlN.
Optionally, in the epitaxial structure of the semiconductor transistor, the thickness of the insertion layer is 0.5nm to 2 nm.
Optionally, in the epitaxial structure of the semiconductor transistor, the material of the P-type layer includes any one or a combination of more than two of P-GaN, P-AlGaN, P-AlInN, P-InGaN, and P-AlInGaN.
Optionally, in the epitaxial structure of the semiconductor transistor, when the P-type layer is made of P-AlGaN, the content of an Al component in the P-AlGaN is less than or equal to 20%.
Optionally, in the epitaxial structure of the semiconductor transistor, the thickness of the P-type layer is 30nm to 150 nm.
In order to achieve the above and other related objects, the present invention also provides a semiconductor transistor comprising: the semiconductor transistor epitaxial structure comprises a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode are formed on the epitaxial structure, and the source electrode and the drain electrode are located on two sides of the grid electrode.
In order to achieve the above and other related objects, the present invention also provides a method for fabricating an epitaxial structure of a semiconductor transistor, including:
providing a substrate;
forming a nucleation layer on the substrate;
forming a buffer layer on the nucleation layer;
forming a channel layer on the buffer layer;
forming a composite barrier layer on the channel layer, wherein the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer;
a P-type layer is formed on the composite barrier layer.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the first barrier layer is a high Al component structure layer, and the second barrier layer has a gradually changed Al component and includes at least one low Al component structure layer.
Optionally, in the preparation method of the semiconductor transistor epitaxial structure, the second barrier layer further includes a plurality of high Al component structure layers, and the two-dimensional electron gas concentration is adjusted by setting the low Al component structure layer and the high Al component structure layer in the second barrier layer.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the Al composition of the second barrier layer is gradually changed in a step-changing manner, a linear-changing manner, or a combination of the step-changing manner and the linear-changing manner.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the thickness of the composite barrier layer is 5nm to 30 nm.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the thickness of the first barrier layer is 0.5nm to 5nm, and the thickness of the second barrier layer is 4.5nm to 25 nm.
Optionally, in the method for manufacturing an epitaxial structure of a semiconductor transistor, the content of Al in the first barrier layer is 12% to 40%.
Optionally, in the method for manufacturing an epitaxial structure of a semiconductor transistor, the content of Al in the second barrier layer is 2% to 30%.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the first barrier layer and the second barrier layer are made of any one or a combination of two or more of AlGaN, AlInGaN, and AlInN.
Optionally, in the method for manufacturing an epitaxial structure of a semiconductor transistor, the composite barrier layer further includes a third barrier layer, and the third barrier layer is formed on the second barrier.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the material of the third barrier layer includes AlN.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the thickness of the third barrier layer is 0.5nm to 2 nm.
Optionally, in the method for manufacturing an epitaxial structure of a semiconductor transistor, an insertion layer is further formed between the channel layer and the composite barrier layer in the method for manufacturing an epitaxial structure of a semiconductor transistor.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, a material of the insertion layer includes AlN.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the thickness of the insertion layer is 0.5nm to 2 nm.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the material of the P-type layer includes any one or a combination of more than two of P-GaN, P-AlGaN, P-AlInN, P-InGaN, and P-AlInGaN.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, when the P-type layer is made of P-AlGaN, the content of the Al component in the P-AlGaN is less than or equal to 20%.
Optionally, in the preparation method of the epitaxial structure of the semiconductor transistor, the thickness of the P-type layer is 30nm to 150 nm.
In the semiconductor transistor epitaxial structure, the preparation method thereof and the semiconductor transistor provided by the invention, the composite barrier layer containing the Al component with gradual change is formed, the lattice mismatch of the first barrier layer with high Al component in the composite barrier layer can be reduced, the crystal defect and dislocation are further reduced, the crystal quality is improved, the quantum limit of channel two-dimensional electron gas can be enhanced by the high barrier of the first barrier layer in the composite barrier layer, the electron tunneling probability is reduced, the current collapse and the gate leakage current are more effectively relieved, and the performance of the transistor is improved.
Drawings
Fig. 1 is a schematic view of an epitaxial structure of a semiconductor transistor according to an embodiment of the invention;
fig. 2 is a flow chart of a method of fabricating an epitaxial structure for a semiconductor transistor according to an embodiment of the invention;
in the figures 1 to 2, it is shown,
100-substrate, 101-nucleation layer, 102-buffer layer, 103-channel layer, 104-insertion layer, 105-composite barrier layer, 106-P-type layer.
Detailed Description
In a traditional HEMT device, an AlN insertion layer is usually added between a channel layer and a barrier layer, so that the band gap difference of a heterojunction can be remarkably improved, the tunneling probability of electrons can be reduced, the quantum limit of two-dimensional electron gas in the channel can be enhanced, and current collapse and gate leakage current can be relieved to a certain extent. But because the usable growth temperature of the AlN insert layer is lower and the lattice mismatch between the AlN insert layer and the GaN channel layer causes the AlN insert layer to grow about 2 nanometers, and a large amount of defects and dislocations appear when the AlN insert layer is thicker. Because the AlN insert layer has limited thickness, the AlN insert layer reduces the electron tunneling probability, the function of reinforcing the quantum limit of channel two-dimensional electron gas cannot be fully exerted, and the improvement effect is limited.
In order to strengthen the quantum limit of channel two-dimensional electron gas and reduce the electron tunneling probability while ensuring the crystal quality, the invention provides a semiconductor transistor epitaxial structure.
The semiconductor transistor epitaxial structure and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the epitaxial structure of the semiconductor transistor sequentially includes, from bottom to top: the semiconductor device comprises a substrate 100, a nucleation layer 101, a buffer layer 102, a channel layer 103, an insertion layer 104, a composite barrier layer 105 and a P-type layer 106, wherein the composite barrier layer 105 comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer.
Wherein the substrate 100 may be sapphire (Al)2O3) The substrate 100 may be a substrate having a semiconductor layer, which may be AlN, SiC, or the like, for example, a sapphire substrate having an AlN layer formed thereon, that is, an AlN layer formed thereon may be used as the substrate 100.
The nucleation layer 101 is located on the substrate 100, and the nucleation layer 101 provides nucleation sites for a thin film (epitaxial layer), which are grown in the transverse and longitudinal directions to finally form a continuous thin film; on the other hand, the nucleation layer 101 can stress-relieve the epitaxial layer and the substrate material, and a large amount of dislocation can appear at the interface of the substrate and the epitaxial layer, so that the dislocation density is reduced in the later epitaxial layer growth, and the crystal quality is improved. The material of the nucleation layer 101 may be nitride, for example, the material of the nucleation layer 101 is one of AlN, GaN, AlGaN, or the like, or a combination of any two of them, and further, the material of the nucleation layer 101 is preferably AlN.
The Buffer layer (Buffer)102 is located on the nucleation layer 101, and the Buffer layer 102 is used for reducing lattice mismatch between the substrate and the epitaxial layer, so as to reduce the possibility of defects and dislocations of the grown epitaxial layer and improve the crystal quality. The buffer layer 102 is not limited to one material, and may be a plurality of materials, combinations of different dopants and different doping contents, etc., and all the buffer layer materials disclosed so far are within the scope of the present invention. Preferably, the material of the buffer layer 102 is nitride, and for example, the material of the buffer layer 102 is any one or a combination of any two of GaN, AlGaN, and AlGaN with a graded Al composition.
The channel layer 103 is located on the buffer layer 102, the channel layer 103 is an unintentional doping layer, and the material of the channel layer 103 may be GaN or InAlGaN, but is not limited thereto, and preferably, the material of the channel layer 103 is GaN.
The insertion layer 104 is located on the channel layer 103, and preferably, the insertion layer 104 is made of AlN. The insertion layer 104 can improve the band gap difference of the heterojunction, is beneficial to reducing the electron tunneling probability and enhancing the quantum limit of the channel two-dimensional electron gas. The thickness of the insertion layer 104 is preferably 0.5nm to 2 nm.
The nucleation layer 101, the buffer layer 102, the channel layer 103, and the insertion layer 104 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Plasma Enhanced Chemical Vapor Deposition (PECVD), laser sputtering, or the like, but are not limited thereto.
The composite barrier layer 105 is located on the trench insertion layer 104, and the thickness of the composite barrier layer 105 is preferably 5nm to 30 nm. Specifically, a first barrier layer of the composite barrier layer 105 is first formed on the insertion layer 104. The first barrier layer has high Al composition and can comprise any one or combination of AlGaN, AlInGaN and AlInN. The AlGaN can reduce lattice mismatch, so that lattice dislocation and defects are reduced, crystal quality can be improved, meanwhile, the AlGaN contains an Al component, quantum limitation of channel two-dimensional electron gas can be enhanced, electron tunneling probability is reduced, current collapse and gate leakage current are relieved more effectively, device performance is improved, growth temperature of the AlGaN is lower than that of the AlN, the AlGaN can grow thicker, the electron tunneling probability is reduced, the function of reinforcing quantum limitation of the channel two-dimensional electron gas can be fully exerted, and a good improvement effect is achieved. The thickness of the first barrier layer is preferably 0.5nm to 5 nm.
Further, the second barrier layer is formed on the first barrier layer, and the second barrier layer is a structural layer with gradually changed components. The second barrier layer may be made of any one or a combination of two or more of AlGaN, AlInGaN, and AlInN. The second barrier layer preferably has a thickness of 4.5nm to 25 nm.
Furthermore, the first barrier layer is a high-Al component structural layer, and the second barrier layer has a gradually-changed Al component and comprises at least one low-Al component structural layer. For example, the second barrier layer includes only one structural layer with a low Al composition, that is, the composite barrier layer includes a structural layer with a high Al composition (first barrier layer) and a structural layer with a low Al composition (second barrier layer) thereon, and the composite barrier layer 105 is a structural layer with a gradual change from a high Al composition to a low Al composition. The Al content of the first barrier layer is 12% -40%, and the Al content of the second barrier layer is 2% -30%.
Further, the second barrier layer can also comprise a plurality of high Al component structure layers. For example, the second barrier layer comprises a low Al component structure layer and a high Al component structure layer on the low Al component structure layer, and the Al content of the high Al component structure layer in the second barrier layer is lower than the Al content of the high Al component structure layer in the first barrier layer. Namely, the composite barrier layer comprises a high Al component structural layer (first barrier layer), a low Al component structural layer positioned on the high Al component structural layer and a high Al component structural layer (second barrier layer) positioned on the low Al component structural layer, and the composite barrier layer is a structural layer which gradually changes from the high Al component to the low Al component and then gradually changes from the low Al component to the high Al component. The second barrier layer may also include two or more low Al composition structure layers and two or more high Al composition structure layers, and so on. The concentration of the two-dimensional electron gas is adjusted through the arrangement of the low Al component structural layer and the high Al component structural layer in the second barrier layer, namely the high Al component structural layer can be inserted into the low Al component structural layer to adjust the concentration of the two-dimensional electron gas of the channel. The low Al component structural layer and the high Al component structural layer in the second barrier layer are arranged to meet the requirement that the concentration of two-dimensional electron gas formed in the heterojunction reaches a process requirement value. The arrangement of the low Al component structure layer and the high Al component structure layer in the second barrier layer may also affect the sheet resistance of the epitaxial structure, and therefore, the arrangement of the low Al component structure layer and the high Al component structure layer in the second barrier layer may also need to meet the process requirements of the sheet resistance.
The Al component in the composite barrier layer is gradually changed in a mode of any one of step gradual change, linear gradual change and combination of step gradual change and linear gradual change.
The step gradual change refers to the content of the Al component in a step-type abrupt change. The implementation manner of the step gradual change can be as follows: at least two growth steps with different Al composition contents (including the first barrier layer) are provided, and the intervals between the Al composition contents of adjacent growth steps in the step-gradient may be different or the same, for example, the intervals between the Al composition contents of adjacent growth steps are different, and are respectively 25%, 10%, 8% and 5%. As another example, the intervals between the Al component contents of the adjacent growth steps are the same, 20%, 12%, and 4%, respectively. The tendency of the stepwise-graded Al component content is not limited, and may be gradually decreased, for example, 25%, 10%, 8%, and 5% of the Al component content, respectively, or increased after decreasing, for example, 25%, 10%, 20%, and 5% of the Al component content, respectively.
The linear gradual change means that the content of the Al component linearly and continuously changes. In a growth machine, for example, MOCVD, the growth mode of two adjacent structural layers with different Al component contents may include an abrupt change mode and a linear gradual change mode, in the abrupt change mode, the growth mode in Recipe is set to an abrupt change, and after a structure with one Al component content is grown, an MFC (flow meter) may directly jump to the Al component content of the next structure. In the linear gradual mode, the growth mode in Recipe is set to be linearly gradual, and after one structure with the Al component content is grown, the MFC (flow meter) gradually decreases (or increases) to the Al component content of the next structure, for example, the Al component content of two growth steps is set to be 25% and 5%, the Al component content gradually decreases from 25% to 5% in the two growth steps, and the decreasing process is a continuous process. Namely, the linear gradual change is realized by setting the growth mode in the machine equipment to be a linear gradual change mode.
The implementation manner of the combination of the step gradual change and the linear gradual change can be as follows: at least three growth steps with different Al component contents (including the first barrier layer) are set, the Al component content of at least one adjacent growth step is changed in a step mode, and the Al component content of at least one adjacent growth step is changed in a linear mode. For example, the Al component content is 25%, 15%, 10% and 20%, respectively, wherein 25% to 15% and to 10% are stepwise varied, and 10% to 20% are linearly stepwise varied.
The composite barrier layer may also include a third barrier layer, and the third barrier layer is on the second barrier layer. The third barrier layer can be arranged according to a subsequent etching process and is used as a barrier layer for etching the P-type layer 106, so that over-etching in the subsequent etching process of the P-type layer 106 is prevented. The third barrier layer may be made of nitride, such as AlN or SiN, and preferably, the third barrier layer is made of AlN. The thickness of the third barrier layer is preferably 0.5nm to 2 nm.
The P-type layer 106 is located on the composite barrier layer 105, the material of the P-type layer 106 is not limited to one material, and may be a plurality of materials, combinations of different dopants and different doping contents, and the like, for example, the P-type layer 106 may include any one or a combination of two or more of P-GaN, P-AlGaN, P-AlInN, P-InGaN, P-AlInGaN, and the like. When the P-type layer 106 can be P-AlGaN, the Al component content is less than or equal to 20%. The thickness of the P-type layer 106 is preferably 30nm to 150 nm. The P-type layer 106 may be doped with an element such as magnesium, zinc, etc., and the doping level may be a function of a single doping level or epitaxial growth direction, but is not limited thereto.
The composite barrier layer 105 and the P-type layer 106 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Plasma Enhanced Chemical Vapor Deposition (PECVD), laser sputtering, or the like, but is not limited thereto.
The present invention also provides a semiconductor transistor comprising: the semiconductor transistor epitaxial structure comprises a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode are formed on the epitaxial structure, and the source electrode and the drain electrode are located on two sides of the grid electrode. That is, after the P-type layer 106 is formed, a source, a drain and a gate are formed, and the source and the drain are located at two sides of the gate. That is, the P-type layer 106 is etched to expose the upper surface of the composite barrier layer, and then a source and a drain are formed on the upper surface of the composite barrier layer, followed by forming a gate on the P-type layer 106. Of course, the gate electrode may be formed first, and then the source electrode and the drain electrode may be formed.
The semiconductor transistor is preferably a GaN transistor, and may be a transistor of a multi-component compound such as InGaN/InAlGaN. The epitaxial structure of the semiconductor transistor containing the composite barrier layer with the gradually-changed components, provided by the embodiment of the invention, can enhance the quantum limit of channel two-dimensional electron gas and reduce the electron tunneling probability while ensuring the crystal quality, so that the current collapse and the gate leakage current are effectively relieved, and the performance of the device is improved.
In addition, the present invention also provides a method for preparing the above-mentioned epitaxial structure of a semiconductor transistor, which can be seen from fig. 2, and specifically includes:
step S1: providing a substrate;
step S2: forming a nucleation layer on the substrate;
step S3: forming a buffer layer on the nucleation layer;
step S4: forming a channel layer on the buffer layer;
step S5: forming a composite barrier layer on the channel layer, wherein the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer;
step S6: a P-type layer is formed on the composite barrier layer.
Wherein the substrate may be sapphire (Al)2O3) And a silicon substrate, and the substrate may be a substrate having a semiconductor layer, and the semiconductor layer may be AlN, SiC, or the like.
The first barrier layer is a high Al component structural layer, and the second barrier layer has a gradually changed Al component and comprises at least one low Al component structural layer. The second barrier layer further comprises a plurality of high-Al component structure layers, and the concentration of the two-dimensional electron gas is adjusted through the arrangement of the low-Al component structure layer and the high-Al component structure layer in the second barrier layer. The Al content of the high Al component structural layer in the second barrier layer is lower than that of the first barrier layer.
The composite barrier layer may also include a third barrier layer, and the third barrier layer is formed on the second barrier.
The preparation method of the semiconductor transistor epitaxial structure further comprises the following steps: interposing a layer between the channel layer and the composite barrier layer.
The process method for sequentially forming the nucleation layer, the buffer layer, the channel layer, the insertion layer, the composite barrier layer and the P-type layer on the substrate includes, but is not limited to, Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Plasma Enhanced Chemical Vapor Deposition (PECVD), laser sputtering, and the like.
The epitaxial structure prepared by the preparation method of the epitaxial structure of the semiconductor transistor can be used for forming the semiconductor transistor, namely after the P-type layer is formed, the P-type layer is etched until the upper surface of the composite barrier layer is exposed; and forming a source electrode and a drain electrode on the exposed composite barrier layer, and forming a grid electrode on the P-type layer, wherein the source electrode and the drain electrode are positioned on two sides of the grid electrode.
The manufacturing sequence of the source, the drain and the gate can also be adjusted according to actual requirements, for example, the source and the drain can be manufactured first, and then the gate can be manufactured, or the gate can be manufactured first, and then the source and the drain can be manufactured.
The grid electrode and the P-type layer form Schottky contact or ohmic contact, and the source electrode, the drain electrode and the composite barrier layer form ohmic contact. The metal of the gate may be a schottky or ohmic contact gate metal such as TiN, W, Ni/Au, Pd/Au, etc., and is not limited thereto. The etching method of the P-type layer may be dry etching or wet etching, and the etching reagent for the dry etching may be an etching gas that can be applied to a dry etching process, such as Cl-based etching gas and/or F-based etching gas, but is not limited thereto. Typically the etching gas may be Cl2/N2/O2Other Cl-based etching gases containing oxygen, e.g. Cl2/BCl3/N2/O2、BCl3/N2/O2、Cl2/O2Etc. etching mixed gas containing Cl group, F group, such as Cl2/BCl3/SF6、Cl2/SF6Etc., conventional Cl-based etchingGases, e.g. Cl2、Cl2/BCl3And the like.
In summary, the epitaxial structure prepared by the preparation method of the epitaxial structure of the semiconductor transistor provided by the embodiment of the invention can ensure the crystal quality, enhance the quantum restriction of channel two-dimensional electron gas, and reduce the electron tunneling probability, thereby more effectively relieving current collapse and gate leakage current, and improving the device performance.
In addition, it is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims (37)

1. The utility model provides a semiconductor transistor epitaxial structure which characterized in that, epitaxial structure includes from the bottom up in proper order: the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer.
2. The semiconductor transistor epitaxial structure of claim 1 wherein the first barrier layer is a high Al composition structural layer and the second barrier layer is graded in Al composition and comprises at least one low Al composition structural layer.
3. The semiconductor transistor epitaxial structure of claim 2 wherein the second barrier layer further comprises a plurality of high Al composition structure layers, and the two-dimensional electron gas concentration is adjusted by the arrangement of the low Al composition structure layer and the high Al composition structure layer in the second barrier layer.
4. The semiconductor transistor epitaxial structure of claim 2 wherein the Al composition of the second barrier layer is graded in a manner including any one of a step grading, a linear grading, and a combination of a step grading and a linear grading.
5. The semiconductor transistor epitaxial structure of claim 1 wherein the composite barrier layer has a thickness of 5nm to 30 nm.
6. The semiconductor transistor epitaxial structure of claim 1 wherein the first barrier layer is 0.5nm to 5nm thick and the second barrier layer is 4.5nm to 25nm thick.
7. The semiconductor transistor epitaxy structure of claim 1, wherein the composite barrier layer further comprises a third barrier layer, and the third barrier layer is on the second barrier layer.
8. The semiconductor transistor epitaxial structure of claim 7, wherein the material of the third barrier layer comprises AlN.
9. The semiconductor transistor epitaxial structure of claim 7 wherein the third barrier layer has a thickness of 0.5nm to 2 nm.
10. The semiconductor transistor epitaxial structure of claim 1 wherein the first barrier layer has an Al content of 12% to 40%.
11. The semiconductor transistor epitaxial structure of claim 1, wherein the content of Al in the second barrier layer is in the range of 2% to 30%.
12. The epitaxial structure of a semiconductor transistor according to claim 1, wherein the first barrier layer and the second barrier layer are made of any one or a combination of two or more of AlGaN, AlInGaN and AlInN.
13. The semiconductor transistor epitaxial structure of claim 1 further comprising an intervening layer between the channel layer and the composite barrier layer.
14. The semiconductor transistor epitaxial structure of claim 13, wherein the material of the insertion layer comprises AlN.
15. The semiconductor transistor epitaxial structure of claim 13, wherein the thickness of the insertion layer is between 0.5nm and 2 nm.
16. The epitaxial structure of a semiconductor transistor according to claim 1, wherein the material of the P-type layer comprises any one or a combination of two or more of P-GaN, P-AlGaN, P-AlInN, P-InGaN and P-AlInGaN.
17. The epitaxial structure of a semiconductor transistor according to claim 16, wherein when the P-type layer is made of P-AlGaN, the content of the Al component in the P-AlGaN is 20% or less.
18. The semiconductor transistor epitaxial structure of claim 1, wherein the P-type layer has a thickness of 30nm to 150 nm.
19. A semiconductor transistor, comprising: the epitaxial structure of a semiconductor transistor of any of claims 1 to 18, a source, a drain and a gate formed on the epitaxial structure, the source and drain being located on either side of the gate.
20. A method for preparing an epitaxial structure of a semiconductor transistor is characterized by comprising the following steps:
providing a substrate;
forming a nucleation layer on the substrate;
forming a buffer layer on the nucleation layer;
forming a channel layer on the buffer layer;
forming a composite barrier layer on the channel layer, wherein the composite barrier layer comprises a first barrier layer and a second barrier layer which are sequentially stacked, and the Al component content of the second barrier layer is lower than that of the first barrier layer;
a P-type layer is formed on the composite barrier layer.
21. The method of claim 20, wherein the first barrier layer is a high Al composition structure layer, and the second barrier layer has a graded Al composition and comprises at least one low Al composition structure layer.
22. The method of fabricating an epitaxial structure for a semiconductor transistor according to claim 21, wherein the second barrier layer further comprises a plurality of high Al composition structure layers, and the two-dimensional electron gas concentration is adjusted by the arrangement of the low Al composition structure layer and the high Al composition structure layer in the second barrier layer.
23. The method for manufacturing an epitaxial structure of a semiconductor transistor according to claim 21, wherein the Al composition of the second barrier layer is graded in a manner including any one of a step grading, a linear grading, and a combination of the step grading and the linear grading.
24. The method of claim 20, wherein the composite barrier layer has a thickness of 5nm to 30 nm.
25. The method for manufacturing an epitaxial structure for a semiconductor transistor according to claim 20, wherein the first barrier layer has a thickness of 0.5nm to 5nm, and the second barrier layer has a thickness of 4.5nm to 25 nm.
26. The method for manufacturing an epitaxial structure for a semiconductor transistor according to claim 20, wherein the content of Al in the first barrier layer is 12% to 40%.
27. The method for manufacturing an epitaxial structure for a semiconductor transistor according to claim 20, wherein the content of Al in the second barrier layer is 2% to 30%.
28. The method for manufacturing an epitaxial structure of a semiconductor transistor according to claim 20, wherein the first barrier layer and the second barrier layer are made of any one or a combination of two or more of AlGaN, AlInGaN, and AlInN.
29. The method of fabricating a semiconductor transistor epitaxial structure of claim 20, in which the composite barrier layer further comprises a third barrier layer, and the third barrier layer is formed on the second barrier.
30. The method of claim 29, wherein the third barrier layer comprises AlN.
31. The method of manufacturing an epitaxial structure for a semiconductor transistor according to claim 29, wherein the third barrier layer has a thickness of 0.5nm to 2 nm.
32. The method of manufacturing an epitaxial structure for a semiconductor transistor according to claim 20, wherein an insertion layer is further formed between the channel layer and the composite barrier layer.
33. The method of claim 32, wherein the material of the insertion layer comprises AlN.
34. The method of claim 32, wherein the thickness of the insertion layer is between 0.5nm and 2 nm.
35. The method for preparing the epitaxial structure of the semiconductor transistor according to claim 20, wherein the material of the P-type layer comprises any one or a combination of two or more of P-GaN, P-AlGaN, P-AlInN, P-InGaN, and P-AlInGaN.
36. The method for manufacturing an epitaxial structure of a semiconductor transistor according to claim 35, wherein when the P-type layer is made of P-AlGaN, the content of the Al component in the P-AlGaN is not more than 20%.
37. A method of fabricating an epitaxial structure for a semiconductor transistor according to claim 20, wherein the P-type layer has a thickness of 30nm to 150 nm.
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