CN113270435B - Silicon-based graphene photoelectric detection array and CMOS three-dimensional integration method thereof - Google Patents

Silicon-based graphene photoelectric detection array and CMOS three-dimensional integration method thereof Download PDF

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CN113270435B
CN113270435B CN202110475908.8A CN202110475908A CN113270435B CN 113270435 B CN113270435 B CN 113270435B CN 202110475908 A CN202110475908 A CN 202110475908A CN 113270435 B CN113270435 B CN 113270435B
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徐杨
刘亦伦
吕建杭
董云帆
刘粒祥
俞滨
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Zhejiang University ZJU
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Abstract

The invention discloses a silicon-based graphene photoelectric detection array and a CMOS three-dimensional integration method thereof, wherein the silicon-based graphene photoelectric detection array adopts a p-type silicon substrate, and comprises a grid, a semiconductor silicon substrate, an oxide insulating layer, a single-layer graphene film and the like; the photosensitive pixel area unit in the array device is isolated from an external area by adopting an LOCOS (local area operation system) process, so that the low crosstalk effect of a small-size array is realized; the CMOS three-dimensional integration technology adopts a flip-chip interconnection technology to realize effective integration of the graphene photoelectric detection array and the readout circuit chip and realize excellent heat conduction; the CMOS readout circuit adopts a trans-impedance amplifier, a sampling amplifier and an analog-digital converter to output high-quality and low-noise signals. The invention realizes the combination of the graphene and the traditional CMOS integrated process, widens the spectral response range, improves the imaging quality and expands the application scene in the photoelectric detection field.

Description

Silicon-based graphene photoelectric detection array and CMOS three-dimensional integration method thereof
Technical Field
The invention belongs to the technical field of image sensors, relates to an image sensor device structure, and particularly relates to a silicon-based graphene photoelectric detection array and a CMOS (complementary metal oxide semiconductor) three-dimensional integration method thereof.
Background
The photoelectric detector can sense light and convert analog signal current, and image acquisition, transmission and processing can be realized through signal processing. The photoelectric detector has good light sensing efficiency and extremely high imaging quality, and has wide application in the fields of high-end imaging chemical material analysis, medical treatment and health, space technology and the like. The mainstream manufacturing technology of the photoelectric detector at present is mainly based on the traditional silicon-based CMOS process, and has the advantages of low cost, high integration density, good compatibility and the like. The traditional silicon-based CMOS process is approaching its performance limit at the next 10 nm technology node, and it is difficult to continue to improve performance due to limitations from the physical laws and manufacturing costs. Therefore, a three-dimensional CMOS integration method using new materials needs to be developed to widen the spectral response range, improve the imaging quality, and expand the application scenarios in the field of photodetectors.
Graphene (Graphene) is a novel two-dimensional material consisting of carbon atoms in sp2Planar thinness of hybrid orbital hexagonal latticesFilm, only one carbon atom thick. Graphene is currently the thinnest and hardest nanomaterial in the world. The transparency of the transparent film is extremely high, and the visible light absorption rate is only 2.3 percent; the thermal conductivity coefficient of the graphene is as high as 5300W/m.K, and the electron mobility exceeds 15000cm at normal temperature2V.s, and a resistivity of only about 10-6Omega cm. The graphene can be used as a transparent conductive film, so that the light absorption capacity of the device is improved, and the signal transfer output speed is increased.
Disclosure of Invention
The invention aims to provide a silicon-based graphene photoelectric detection array and a CMOS three-dimensional integration method thereof aiming at the defects of the prior art.
The purpose of the invention is realized by the following technical scheme: a silicon-based graphene photoelectric detection array sequentially comprises a p-type semiconductor silicon substrate, an N well, an oxide insulating layer, a first passivation layer, a second passivation layer and a CMOS readout circuit from bottom to top; the N trap is deposited to form an isolation layer; the oxide insulating layer is provided with a grid through hole, the upper surface of the oxide insulating layer is provided with a pixel electrode, the pixel electrode is covered with a single-layer graphene film, the graphene film is covered with a first passivation layer, the pixel electrode and the grid through hole are exposed on the first passivation layer, and a first UBM layer, a solder bump, a second UBM layer and a metal electrode are sequentially arranged on the exposed pixel electrode and the exposed grid through hole; and covering a second passivation layer on the metal electrode, and arranging a CMOS reading circuit communicated with the metal electrode on the second passivation layer.
Furthermore, two parallel pixel electrodes are arranged at two ends of each pixel point on the upper surface of the oxide insulating layer, and the single-layer graphene film of each pixel point is in contact with the oxide insulating layer and the two pixel electrodes of the pixel point.
Furthermore, the N well is formed by doping the upper surface of the p-type semiconductor silicon substrate, and the doping depth is 10-15 μm.
Furthermore, the isolation layer is a silicon nitride isolation layer, a silicon nitride layer is deposited on the N trap, a silicon nitride mask is utilized to perform deposition, patterning and silicon etching, a groove is formed, deposited oxide is filled in the groove, the silicon nitride isolation layer is used for isolating silicon, and the thickness of the silicon nitride isolation layer is 5 nm-20 nm.
Further, the oxide insulating layer is silicon dioxide, selective oxidation of silicon is carried out through a LOCOS process, and the thickness is 5 nm-20 nm.
Further, the CMOS readout circuit is composed of a time sequence grid voltage input circuit, a trans-impedance amplifier, a sampling amplifier and an analog-to-digital converter (ADC); the time sequence grid voltage input circuit is communicated with the grid through hole; the input end of the trans-impedance amplifier is communicated with the pixel electrode, and the output end of the trans-impedance amplifier is sequentially connected with the sampling amplifier and the analog-to-digital converter.
Furthermore, the pixel electrode and the metal electrode are both metal film electrodes, are made of chrome-gold alloy and have the thickness of 800 nm.
Further, the first passivation layer and the second passivation layer are silicon nitride, and the reaction temperature is 50-100 ℃.
Further, the first UBM layer and the second UBM layer are both of a three-layer structure and respectively comprise chromium, chromium-copper (mass fraction is 50% -50%) and copper.
Furthermore, the solder bumps are indium columns with consistent thickness and uniformity. The indium columns can enable the pixel electrodes and the UBM layers on the metal electrodes to complete the processes of alignment, bonding and backflow, and the success rate of flip-chip bonding connection can be improved.
Furthermore, when a single pixel in the photoelectric detection array works, a time sequence pulse bias voltage is applied to the grid through hole to drive the p-type semiconductor silicon substrate to enter a deep depletion state, meanwhile, the current in a pixel loop is read as a signal current through pixel electrodes at two ends of the single-layer graphene film, the incident light power is obtained, all the pixels are read to the CMOS reading circuit according to the columns, and the incident light power of the array can be obtained.
Further, the output signal of the photoelectric detection array is input into a CMOS reading circuit, namely in the pulse grid voltage time sequence operation process, the output signal of each pixel is subjected to current-voltage conversion by a trans-impedance amplifier and is input into a sampling amplifier, the sampling amplifier sequentially selects an initial position before reading out the photocurrent and samples the current at the point under the action of a fixed time sequence, then samples the photocurrent in work, subtracts two sampling values to obtain the final output, and after the output signal enters an ADC (analog-to-digital converter) to complete analog-to-digital conversion, the circuit automatically resets and waits for the output signal of the next pixel to be sampled.
The invention also provides a CMOS three-dimensional integration method of the silicon-based graphene photoelectric detection array, which specifically comprises the following steps: the silicon-based graphene photoelectric detection array is divided into two chip parts, wherein the first part is a photoelectric detection chip part, the second part is a CMOS reading circuit chip part, after the two parts are respectively prepared, the photoelectric detection chip and the CMOS reading circuit chip are respectively sucked by using an alignment bonding tool, the two chips are respectively placed on a base by using a self-alignment display system, solder bumps of the two chips are positioned at corresponding contact points of the base, a flip-chip welding mode is adopted, a heating and pressurizing method is used for causing solder to reflow and forming electrical and physical connection between the base and the chips, conditions such as pressure welding interconnection pressure, time and temperature are strictly controlled, and the angle problem between the two chips is controlled, so that a good flip-chip interconnection effect is achieved.
The working principle of the silicon-based graphene photoelectric detection array is as follows:
a timing pulse bias is applied to the gate via of the probe array. The pulse voltage is grid voltage, at the time when the grid voltage is 0V, the time sequence of the sampling amplifier is started, and the initial state signal I of the pixel point is sampled1(ii) a When the grid voltage jumps from 0V to 5V, the semiconductor silicon substrate generates a deep depletion potential well, incident light can accumulate photo-generated charges in the silicon, the time sequence of the sampling amplifier can be started again, and the working state signal I of the pixel point is sampled2And outputs the difference value of the two values to the ADC as an output signal current. When the grid voltage sequence returns to 0V, the pixel is reset and waits for the next sequence to start. The method can greatly eliminate the inherent noise of the device, thereby improving the sensitivity and the detection speed of the device.
The invention has the following beneficial effects:
1. according to the invention, the graphene is used for replacing a metal layer in a traditional photoelectric detector, so that the incidence efficiency of light is greatly improved. And the preparation process of the graphene is mature, the manufacturing cost is relatively low, and the preparation and production are easy.
2. The invention provides a novel CMOS three-dimensional integration method, which adds graphene into the traditional silicon-based production process, effectively widens the spectral response range of a photoelectric detector and improves the imaging quality of the photoelectric detector.
3. The invention adopts the flip chip interconnection technology, has excellent heat conduction characteristic and is beneficial to realizing the effective heat dissipation of the device.
4. The invention adopts the column selection sequence for reading, has simple time sequence and effectively reduces the reset noise in the reading circuit.
5. According to the invention, silicon nitride is adopted as an isolation well among pixel points, and a surrounding oxide insulation layer prepared by an LOCOS (local oxidation of silicon) process is adopted as isolation among arrays, so that the low crosstalk effect of small-size arrays is realized.
Drawings
Fig. 1 is a schematic structural diagram of a silicon-based graphene photodetection array according to the present invention, wherein a p-type semiconductor silicon substrate 1, an N well 2, an isolation layer 3, an oxide insulating layer 4, a pixel electrode 5, a single-layer graphene film 6, a through-hole gate 7, a solder bump 8, a first UBM layer 9, a metal electrode 10, a first passivation layer 11, a timing gate voltage input circuit 12, a transimpedance amplifier 13, a sampling amplifier 14, an ADC 15, a CMOS readout circuit 16, a second passivation layer 17, and a first UBM layer 18;
FIG. 2 is a timing signal diagram of a silicon-based graphene photodetection array according to the present invention;
fig. 3 is a diagram of the imaging effect of the silicon-based graphene photoelectric detection array of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be fully described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the silicon-based graphene photoelectric detection array provided by the invention sequentially comprises a p-type semiconductor silicon substrate 1, an N well 2, an oxide insulating layer 4, a first passivation layer 11, a second passivation layer 17 and a CMOS readout circuit 16 from bottom to top; the N trap 2 is deposited to form an isolation layer 3; a gate through hole 7 is formed in the oxide insulating layer 4, a pixel electrode 5 is arranged on the upper surface of the oxide insulating layer, a single-layer graphene film 6 covers the pixel electrode 5, a first passivation layer 11 covers the graphene film 6, the pixel electrode 5 and the gate through hole 7 are exposed on the first passivation layer 11, and a first UBM layer 9, a solder bump 8, a second UBM layer 18 and a metal electrode 10 are sequentially arranged on the exposed pixel electrode 5 and the exposed gate through hole 7; a second passivation layer 17 is covered on the metal electrode 10 and a CMOS readout circuit 16 is provided on the second passivation layer 17 in communication with the metal electrode 10.
Further, the solder bumps 8 are indium columns with proper height and consistent uniformity. The indium columns can enable the pixel electrodes and the UBM layers on the metal electrodes to complete the processes of alignment, bonding and backflow, and the success rate of flip-chip bonding connection can be improved.
Further, the CMOS readout circuit 16 is composed of a timing gate voltage input circuit 12, a transimpedance amplifier 13, a sampling amplifier 14, and an analog-to-digital converter (ADC) 15; the time sequence grid voltage input circuit is communicated with the grid through hole; the input end of the trans-impedance amplifier is communicated with the pixel electrode, and the output end of the trans-impedance amplifier is sequentially connected with the sampling amplifier and the analog-to-digital converter.
As shown in fig. 2, in the pulse grid voltage timing sequence operation process, the output signal of each pixel is subjected to current-voltage conversion by the transimpedance amplifier and is input to the sampling amplifier, the sampling amplifier selects an initial position and samples the current point in sequence before reading out the photocurrent under the action of a fixed timing sequence, then samples the photocurrent in operation, subtracts two sampling values to obtain the final output, and after the output signal enters the ADC to complete analog-to-digital conversion, the circuit automatically resets and waits for the output signal of the next pixel to be sampled. The sampling mode reduces the noise of the device caused by resetting, and can improve the noise parameter and the signal-to-noise ratio of the device.
As shown in FIG. 3, the device was imaged clearly under visible light after the imaging experiment through the column selection procedure.
The method for preparing the silicon-based graphene photoelectric detection array comprises the following steps:
1. preparation of silicon-based graphene photoelectric detection array part
(1) Doping a p-type semiconductor silicon substrate with the resistivity of 1 k-10 k omega-cm on the upper surface of the silicon substrate, wherein the doping type is opposite to that of a silicon wafer, the doping depth is 10-15 mu m, and an N well is obtained after doping;
(2) depositing silicon nitride isolation grooves on the upper surface of the doped silicon wafer, wherein the spacing is the width of the device, and the thickness is 1-5 microns;
(3) growing a silicon dioxide insulating layer on the upper surface of the doped silicon wafer, wherein the thickness of the silicon dioxide insulating layer is 5 nm-100 nm;
(4) punching a through hole on the oxide layer, wherein the radius of the through hole is 20 microns;
(5) manufacturing parallel pixel electrode patterns on the surface of the silicon dioxide insulating layer by using a photoetching technology, reserving through hole patterns, and then adopting an electron beam evaporation or thermal evaporation technology to firstly grow a chromium adhesion layer with the thickness of about 15nm and then grow a gold layer with the thickness of 80nm as an electrode;
(6) covering a single-layer graphene film on the upper surfaces of the parallel pixel electrodes and the silicon dioxide insulating layer; graphene transfer using a wet process: uniformly spin-coating a layer of polymethyl methacrylate (PMMA) film on the surface of the single-layer graphene, then putting the single-layer graphene into an acidic etching solution, soaking for about 6 hours, and corroding to remove the copper foil, so that the single-layer graphene film supported by the PMMA is left; washing a graphene film supported by PMMA (polymethyl methacrylate) with deionized water, and transferring the washed graphene film to the upper surfaces of a silicon dioxide insulating layer, a source electrode and a drain electrode; finally, soaking the sample in acetone and isopropanol to remove PMMA; wherein the acid etching solution is prepared from CuSO4HCl and water, CuSO4：HCl：H2O＝10g:45ml:50ml；
(7) And carrying out secondary photoetching on the device, and covering the defined area of the needed single-layer graphene pattern by using photoresist. Then, Oxygen plasma reactive ion etching (Oxygen plasma ICP-RIE) is carried out, wherein the power and the etching time are respectively 75W and 3 min. Etching off redundant graphene outside the photoresist, and after etching is finished, cleaning with acetone and isopropanol to remove residual photoresist;
(8) etching the pattern of the silicon substrate at the bottom of the silicon substrate by using BOE etching liquid, and growing a silicon dioxide insulating layer on the surface of the etched surface. Wherein the BOE etching solution is prepared from 49% HF water solution: 40% NH4F, mixing an aqueous solution of 1: 6, and the thickness of the silicon dioxide insulating layer is 5 nm-100 nm.
2. Flip-chip interconnect process partial preparation
(1) Growing metal electrodes on the prepared CMOS reading circuit, wherein the size interval is the same as that of the pixel electrodes, and firstly growing a chromium adhesion layer with the thickness of about 15nm by adopting an electron beam evaporation or thermal evaporation technology, and then growing a gold layer with the thickness of 80nm as an electrode;
(2) respectively growing silicon nitride as a passivation layer on the silicon-based graphene photoelectric detection array and other parts except electrodes on the CMOS readout circuit, wherein the reaction temperature is 50-100 ℃;
(3) growing a UBM layer on a pixel electrode of a silicon-based graphene photoelectric detection array and a metal electrode of a CMOS read-out circuit by using an electron beam evaporation or thermal evaporation technology, wherein the UBM layer is of a three-layer structure and is respectively chromium, chromium-copper (mass fraction is 50-50%) and copper, a very thin gold layer can be arranged on the UBM layer and is used for preventing the oxidation of the metal copper, and the component of a flange is lead-tin alloy;
(4) indium columns grow on pixel electrodes of the silicon-based graphene photoelectric detection array to serve as solder bumps, and a filling agent covers the metal electrodes of the CMOS readout circuit to play a role in adhesion and protection;
(5) the silicon-based graphene photoelectric detection array chip is sucked by using an alignment bonding tool, the chip is placed on a base by using a self-alignment display system, solder bumps of the chip are positioned at corresponding contact points of the base, and the solder is caused to reflow by using a heating and pressurizing method to form electrical and physical connection between the base and the chip.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (9)

1. The silicon-based graphene photoelectric detection array is characterized by sequentially comprising a p-type semiconductor silicon substrate (1), an N well (2), an oxide insulating layer (4), a first passivation layer (11), a second passivation layer (17) and a CMOS (complementary metal oxide semiconductor) readout circuit (16) from bottom to top; the N trap (2) is deposited to form an isolation layer (3); a grid through hole (7) is formed in the oxide insulating layer (4), a pixel electrode (5) is arranged on the upper surface of the oxide insulating layer, a single-layer graphene film (6) covers the pixel electrode (5), a first passivation layer (11) covers the graphene film (6), the pixel electrode (5) and the grid through hole (7) are exposed on the first passivation layer (11), and a first UBM layer (9), a solder bump (8), a second UBM layer (18) and a metal electrode (10) are sequentially arranged on the exposed pixel electrode (5) and the exposed grid through hole (7); a second passivation layer (17) covers the metal electrode (10), a CMOS readout circuit (16) communicated with the metal electrode (10) is arranged on the second passivation layer (17), when a single pixel in the photoelectric detection array works, a time sequence pulse bias voltage is applied to the grid through hole (7), the p-type semiconductor silicon substrate (1) is driven to enter a deep depletion state, meanwhile, the current in the pixel circuit is read through the pixel electrodes (5) at two ends of the single-layer graphene film (6) to serve as a signal current, incident light power is obtained, all pixels are read out to the CMOS readout circuit (16) according to columns, and the incident light power of the array can be obtained.
2. The silicon-based graphene photoelectric detection array according to claim 1, wherein two parallel pixel electrodes (5) are arranged at two ends of each pixel point on the upper surface of the oxide insulating layer (4), and the single-layer graphene film (6) of each pixel point is in contact with the oxide insulating layer (4) and the two pixel electrodes (5) of the pixel point.
3. The silicon-based graphene photodetection array according to claim 1, characterized in that the N-well (2) is formed by doping the upper surface of a p-type semiconductor silicon substrate (1), and the doping depth is 10 μm to 15 μm; the isolation layer (3) is a silicon nitride isolation layer, a silicon nitride layer is deposited on the N trap (2), a silicon nitride mask is used for forming a groove after deposition, patterning and silicon etching are carried out, deposited oxide is filled in the groove to form the silicon nitride isolation layer, and the thickness of the silicon nitride isolation layer is 5 nm-20 nm.
4. The silicon-based graphene photodetection array according to claim 1, characterized in that the oxide insulating layer (4) is silicon dioxide, and selective oxidation of silicon is performed by LOCOS process, with a thickness of 5nm to 20 nm.
5. The silicon-based graphene photodetection array according to claim 1, characterized in that the CMOS readout circuit (16) is composed of a timing gate voltage input circuit (12), a transimpedance amplifier (13), a sampling amplifier (14), and an ADC (15); the time sequence grid voltage input circuit (12) is communicated with the grid through hole (7); the input end of the trans-impedance amplifier (13) is communicated with the pixel electrode (5), and the output end of the trans-impedance amplifier is sequentially connected with the sampling amplifier (14) and the analog-to-digital converter (15).
6. The silicon-based graphene photoelectric detection array according to claim 1, wherein the pixel electrode (5) and the metal electrode (10) are both metal thin film electrodes made of chrome-gold alloy and have a thickness of 800 nm.
7. The silicon-based graphene photodetection array according to claim 1, characterized in that the first passivation layer (11) and the second passivation layer (17) are silicon nitride, and the reaction temperature is 50 ℃ to 100 ℃; the first UBM layer (9) and the second UBM layer (18) are both of a three-layer structure and respectively made of chromium, chromium-copper and copper; the solder bumps (8) are indium columns with consistent thickness and uniformity.
8. The silicon-based graphene photoelectric detection array according to claim 5, wherein an output signal of the photoelectric detection array is input into a CMOS readout circuit (16), that is, in a pulse gate voltage time sequence operation process, an output signal of each pixel is subjected to current-voltage conversion by a transimpedance amplifier (13) and is input into a sampling amplifier (14), the sampling amplifier (14) selects an initial position and samples a point current before reading out a photocurrent under the action of a fixed time sequence, samples the photocurrent during operation, subtracts two sampling values to obtain a final output, and after the output signal enters an ADC (15) to complete analog-to-digital conversion, the circuit automatically resets and waits for sampling of an output signal of a next pixel.
9. A CMOS three-dimensional integration method of silicon-based graphene photoelectric detection array according to any one of claims 1 to 7, the method is characterized in that the silicon-based graphene photoelectric detection array is divided into two chip parts, wherein the first part is a photoelectric detection chip part, the second part is a CMOS readout circuit chip part, after the two parts are respectively prepared, the method comprises the steps of respectively sucking a photoelectric detection chip and a CMOS reading circuit chip by using an alignment bonding tool, respectively placing two parts of chips on a base by using a self-alignment display system, positioning solder bumps (8) of the two parts of chips on corresponding base contact points, adopting a flip chip welding mode, causing solder to reflow by using a heating and pressurizing method, forming electrical and physical connection between the base and the chips, strictly controlling conditions such as pressure, time, temperature and the like of pressure welding interconnection, and controlling the angle between the two chips so as to achieve a good flip chip interconnection effect.
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