CN113257966B - LED chip structure, preparation method thereof and display module - Google Patents

LED chip structure, preparation method thereof and display module Download PDF

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CN113257966B
CN113257966B CN202110396768.5A CN202110396768A CN113257966B CN 113257966 B CN113257966 B CN 113257966B CN 202110396768 A CN202110396768 A CN 202110396768A CN 113257966 B CN113257966 B CN 113257966B
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CN113257966A (en
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刘召军
莫炜静
邱成峰
刘时彪
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Shenzhen Stan Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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Abstract

The invention discloses an LED chip structure, a preparation method thereof and a display module, wherein the LED chip structure comprises an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, the LED chip structure is also provided with a plurality of hole structures, the hole structures sequentially penetrate through the P-type layer and the quantum hydrazine active layer until reaching the inside of the N-type layer, quantum dots are arranged in the hole structures and are positioned at the bottom of the hole structures, the quantum dots are directly contacted with the N-type layer and are not directly contacted with the quantum hydrazine active layer. According to the invention, the quantum dots are only filled into the N-type layer, and the quantum dots are not directly contacted with the quantum hydrazine active layer and the P-type layer, so that the influence of the temperature rise of the P-type layer on the performance of the quantum dots is avoided.

Description

LED chip structure, preparation method thereof and display module
Technical Field
The invention relates to the technical field of LED chips, in particular to an LED chip structure, a preparation method thereof and a display module.
Background
The existing NanoLED chip structure comprises an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, wherein the N-type layer and the P-type layer are respectively connected with a power supply, the NanoLED chip structure is further provided with a plurality of hole structures, the hole structures sequentially penetrate through the P-type layer and the quantum hydrazine active layer until the inside of the N-type layer, an N-type layer region, a quantum hydrazine active layer region and a P-type layer region in the hole structures are filled with quantum dots, and the quantum dots can generate light with specific wavelength by excitation. Because the filled quantum dots are in contact with the P-type layer, the temperature of the P-type layer is easy to rise after being communicated with a power supply, so that the temperature of the quantum dots is also increased, and the performance of the quantum dots is unstable.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an LED chip structure, a preparation method thereof and a display module.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the LED chip structure comprises an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, wherein the LED chip structure is further provided with a plurality of hole structures, the hole structures sequentially penetrate through the P-type layer and the quantum hydrazine active layer until the inside of the N-type layer, quantum dots are arranged in the hole structures, and the quantum dots are in direct contact with the N-type layer and are not in direct contact with the quantum hydrazine active layer and the P-type layer.
Preferably, the quantum well further comprises a passivation layer, the passivation layer is arranged in the hole structure and above the quantum dots, the quantum dots are closer to the N-type layer than the passivation layer, and the passivation layer isolates the quantum dots from the quantum well active layer and the P-type layer.
Preferably, the height of the passivation layer at least reaches the surface of the quantum hydrazine active layer close to the P-type layer.
Preferably, the passivation layer is made of SiO2、Si3N4Or Al2O3。
Preferably, the quantum well structure further comprises a current spreading layer formed on the surface of the P-type layer far away from the quantum well active layer and on the side wall of the P-type layer region in the pore structure.
Preferably, the current spreading layer further comprises a P-electrode layer laminated on a surface of the current spreading layer on a side away from the P-type layer.
Preferably, the display device further comprises a conductive substrate laminated to a surface of the P electrode layer on a side facing away from the P-type layer.
Preferably, the surface of the N-type layer on the side away from the P-type layer is a roughened surface.
Preferably, the organic light-emitting diode further comprises an N electrode, and the N electrode is laminated on the surface of one side of the N-type layer, which is away from the P-type layer.
The invention also discloses a preparation method of the LED chip structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises a substrate layer, an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, and the substrate is also provided with a plurality of hole structures which sequentially penetrate through the P-type layer and the quantum hydrazine active layer to the inside of the N-type layer;
and filling quantum dots in the hole structure, wherein the quantum dots are positioned at the bottom of the hole structure, and the quantum dots are in direct contact with the N-type layer and are not in direct contact with the quantum hydrazine active layer.
Preferably, the method further comprises the preparation of a passivation layer, wherein the preparation process of the passivation layer comprises the following steps: forming the passivation layer over the quantum dots in the hole structure, the quantum dots being closer to the N-type layer than the passivation layer, the passivation layer isolating the quantum dots from the quantum hydrazine active layer and the P-type layer.
Preferably, the method of forming the passivation layer is a PECVD method or an ALD method.
Preferably, the method also comprises the preparation of a current expansion layer, the preparation of a P electrode layer, the preparation of a conductive substrate, the preparation of coarsening the N-type layer and the preparation of an N electrode in sequence,
the preparation process of the current spreading layer comprises the following steps: forming the current expansion layer on the surface of the P-type layer far away from the side of the quantum hydrazine active layer and the side wall of the P-type layer region in the hole structure;
the preparation process of the P electrode layer comprises the following steps: forming the P electrode layer on the surface of the current expansion layer, which is far away from one side of the P type layer;
the preparation process of the conductive substrate comprises the following steps: forming the conductive substrate on the surface of the P electrode layer, which is far away from one side of the P type layer;
the preparation process of roughening the N-type layer comprises the following steps: removing the substrate layer, exposing the N-type layer, and roughening the surface of one side of the N-type layer, which is far away from the P-type layer, to form a roughened surface;
the preparation process of the N electrode comprises the following steps: and forming the N electrode on the roughened surface, wherein the N electrode is connected with the N-type layer.
The invention also discloses a display module which is characterized by comprising the LED chip structure.
The embodiment of the invention has the following beneficial effects:
according to the embodiment of the invention, the quantum dots are only filled in the N-type layer region in the hole structure, so that the quantum dots are not directly contacted with the quantum hydrazine active layer and the P-type layer, the influence of the temperature rise of the P-type layer on the performance of the quantum dots is avoided, and the influence of the quantum dots on the performance of the quantum hydrazine active layer is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
fig. 1 to 11 are schematic structural diagrams of a manufacturing process of an LED chip structure according to an embodiment of the invention;
the device comprises an N-type layer 3, a quantum hydrazine active layer 4, a P-type layer 5, a hole structure 6, quantum dots 7, a passivation layer 8, a current expansion layer 9, a P electrode layer 10, a conductive substrate 11, a roughened surface 12, a passivation film 13 and an N electrode 14.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 11, the invention discloses an LED chip structure, which includes an N-type layer 3, a quantum hydrazine active layer 4, and a P-type layer 5 stacked in sequence, the LED chip structure is further provided with a plurality of hole structures 6, the hole structures 6 penetrate through the quantum hydrazine active layer 4 from the outer surface of the P-type layer 5 to the inside of the N-type layer 3, the N-type layer 3 area in the hole structures 6 is filled with quantum dots 7, the quantum dots 7 are located at the bottom of the hole structures 6, the quantum dots 7 are in direct contact with the N-type layer 3, and the quantum dots 7 are not in contact with the quantum hydrazine active layer 4 and the P-type layer, so that the influence of the temperature rise of the P-type layer 5 on the performance of the quantum dots 7 is avoided, and the influence of the quantum dots 7 on the performance of the quantum hydrazine active layer 4 is also avoided.
Referring to fig. 11, in a specific embodiment, the LED chip structure further includes a passivation layer 8, the passivation layer 8 is disposed in the hole structure 6 and above the quantum dot 7, the quantum dot 7 is closer to the N-type layer 3 than the passivation layer 8, that is, the quantum dot 7 is disposed at the bottom of the hole structure 6, and the passivation layer 8 isolates the quantum dot 7 from the quantum hydrazine active layer 4 and the P-type layer 5. By arranging the passivation layer 8, the quantum dot 7 and the P-type layer 5 are isolated by the passivation layer 8, and the influence of the temperature rise of the P-type layer 5 on the performance of the quantum dot 7 is avoided. In addition, the passivation layer 8 filled in the hole structure 6 can also passivate the surface state and the defect state of the side wall of the quantum well active region 4, so that the effect of reducing leakage current caused by the defect of the side wall of the active region is achieved.
The passivation layer 8 is a spacer for spacing the quantum dot 7 from the quantum hydrazine active layer 4 and the P-type layer 5, and may be a layer structure covering the sidewall of the hole structure 6, so that the quantum dot is not in direct contact with the quantum hydrazine active layer 4 and the P-type layer 5, or may be a structure of filling the hole structure 6 and covering the quantum dot 7, as shown in fig. 11. Any structure that can separate the quantum dots 7 from the quantum well active layer 4 and the P-type layer 5 falls within the scope of the present invention.
Further, in a specific embodiment, the height of the quantum dot 7 does not exceed the surface of the N-type layer 3 close to the P-type layer 5, so as to avoid the performance influence of the quantum dot 7 on the quantum hydrazine active layer 4.
Specifically, the quantum dot 7 may be one kind of quantum dot 7, or may be two or more kinds of quantum dots 7, and the material of the quantum dot 7 may be one or more kinds of ZnSe, ZnS, CdSe, CdS, InP, and the like. The filling amount of the quantum dots 7 can be adjusted by adjusting the pore diameter of the pore structure and/or the thickness of the N-type layer 3.
Further, in a specific embodiment, the height of the passivation layer 8 at least reaches the surface of the side, close to the P-type layer 5, of the quantum hydrazine active layer 4, so that the passivation layer 8 completely shields the side wall of the quantum hydrazine active layer 4 in the hole structure 6, the surface state and the defect state of the side wall of the quantum hydrazine active layer 4 are passivated, and the magnitude of leakage current caused by the defect of the side wall of the active region is reduced.
Specifically, the passivation layer 8 may be made of SiO2、Si3N4Or Al2O3And the like.
Referring to fig. 11, the LED chip structure of the present invention further includes a current spreading layer 9, where the current spreading layer 9 is formed on the surface of the P-type layer 5 far from the quantum well active layer 4 and the sidewall of the P-type layer 5 region in the hole structure 6, and the current spreading layer 9 can increase the current uniformity of the P-type layer 5, and further increase the current uniformity of the P-type layer 5.
Further, the LED chip structure further includes a P electrode layer 10, the P electrode layer 10 is stacked on a surface of the current spreading layer 9 away from the P layer 5, and the P electrode layer 10 is mainly used for connecting a power supply.
The LED chip structure of each of the above embodiments can be used in both a flip LED chip structure and a vertical LED chip structure, in the flip LED chip structure, the P-electrode connected to the P-type region and the N-electrode 14 connected to the N-type region are both located on the same side of the LED chip structure, in the vertical LED chip structure, the P-electrode connected to the P-type region and the N-electrode 14 connected to the N-type region are respectively located on both sides of the LED chip structure, and the vertical LED chip structure has better current expandability than the flip LED chip structure.
The LED chip structure shown in fig. 1 to 11 of an embodiment of the present invention is a vertical LED chip structure, and in the vertical LED chip structure, further, the P electrode layer 10 completely covers the current spreading layer 9, and a surface of the P electrode layer 10 on a side away from the P-type layer 5 is a flat surface, so as to form the vertical LED chip structure, thereby improving current spreading.
Further, the P electrode layer 10 is a metal layer having a reflective function. The metal layer may include one or more than two metal layers, the material of the metal layer may be titanium, aluminum, silver, gold, or nickel, in a specific embodiment, the metal layer may be a titanium layer, an aluminum layer, a titanium layer, and a gold layer, which are sequentially stacked, and in another specific embodiment, the metal layer may also be a nickel layer and a silver layer, which are sequentially stacked.
Further, the LED chip structure further comprises a conductive substrate 11, the conductive substrate 11 is stacked on the surface of the P electrode layer 10, which is away from one side of the P type layer 5, the conductive substrate 11 completely covers the P electrode layer 10, the conductive substrate 11 is mainly used for heat dissipation and power supply connection, the conductive substrate 11 has high thermal conductivity, and the heat generated by the P type region can be better cooled. The conductive substrate 11 is preferably a copper conductive substrate 11 or a silicon conductive substrate 11, and has high thermal conductivity and better heat dissipation effect.
The surface of the N-type layer 3 on the side away from the P-type layer 5 is a light emitting surface, and in order to reduce total reflection of light and improve light extraction efficiency, in a specific embodiment, the surface of the N-type layer 3 on the side away from the P-type layer 5 is a roughened surface 12.
The LED chip structure further comprises an N electrode 14, the N electrode 14 is stacked on the surface of one side, away from the P-type layer 5, of the N-type layer 3, and the N electrode 14 and the P-type electrode layer 10 are different in side and are of a vertical LED chip structure.
The technical features of the above embodiments may be used interchangeably.
In the above embodiments, the thickness of the N-type layer 3 is 1500nm to 3000nm, and the material of the N-type layer 3 may be N-GaN; the thickness of the quantum hydrazine active layer 4 is 250 nm-400 nm; the quantum hydrazine active layer 4 can be made of InGaN/GaN; the thickness of the P type layer 5 is 100 nm-300 nm, and the material of the P type layer 5 can be P-GaN; the thickness of the current expansion layer 9 is 100 nm-200 nm, and the material of the current expansion layer 9 can be ITO; the thickness of the P electrode layer 10 is 100nm to 300nm, the thickness of the N electrode 14 is 100nm to 300nm, the N electrode 14 may include one or more metal layers, the material of the metal layer may be titanium, aluminum, gold, chromium or platinum, in one embodiment, the N electrode 14 may be a titanium layer, an aluminum layer, a titanium layer and a gold layer which are sequentially stacked, and in another embodiment, the N electrode 14 may also be a chromium layer, a platinum layer and a gold layer which are sequentially stacked.
The invention also discloses a display module which comprises the LED chip structure and can be applied to products such as mobile phones, flat panels, notebook computers, televisions, AR/VR equipment, vehicle instruments and central control, outdoor displays, head-up displays (HUDs) and the like.
Referring to fig. 1 to 11, the present invention further provides a method for manufacturing an LED chip structure, including the following steps:
step S1, providing a substrate, where the substrate includes a substrate layer 1, an N-type layer 3, a quantum hydrazine active layer 4, and a P-type layer 5, which are sequentially stacked, and the substrate is further provided with a pore structure 6, where the pore structure 6 penetrates through the quantum hydrazine active layer 4 from the outer surface of the P-type layer 5 to the inside of the N-type layer 3.
In this step, the substrate may be formed by a top-down method, and referring to fig. 1 and fig. 2, an N-type layer 3, a quantum hydrazine active layer 4, and a P-type layer 5 are sequentially formed on a substrate layer 1, and then a hole structure 6 is formed by etching.
Etching the hole structure 6, in particular, comprises the following processes: firstly, a layer of silicon dioxide is deposited on a P type layer 5 as a mask layer, RIE technology is adopted after exposure and development, and CF is introduced3And O2The silicon dioxide is etched by the mixed gas to form the patterned hard mask layer. Then, ICP technique is adopted, and Cl is introduced2And BCl3The area uncovered by the patterned hard mask layer is etched by the mixed gas, and a hole structure 6 penetrating through the P-type layer 5, the quantum hydrazine active layer 4 and part of the N-type layer 3 is formed. Then, the sample was placed in a BOE solution (Buffered Oxide Etch, formed by mixing hydrofluoric acid and water or ammonium fluoride and water) to remove the hard mask layer, and the sample shown in fig. 2 was obtained.
And placing the obtained sample in a KOH solution of 1mol/L at the temperature of 80 ℃ for 5-10 min, corroding the side wall of the hole structure 6 to remove damage on the side wall of the hole structure 6, and then cleaning by using an HCl solution.
Of course, the substrate may also be formed by a bottom-up method, that is, an N-type layer 3 nanopillar array, a quantum hydrazine active region nanopillar array, and a P-type layer 5 nanopillar array are directly and sequentially grown on the substrate layer 1, and a hole structure 6 is formed in a gap between the nanopillars, so as to form the structure shown in fig. 2.
In the present embodiment, in order to avoid lattice defects at the interface, a buffer layer 2 is further formed on the substrate layer 1, and then an N-type layer 3, a quantum hydrazine active layer 4, and a P-type layer 5 are sequentially formed on the buffer layer 2.
Step S2: referring to fig. 3, quantum dots 7 are filled into the region of the N-type layer 3 within the pore structure 6.
Step S3: referring to fig. 4, the passivation layer 8 is filled into the quantum well active layer 4 region within the hole structure 6, such that the passivation layer 8 isolates the quantum dots 7 from the P-type layer 5.
In particular, the passivation layer 8 may be deposited in the hole structure 6 to the same depth as the active region using PECVD (plasma enhanced chemical vapor deposition technique) or ALD (atomic layer deposition technique).
Step S4: referring to fig. 5, a current spreading layer 9 is formed on the surface of the P-type layer 5 on the side away from the quantum well active layer 4 and on the sidewall of the P-type layer 5 region within the hole structure 6.
Specifically, the current spreading layer 9 may be formed using electron beam evaporation or measurement and control sputtering techniques.
Step S5: referring to fig. 6, a P-electrode layer 10 is formed on the surface of the current spreading layer 9 on the side away from the P-type layer 5.
Specifically, a metal layer having a reflection function is deposited in the hole structure 6 and on the surface of the P-type layer 5 by electron beam evaporation.
Step S6: referring to fig. 7, a conductive substrate 11 is formed on a surface of the P-electrode layer 10 on a side facing away from the P-type layer 5.
Specifically, the conductive substrate 11 is bonded to the P electrode layer 10.
Step S7: referring to fig. 8, the substrate layer 1 and the buffer layer 2 are removed.
Step S8: referring to fig. 9, the surface of the N-type layer 3 on the side away from the P-type layer 5 is roughened to form a roughened surface 12.
Specifically, the surface of the N-type layer 3 made of N-GaN material can be roughened by using a hot KOH solution to form a hexagonal cone shape, so that total reflection of light can be reduced, and light extraction efficiency can be improved.
Step S9: referring to fig. 10, a patterned passivation film 13 is formed on the roughened surface 12 and the side surface of the LED chip structure, and the patterned passivation film 13 has a hollow pattern that is opened to the N-type layer 3, and the hollow pattern corresponds to the region where the N electrode 14 is located.
Specifically, the passivation film 13 may be deposited by PECVD or ALD, and then, a photoresist is spin-coated on the passivation film 13, and after exposure and development, a hollow pattern that opens to the N-type layer 3 is formed by dry etching or wet etching. The passivation film 13 may be made of SiO2、Si3N4Or Al2O3And the like.
In step S10, referring to fig. 11, the N electrode 14 is formed at the hollow pattern.
Specifically, the N-electrode 14 may be formed by electron beam evaporation of the N-electrode 14 metal.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. An LED chip structure is characterized by comprising an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, wherein the LED chip structure is also provided with a plurality of hole structures, the hole structures sequentially penetrate through the P-type layer and the quantum hydrazine active layer until the inside of the N-type layer, quantum dots are arranged in the hole structures, the quantum dots are directly contacted with the N-type layer, and the quantum dots are not directly contacted with the quantum hydrazine active layer and the P-type layer;
the thickness of the N-type layer is 1500 nm-3000 nm;
the thickness of the quantum hydrazine active layer is 250 nm-400 nm;
the thickness of the P-type layer is 100 nm-300 nm.
2. The LED chip structure of claim 1, further comprising a passivation layer disposed within the hole structure and over the quantum dots, the quantum dots being closer to the N-type layer than the passivation layer, the passivation layer isolating the quantum dots from the quantum hydrazine active layer and the P-type layer.
3. The LED chip structure of claim 2, wherein the passivation layer has a height at least up to a surface of the quantum hydrazine active layer on a side close to the P-type layer.
4. The LED chip structure of claim 2, wherein the passivation layer is made of SiO2、Si3N4Or Al2O3。
5. The LED chip structure according to any one of claims 1 to 4, further comprising a current spreading layer formed on a surface of the P-type layer on a side away from the quantum hydrazine active layer and a sidewall of the P-type layer region in the hole structure.
6. The LED chip structure of claim 5, further comprising a P electrode layer laminated on a surface of the current spreading layer on a side away from the P-type layer.
7. The LED chip structure of claim 6, further comprising a conductive substrate laminated to a surface of the P electrode layer on a side facing away from the P-type layer.
8. The LED chip structure of claim 1, 2, 3, 4, 6 or 7, wherein the surface of the N-type layer facing away from the P-type layer is roughened.
9. The LED chip structure according to claim 1, 2, 3, 4, 6 or 7, further comprising an N electrode laminated on a surface of the N-type layer on a side facing away from the P-type layer.
10. A preparation method of an LED chip structure is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a substrate layer, an N-type layer, a quantum hydrazine active layer and a P-type layer which are sequentially stacked, and the substrate is also provided with a plurality of hole structures which sequentially penetrate through the P-type layer and the quantum hydrazine active layer to the inside of the N-type layer;
and filling quantum dots in the hole structure, wherein the quantum dots are positioned at the bottom of the hole structure, and the quantum dots are in direct contact with the N-type layer and are not in direct contact with the quantum hydrazine active layer.
11. The method for preparing the passivation layer according to claim 10, further comprising preparing the passivation layer by: forming the passivation layer over the quantum dots in the hole structure, the quantum dots being closer to the N-type layer than the passivation layer, the passivation layer isolating the quantum dots from the quantum hydrazine active layer and the P-type layer.
12. The production method according to claim 11, wherein the method of forming the passivation layer is a PECVD method or an ALD method.
13. The preparation method according to claim 11 or 12, further comprising the steps of preparing a current spreading layer, preparing a P electrode layer, preparing a conductive substrate, roughening the N-type layer, and preparing an N electrode in sequence,
the preparation process of the current spreading layer comprises the following steps: forming the current expansion layer on the surface of the P-type layer far away from the side of the quantum hydrazine active layer and the side wall of the P-type layer region in the hole structure;
the preparation process of the P electrode layer comprises the following steps: forming the P electrode layer on the surface of the current expansion layer, which is far away from one side of the P type layer;
the preparation process of the conductive substrate comprises the following steps: forming the conductive substrate on the surface of the P electrode layer, which is far away from one side of the P type layer;
the preparation process of roughening the N-type layer comprises the following steps: removing the substrate layer, exposing the N-type layer, and roughening the surface of one side of the N-type layer, which is far away from the P-type layer, to form a roughened surface;
the preparation process of the N electrode comprises the following steps: and forming the N electrode on the roughened surface, wherein the N electrode is connected with the N-type layer.
14. A display module comprising the LED chip structure of any one of claims 1 to 9.
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