CN113257738B - Preparation method of array substrate, array substrate and display panel - Google Patents

Preparation method of array substrate, array substrate and display panel Download PDF

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Publication number
CN113257738B
CN113257738B CN202110611696.1A CN202110611696A CN113257738B CN 113257738 B CN113257738 B CN 113257738B CN 202110611696 A CN202110611696 A CN 202110611696A CN 113257738 B CN113257738 B CN 113257738B
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metal layer
layer
insulating layer
substrate
array substrate
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CN113257738A (en
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谭芳
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Suzhou China Star Optoelectronics Technology Co Ltd
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Suzhou China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The application discloses a preparation method of an array substrate, the array substrate and a display panel, wherein a first substrate is provided, and the first substrate comprises a first metal layer, a first insulating layer, a second metal layer and a second insulating layer which are arranged in a stacked mode; openings are arranged at the positions of the second metal layer and the second insulating layer corresponding to the first metal layer, and part of the first insulating layer is leaked out; and simultaneously, preparing a third metal layer above the first substrate, wherein the third metal layer is disconnected at the opening, and meanwhile, the part of the third metal layer above the opening is also connected with the second metal layer. The disconnected second metal layer is connected through the third metal layer, so that the second metal layer is connected, and meanwhile, the problem that the second metal layer is broken at the opening is avoided.

Description

Preparation method of array substrate, array substrate and display panel
Technical Field
The application relates to the technical field of display, in particular to a preparation method of an array substrate, the array substrate and a display panel.
Background
In a traditional Thin Film Transistor Liquid Crystal Display (TFT LCD) process, due to product design requirements, when a metal wire of a source and drain metal layer passes through a gate metal layer, a climbing process needs to be performed. Influenced by the appearance of the climbing position, the leveling property of the light resistor is poor in the light resistor coating process, the light resistor at the climbing position is not completely filled, and a hole is easily formed between metal and the light resistor, so that liquid medicine permeates into the hole in the etching process to generate hole corrosion, the climbing disconnection is abnormal, and the yield of the display panel is greatly influenced.
Disclosure of Invention
The embodiment of the application provides a preparation method of an array substrate, the array substrate and a display panel, and aims to solve the problem that a display panel in the prior art is prone to climbing and wire breaking.
In a first aspect, an embodiment of the present application provides a method for manufacturing an array substrate, where the method includes:
providing a first substrate, wherein the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal layer formed on the first insulating layer and on the side away from the first metal layer, and a second insulating layer formed on the second metal layer and on the side away from the first insulating layer, and openings are formed in the second metal layer and the second insulating layer at positions corresponding to the first metal layer to expose part of the first insulating layer;
preparing a third metal layer over the first substrate, the third metal layer completely covering the second insulating layer and the opening;
etching the third metal layer to make the third metal layer disconnected at the opening, and connecting a part of the third metal layer in the opening with the second metal layer to obtain the array substrate;
wherein the opening completely covers the patterned first metal layer.
Further, the providing a first substrate, the first substrate including a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal formed on the first insulating layer at a side away from the first metal layer, and a second insulating layer formed on the second metal layer at a side away from the first insulating layer, the second metal layer and the second insulating layer being provided with openings at positions corresponding to the first metal layer to expose portions of the first insulating layer, includes:
providing a second substrate, wherein the second substrate comprises a first metal layer and a first insulating layer which are arranged in a stacking mode, the first insulating layer completely covers the first metal layer, and a bulge is formed on the first insulating layer at a position corresponding to the first metal layer;
preparing a second metal layer above the first insulating layer, wherein the second metal layer completely covers the first insulating layer;
and etching the second metal layer, and removing part of the second metal layer above the bulge to obtain a third substrate.
Further, the etching the second metal layer to remove a portion of the second metal layer located above the protrusion to obtain a third substrate includes:
coating a photoresist layer above the second metal layer, wherein the photoresist layer completely covers the second metal layer;
obtaining a first preset mask plate, so that a second metal layer on the second metal layer and positioned at the bulge is exposed;
and wet etching the photoresist layer and the second metal layer by using the first preset mask to remove a part of the second metal layer above the first metal layer, so that the opening is formed on the second metal layer to obtain a third substrate.
Further, the method further comprises:
preparing a second insulating layer over the third substrate, the second insulating layer completely covering the second metal layer;
and etching the second insulating layer, and removing part of the second insulating layer above the bulge to obtain the first substrate.
Further, the etching the second insulating layer to remove a portion of the second insulating layer located above the protrusion to obtain the first substrate includes:
coating the photoresist layer over the second insulating layer, the photoresist layer completely covering the second insulating layer;
obtaining a second preset mask plate to expose the second insulating layer on the second insulating layer at the bulge;
and dry etching the photoresist layer and the second insulating layer by using the second preset mask to remove part of the second insulating layer above the second metal layer to obtain the first substrate.
Further, the etching the third metal layer to break the third metal layer at the opening, and a portion of the third metal layer above the opening is connected to the second metal layer to obtain the array substrate, including:
utilizing a third preset mask to expose a part of the third metal layer on the third metal layer at the opening;
and removing the exposed part of the third metal layer by utilizing acid etching, so that the third metal layer is disconnected at the opening, and the part of the third metal layer positioned above the opening is connected with the first metal layer to obtain the array substrate.
In a second aspect, an embodiment of the present application provides an array substrate, including:
the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal formed on one side, away from the first metal layer, of the first insulating layer, and a second insulating layer formed on one side, away from the first insulating layer, of the second metal layer, wherein openings are formed in positions, corresponding to the first metal layer, of the second metal layer and the second insulating layer so as to expose the first insulating layer;
the third metal layer is positioned above the first substrate, the third metal layer is disconnected at the opening, and part of the third metal layer positioned in the opening is connected with the second metal layer;
wherein the opening completely covers the patterned first metal layer.
Furthermore, a part of the third metal layer located at the opening is at the same level as the second metal layer.
Further, the third metal layer is an oxide metal layer.
In a third aspect, an embodiment of the present application provides a display panel including an opposing substrate, a liquid crystal layer, and the array substrate as described in any one of the above, the opposing substrate being disposed opposite to the array substrate, the liquid crystal layer being interposed between the array substrate and the opposing substrate.
According to the preparation method of the array substrate, the array substrate and the display panel, the first substrate is provided, and the first substrate comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer which are arranged in a stacked mode; openings are arranged at the positions of the second metal layer and the second insulating layer corresponding to the first metal layer, and part of the first insulating layer is leaked out; and simultaneously, preparing a third metal layer above the first substrate, wherein the third metal layer is disconnected at the opening, and meanwhile, the part of the third metal layer above the opening is also connected with the second metal layer. The disconnected second metal layer is connected through the third metal layer, so that the second metal layer is connected, and meanwhile, the problem that the second metal layer is broken at the opening is avoided.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart illustrating an embodiment of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of an embodiment of an array substrate in the prior art;
fig. 3 is a schematic flowchart illustrating an embodiment of providing a first substrate according to the present disclosure;
fig. 4 is a schematic structural diagram of an embodiment of an array substrate after a second metal layer is prepared according to the present application;
fig. 5 is a schematic structural diagram of an embodiment of an array substrate after etching a second metal layer according to the present disclosure;
fig. 6 is a schematic structural diagram of an embodiment of an array substrate after a second insulating layer is prepared according to the present application;
FIG. 7 is a flowchart illustrating an embodiment of etching a second insulating layer according to the present disclosure;
fig. 8 is a schematic structural diagram of a display panel after etching a second insulating layer according to an embodiment of the present disclosure;
fig. 9 is a schematic flow chart illustrating one embodiment of a process for forming a third metal layer according to the present disclosure;
fig. 10 is a schematic structural diagram of an embodiment of an array substrate after a third metal layer is prepared according to the present application;
fig. 11 is a schematic structural diagram of an embodiment of an array substrate according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Embodiments of the present application provide a method for manufacturing an array substrate, an array substrate and a display panel, which are described below.
As shown in fig. 1, a schematic flow chart of an embodiment of a method for manufacturing an array substrate according to an embodiment of the present disclosure is shown, where the method for manufacturing an array substrate may include:
11. providing a first substrate, wherein the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal layer formed on the first insulating layer and deviating from one side of the first metal layer, and a second insulating layer formed on the second metal layer and deviating from one side of the first insulating layer, and openings are formed in the positions, corresponding to the first metal layer, of the second metal layer and the second insulating layer so as to expose part of the first insulating layer.
In an embodiment of the present application, the first substrate includes a structure in which a plurality of layers are stacked. Specifically, the first insulating layer is arranged above the first metal layer, and the first insulating layer completely covers the first metal layer; a protruding structure is formed on the first insulating layer at a position corresponding to the first metal layer. The second metal layer is arranged on one side, away from the first metal layer, of the first insulating layer, and the second insulating layer is arranged on one side, away from the first insulating layer, of the second metal layer; openings are formed in the second metal layer and the second insulating layer at positions corresponding to the first metal layer, so that a portion of the first insulating layer is exposed.
Fig. 2 is a schematic structural diagram of an embodiment of an array substrate in the prior art. The array substrate may include a first metal layer 201, a first insulating layer 202, a second metal layer 203, and a second insulating layer 204 stacked from bottom to top; and the first insulating layer 202 completely covers the first metal layer 201, and due to the existence of the first metal layer 201, a first protrusion is formed on the first insulating layer 202 in a region corresponding to the first metal layer 201. The side of the first protrusion is a climbing structure, i.e. the first insulating layer 202 forms a climbing structure above the first metal layer 201.
In the array substrate shown in fig. 2, the second metal layer 203 completely covers the first insulating layer 202, so that a second protrusion is formed on a region of the second metal layer 203 corresponding to the first protrusion, that is, the second metal layer 203 also forms a climbing structure above the first insulating layer 202.
A second insulating layer 204 is further formed above the second metal layer 203, and the second insulating layer 204 completely covers the second metal layer 203, so that a third protrusion is formed on a region of the second insulating layer 204 corresponding to the second protrusion, that is, the second insulating layer 204 also forms a climbing structure above the second metal layer 203.
That is, in the array substrate of the prior art shown in fig. 2, a climbing structure is formed between the first insulating layer 202 and the first metal layer 201, a climbing structure is also formed between the second metal layer 203 and the first metal layer 201, and a climbing structure is also formed between the second insulating layer 204 and the first metal layer 201. However, in the display panel provided in the embodiment of the present application, both the second metal layer 203 and the second insulating layer 204 are disconnected at the climbing structure, that is, both the second metal layer 203 and the second insulating layer 204 do not exist above the first protrusion and at the climbing structure.
12. And preparing a third metal layer above the first substrate, wherein the third metal layer completely covers the second insulating layer and the opening.
After providing the first substrate comprising the opening, the third metal layer 205 may be prepared above the first substrate, while the third metal layer 205 at this point completely covers the first substrate, i.e. the third metal layer 205 completely covers the second insulating layer 204 and the opening.
13. And etching the third metal layer to make the third metal layer disconnected at the opening, wherein part of the third metal layer positioned at the opening is connected with the second metal layer to obtain the array substrate.
After the third metal layer 205 completely covering the first substrate is prepared, the third metal layer 205 needs to be etched to remove a portion of the third metal layer 205, so that the third metal layer 205 is broken at the opening. In the embodiment of the present application, a portion of the metal layer 205 located above the opening is connected to the second metal layer 203 that needs to be disconnected, so that the second metal layer 203 disconnected at the opening is connected through the third metal layer 205, and conduction is achieved.
According to the preparation method of the array substrate provided by the embodiment of the application, the first substrate is provided, and the first substrate comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer which are stacked; openings are arranged at the positions of the second metal layer and the second insulating layer corresponding to the first metal layer, and part of the first insulating layer is leaked out; and simultaneously, preparing a third metal layer above the first substrate, wherein the third metal layer is disconnected at the opening, and meanwhile, the part of the third metal layer above the opening is also connected with the second metal layer. The disconnected second metal layer is connected through the third metal layer, so that the second metal layer is connected, and meanwhile, the problem that the second metal layer is broken at the opening is avoided.
As shown in fig. 3, for a schematic flow chart of an embodiment of providing a first substrate provided in the present application, providing a first glass substrate may include:
31. and providing a second substrate, wherein the second substrate comprises a first metal layer and a first insulating layer which are arranged in a stacking mode.
In the embodiment of the present application, a second substrate including a first metal layer 201 and a first insulating layer 202 stacked in layers may be provided, the first insulating layer 202 in the second substrate completely covers the first metal layer 201, and a first protrusion is formed on the first insulating layer 202 at a position corresponding to the first metal layer 201.
32. And preparing a second metal layer above the first insulating layer, wherein the second metal layer completely covers the first insulating layer.
In the above embodiment, it is necessary to continue to prepare the second metal layer 203 on the second substrate, i.e. to prepare the second metal layer 203 on the first insulating layer 202, and the second metal layer 203 at this time completely covers the first insulating layer 202.
As shown in fig. 4, which is a schematic structural diagram of an embodiment of the array substrate after the second metal layer is prepared according to the embodiment of the present disclosure, in the embodiment of the present disclosure, the second metal layer 203 may be prepared by a Physical Vapor Deposition (PVD) method. Specifically, the metal material forming the second metal layer 203 may be vaporized into atoms, molecules, or partially ionized into ions, and then the second metal layer 203 is deposited on the surface of the first insulating layer 202 through a low-pressure gas (or plasma) process to form the second metal layer 203, at this time, the prepared second metal layer 203 completely covers the first insulating layer 202, a second protrusion is formed on a region of the second metal layer 203 corresponding to the first protrusion, that is, a climbing structure is also formed between the second metal layer 203 and the first metal layer 201.
In other embodiments of the present application, the second metal layer 203 may also be prepared by vacuum evaporation, sputter coating, arc plasma plating, ion coating, molecular beam epitaxy, and the like, and the specific preparation process may refer to the prior art, which is not limited herein.
33. And etching the second metal layer, and removing part of the second metal layer above the protrusion to obtain a third substrate.
The second metal layer 203 prepared in step 32 completely covers the first insulating layer 202, and in the embodiment of the present application, a portion of the second metal layer above the first metal layer 201 needs to be removed, that is, a portion of the second metal layer above the first bump needs to be removed, so as to obtain a third substrate. The second metal layer is broken at the first bump, and the second metal layer forms an opening at the first bump. Fig. 5 is a schematic structural diagram of an embodiment of an array substrate after etching a second metal layer according to the embodiment of the present disclosure.
In the foregoing embodiment, performing an etching process on the second metal layer 203 to remove a portion of the second metal layer located above the protrusion to obtain the third substrate may include:
coating a photoresist layer above the second metal layer, wherein the photoresist layer completely covers the second metal layer; acquiring a first preset mask plate to expose a second metal layer positioned at the bulge on the second metal layer; and wet etching the photoresist layer and the second metal layer by using a first preset mask, and removing part of the second metal layer above the first metal layer to obtain a third substrate.
Specifically, a photoresist layer completely covering the second metal layer 203 may be coated on the second metal layer 203, and the first preset mask is disposed above the photoresist layer; and the first preset mask plate covering the photoresist layer exposes part of the photoresist layer. After the photoresist layer is exposed and developed, a part of the photoresist layer to be left is shielded by a first preset mask plate, and the other part of the exposed photoresist layer is cleaned by a developing solution; leaving the unexposed photoresist layer to form a patterned photoresist layer. And then removing the unexposed photoresist layer to obtain the final second metal layer 203.
In other embodiments of the present application, after the second metal layer is prepared, a second insulating layer 204 is also prepared over the second metal layer. Specifically, the method may include:
preparing a second insulating layer above the third substrate, wherein the second insulating layer completely covers the second electrode metal layer; and etching the second insulating layer, and removing part of the second insulating layer above the protrusion to obtain the first substrate. As shown in fig. 6, which is a schematic structural diagram of an embodiment of the array substrate after the second insulating layer is prepared according to the embodiment of the present application, at this time, the prepared second insulating layer 204 completely covers the second metal layer 203 and the first insulating layer 202.
Wherein the second insulating layer 204 can also be prepared by Physical Vapor Deposition (PVD). The specific preparation process can refer to the prior art, and is not limited herein.
As shown in fig. 7, an embodiment of a flowchart of performing an etching process on the second insulating layer according to the embodiment of the present disclosure is shown, wherein after the second insulating layer completely covering the second metal layer is prepared by a pvd method, the second insulating layer is further subjected to an etching process to remove a portion of the second insulating layer above the protrusion; the specific steps may include:
71. and coating a photoresist layer on the second insulating layer, wherein the photoresist layer completely covers the second insulating layer.
72. And obtaining a second preset mask plate, so that the second insulating layer positioned at the bulge on the second insulating layer is exposed.
73. And dry etching the photoresist layer and the second insulating layer by using a second preset mask, and removing part of the second insulating layer above the second metal layer to obtain the first substrate.
Specifically, the second insulating layer 204 prepared by using the physical vapor deposition method completely covers the second metal layer 203, and a portion of the second insulating layer 204 needs to be removed, so that the second insulating layer 204 is disconnected at the opening. Therefore, a portion of the insulating layer 204 to be removed may be exposed by using a second predetermined mask, where the portion of the insulating layer 204 to be removed includes a portion of the insulating layer 204 located above the first metal layer 201.
Since the second metal layer 203 is mainly composed of a metal material, the second metal layer can be removed by wet etching; since the second insulating layer 204 is made of an insulating material, the second insulating layer 204 can be removed by dry etching.
The dry etching is an etching mode of putting specific gas under a low-pressure state, applying voltage, exciting the specific gas into plasma, and chemically etching and bombarding ions on the specific film layer to remove the film layer. The specific process and steps for removing the portion of the insulating layer 204 by dry etching can refer to the prior art, and are not limited herein.
Fig. 8 is a schematic structural diagram of an array substrate after etching a second insulating layer according to an embodiment of the present disclosure. In the above embodiment, the second insulating layer 204 obtained after the etching process is broken at the protrusion, and the second insulating layer 204 does not exist above the first metal layer 201. That is, the second metal layer 203 and the second insulating layer 204 are not only disconnected at the first bump, but also a portion of the second metal layer corresponding to the first metal layer 201 on the second metal layer 203 is removed, and a portion of the second insulating layer corresponding to the first metal layer 201 on the second insulating layer 204 is removed; openings are formed in both the second metal layer 203 and the second insulating layer 204.
In other embodiments of the present application, it is also desirable to prepare a third metal layer 205 over the first substrate, i.e., over the second year insulating layer 204. And the third metal layer is disconnected at the opening, and part of the third metal layer above the opening is connected with the second metal layer, so that the array substrate is obtained.
As shown in fig. 9, a schematic flow chart of an embodiment of the present application for preparing a third metal layer may include:
91. and exposing a part of the third metal layer positioned at the opening on the third metal layer by using a third preset mask.
92. And removing the exposed part of the third metal layer by utilizing acid etching, so that the third metal layer is disconnected at the opening, and the part of the third metal layer positioned above the opening is connected with the second metal layer to obtain the array substrate.
Specifically, as shown in fig. 10, a schematic structural diagram of an embodiment of the array substrate after preparing the third metal layer provided in the embodiment of the present application is shown, wherein the first insulating layer 202 completely covers the first metal layer 201, and a protruding structure is formed between the first insulating layer 202 and the first metal layer 201. And the second metal layer 203 and the insulating layer 204 are disconnected at the raised structure, the portion of the second metal layer 203 corresponding to the first metal layer 201 is removed, and the portion of the second insulating layer 204 corresponding to the second metal layer 203 is also removed, so that openings are formed on both the second metal layer 203 and the second insulating layer 204. The third metal layer 205 at this time completely covers the first insulating layer 202 and the second insulating layer 204.
As shown in fig. 11, which is a schematic structural diagram of an embodiment of the array substrate provided in the present application, after the third metal layer 205 completely covering the second insulating layer 204 and the first insulating layer 202 is prepared by a pvd method, the third metal layer 205 needs to be etched, so that the third metal layer is disconnected at the opening, and a portion of the third metal layer above the opening is connected to the second metal layer.
Specifically, since the third metal layer is formed of a metal oxide, the exposed third metal layer 205 may be removed using an acidic solution. In some embodiments of the present application, a portion of the third metal layer 205 at the opening may be removed by using an oxalic acid etching method, so that the third metal layer 205 is disconnected at the opening.
Referring to fig. 11, in the above embodiment, only the third metal layer 205 located at the opening is disconnected, a portion of the third metal layer 205 located above the opening is not removed, and the disconnected second metal layer 203 is connected by using the third metal layer 205 located above the opening. The design not only connects the disconnected second metal layer 203, so that the second metal layer 203 can still realize functions; and the second metal layer 203 does not need to climb at the first bump, so that the problem of climbing and wire breaking is avoided.
The embodiment of the present application further provides an array substrate, which includes:
the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal formed on one side, away from the first metal layer, of the first insulating layer, and a second insulating layer formed on one side, away from the first insulating layer, of the second metal layer, wherein openings are formed in positions, corresponding to the first metal layer, of the second metal layer and the second insulating layer so as to expose the first insulating layer.
And the third metal layer is positioned above the insulating layer, the third metal layer is disconnected at the opening, and part of the third metal layer positioned above the opening is connected with the second metal layer.
According to the array substrate provided by the embodiment of the application, the first substrate is provided and comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer which are stacked; openings are arranged at the positions of the second metal layer and the second insulating layer corresponding to the first metal layer, and part of the first insulating layer is leaked out; and simultaneously, preparing a third metal layer above the first substrate, wherein the third metal layer is disconnected at the opening, and meanwhile, the part of the third metal layer above the opening is also connected with the second metal layer. The disconnected second metal layer is connected through the third metal layer, so that the second metal layer is connected, and meanwhile, the problem that the second metal layer is broken at the opening is avoided.
Referring to fig. 11, in the array substrate shown in fig. 10, a portion of the second metal layer 203 on the second metal layer 203 corresponding to the first metal layer 201 is removed; and a part of the insulating layer 204 on the second insulating layer 204 corresponding to the first metal layer 201 is also removed; openings are formed in both the second metal layer 203 and the second insulating layer 204.
The third metal layer 205 is disconnected at the opening, but a part of the third metal layer 205 located at the opening is connected with the second metal layer, so that the second metal layer 203 is prevented from being disconnected and the function cannot be normally realized. And because the part of the oxide metal layer 205 located at the opening is disconnected at the opening, even if the second metal layer 203 is connected with part of the third metal layer, the part of the third metal layer 205 located above the second insulating layer is not conducted with the second metal layer 203, which affects the display.
In some other embodiments of the present application, the portion of the third metal layer 205 located at the opening may be at the same level as the second metal layer 203. Meanwhile, the third metal layer 205 may be an oxide metal layer, that is, the third metal layer 205 may be formed of an oxide.
The array substrate provided by the embodiment of the present application includes the array substrate prepared by the preparation method of the array substrate described above.
An embodiment of the present application further provides a display panel, which includes an opposite substrate, a liquid crystal layer, and the array substrate as described in any of the foregoing, wherein the opposite substrate is disposed opposite to the array substrate, and the liquid crystal layer is sandwiched between the array substrate and the opposite substrate.
According to the display panel provided by the embodiment of the application, the first substrate is provided and comprises a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer which are arranged in a stacked mode; openings are arranged at the positions of the second metal layer and the second insulating layer corresponding to the first metal layer, and part of the first insulating layer is leaked out; and simultaneously, preparing a third metal layer above the first substrate, wherein the third metal layer is disconnected at the opening, and meanwhile, the part of the third metal layer above the opening is also connected with the second metal layer. The disconnected second metal layer is connected through the third metal layer, so that the second metal layer is connected, and meanwhile, the problem that the second metal layer is broken at the opening is avoided.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above detailed description is provided for the preparation method of the array substrate, the array substrate and the display panel provided in the embodiments of the present application, and a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A preparation method of an array substrate is characterized by comprising the following steps:
providing a first substrate, wherein the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal layer formed on the first insulating layer and on the side away from the first metal layer, and a second insulating layer formed on the second metal layer and on the side away from the first insulating layer, and openings are formed in the second metal layer and the second insulating layer at positions corresponding to the first metal layer to expose part of the first insulating layer;
preparing a third metal layer over the first substrate, the third metal layer completely covering the second insulating layer and the opening;
etching the third metal layer to make the third metal layer disconnected at the opening, and connecting a part of the third metal layer in the opening with the second metal layer to obtain the array substrate;
wherein the opening completely covers the patterned first metal layer.
2. The method for preparing the array substrate according to claim 1, wherein the providing a first substrate, the first substrate comprising a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal layer formed on the first insulating layer on a side facing away from the first metal layer, and a second insulating layer formed on the second metal layer on a side facing away from the first insulating layer, the second metal layer and the second insulating layer being provided with openings at positions corresponding to the first metal layer to expose portions of the first insulating layer, comprises:
providing a second substrate, wherein the second substrate comprises a first metal layer and a first insulating layer which are arranged in a stacking mode, the first insulating layer completely covers the first metal layer, and a bulge is formed on the first insulating layer at a position corresponding to the first metal layer;
preparing a second metal layer above the first insulating layer, wherein the second metal layer completely covers the first insulating layer;
and etching the second metal layer, and removing part of the second metal layer above the protrusion to obtain a third substrate.
3. The method for manufacturing the array substrate according to claim 2, wherein the etching the second metal layer to remove a portion of the second metal layer above the protrusion to obtain a third substrate includes:
coating a photoresist layer above the second metal layer, wherein the photoresist layer completely covers the second metal layer;
obtaining a first preset mask plate, so that a second metal layer on the second metal layer and positioned at the bulge is exposed;
and wet etching the photoresist layer and the second metal layer by using the first preset mask to remove a part of the second metal layer above the first metal layer, so that the opening is formed on the second metal layer to obtain the third substrate.
4. The method for preparing the array substrate according to claim 3, further comprising;
preparing a second insulating layer over the third substrate, the second insulating layer completely covering the second metal layer;
and etching the second insulating layer, and removing part of the second insulating layer above the protrusion to obtain the first substrate.
5. The method for manufacturing the array substrate according to claim 4, wherein the etching the second insulating layer to remove a portion of the second insulating layer over the protrusion to obtain the first substrate comprises:
coating the photoresist layer over the second insulating layer, the photoresist layer completely covering the second insulating layer;
obtaining a second preset mask plate to expose the second insulating layer on the second insulating layer at the bulge;
and dry etching the photoresist layer and the second insulating layer by using the second preset mask to remove part of the second insulating layer above the second metal layer to obtain the first substrate.
6. The method for manufacturing the array substrate according to claim 3, wherein the etching the third metal layer to make the third metal layer disconnected at the opening, and a portion of the third metal layer above the opening is connected to the second metal layer to obtain the array substrate, includes:
utilizing a third preset mask to expose a part of the third metal layer on the third metal layer at the opening;
and removing the exposed part of the third metal layer by utilizing acid etching, so that the third metal layer is disconnected at the opening, and the part of the third metal layer positioned above the opening is connected with the second metal layer to obtain the array substrate.
7. An array substrate, comprising:
the first substrate comprises a patterned first metal layer, a first insulating layer formed on the first metal layer, a second metal layer formed on one side, away from the first metal layer, of the first insulating layer, and a second insulating layer formed on one side, away from the first insulating layer, of the second metal layer, wherein openings are formed in positions, corresponding to the first metal layer, of the second metal layer and the second insulating layer so as to expose the first insulating layer;
the third metal layer is positioned above the first substrate, the third metal layer is disconnected at the opening, and part of the third metal layer positioned in the opening is connected with the second metal layer;
wherein the opening completely covers the patterned first metal layer.
8. The array substrate of claim 7, wherein a portion of the third metal layer at the opening is at the same level as the second metal layer.
9. The array substrate of claim 7, wherein the third metal layer is an oxide metal layer.
10. A display panel comprising an opposing substrate, a liquid crystal layer, and the array substrate according to any one of claims 7 to 9, wherein the opposing substrate is disposed opposite to the array substrate, and the liquid crystal layer is interposed between the array substrate and the opposing substrate.
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