CN108666265A - A kind of thin film transistor base plate and preparation method thereof - Google Patents
A kind of thin film transistor base plate and preparation method thereof Download PDFInfo
- Publication number
- CN108666265A CN108666265A CN201810344736.9A CN201810344736A CN108666265A CN 108666265 A CN108666265 A CN 108666265A CN 201810344736 A CN201810344736 A CN 201810344736A CN 108666265 A CN108666265 A CN 108666265A
- Authority
- CN
- China
- Prior art keywords
- metal layer
- layer
- metal
- groove
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Abstract
The present invention provides a kind of preparation method of thin film transistor base plate, including provides a underlay substrate；Insulating layer is formed in the upper surface of underlay substrate, and offers an at least groove on the insulating layer；The first metal layer is set to the upper surface of insulating layer and its corresponding each groove, and by etching so that being formed with the first metal layer in each groove；Second metal layer is set to the upper surface of insulating layer and the first metal layer, and by etching so that the top of the first metal layer in each groove is covered with second metal layer accordingly.Implement the present invention, the primary battery Structure Phenomenon formed when being avoided that using wet etching, to reduce the probability that the bad phenomenons such as undercutting or fracture occur.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of thin film transistor base plate and preparation method thereof.
Background technology
Liquid crystal display panel obtains extensively in daily life because of many merits such as, power saving thin with fuselage, radiationless
Using, such as TV, computer, mobile phone display screen.Liquid crystal display panel includes two plate bases（Such as color membrane substrates and thin film transistor (TFT)
（TFT）Substrate）And it is clamped in the liquid crystal layer between two plate bases, it is controlled by applying driving voltage on two plate bases
The different rotary of liquid crystal molecule in liquid crystal layer, the light to reflect form different pictures.
It is provided in general, can be equipped with to provide the grid line of Gate signals to TFT gate and drain to IFT in TFT substrate
The data line of Date signals；Wherein, grid line and data line can using double-layer structure or multilayered structure come provide conductive capability with
And reduce the risk of fracture.However, in existing TFT substrate, either in the grid wire forming proces of bilayer or multilayer structure,
Or can occur undercut phenomenon or phenomenon of rupture between the layers in the data wire forming proces of bilayer or multilayer structure, it is main
Reason is wanted to be：When carrying out wet etching to upper layer and lower layer metal using mask, because double layer of metal is in etching solution, photo resistive removing liquor
And there are different potential differences in rinsing solution, generate chemical reaction to form primary battery Structure Phenomenon, lead to activity
Higher metal is spent to be corroded.
Therefore, it is urgent to provide a kind of TFT substrate, the primary battery Structure Phenomenon formed when being avoided that using wet etching is used
To reduce the probability that the bad phenomenons such as undercutting or fracture occur.
Invention content
Technical problem to be solved of the embodiment of the present invention is, provides a kind of thin film transistor base plate and its preparation side
To reduce the bad phenomenons such as undercutting or fracture occur for method, the primary battery Structure Phenomenon formed when being avoided that using wet etching
Probability.
In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a kind of preparation method of thin film transistor base plate,
Include the following steps：
Step S1, one underlay substrate is provided；
Step S2, insulating layer is formed in the upper surface of the underlay substrate, and offers an at least groove on the insulating layer；
Step S3, the first metal layer is set to the upper surface of the insulating layer and its corresponding each groove, and pass through etching
So that being formed with the first metal layer in each groove；
Step S4, second metal layer is set to the upper surface of the insulating layer and the first metal layer, and made by etching
The top for obtaining the first metal layer in each groove is covered with the second metal layer accordingly.
Wherein, the step S2 is specifically included：
It smears in the upper surface of the underlay substrate by chemical vapour deposition technique CVD and covers one layer of inorganic material and form insulation
Layer, and after smearing a layer photoresist above the insulating layer, the photoetching of the insulating layer is made by using translucent light shield
Glue pattern turns to required photoresist pattern, and further by dry etching process to corresponding to the photoresist figure on the insulating layer
The region not being covered by photoresist in case is etched so that an at least groove is formed on the insulating layer；
Continue to remove the photoresist corresponding to region of the insulating layer in addition to each groove using dry etching process.
Wherein, the step S3 is specifically included：
By physical vaporous deposition PVD the is formed in the upper surface jet-plating metallization of the insulating layer and its corresponding each groove
One metal layer, and by the first metal layer smear photoresist after, using yellow light processing procedure to the first metal layer
Photoresist is exposed to form required photoresist pattern；Wherein, the region being covered by photoresist on the first metal layer and institute
Each groove is stated to correspond；
The region not being covered by photoresist on the first metal layer is etched by acid solution, is further continued for using alkalinity
Solution removes the photoresist on the first metal layer region corresponding with each groove so that shape in each groove
At there is the first metal layer；Or
The region not being covered by photoresist on the first metal layer is etched by dry etching process, is further continued for dry method
Etch process removes the photoresist on the first metal layer region corresponding with each groove so that each groove
In be formed with the first metal layer.
Wherein, the step S4 is specifically included：
By physical vaporous deposition PVD second is formed in the upper surface jet-plating metallization of the insulating layer and the first metal layer
Metal layer, and by the second metal layer smear photoresist after, using yellow light processing procedure to the light of the second metal layer
Photoresist is exposed to form required photoresist pattern；Wherein, the region being covered by photoresist in the second metal layer with it is described
The first metal layer in each groove corresponds, and the area in the region being covered by photoresist in the second metal layer is uniform
One corresponds to the area for covering the first metal layer in each groove；
The region not being covered by photoresist in the second metal layer is etched by acid solution, is further continued for using alkalinity
Solution removes the photoresist on second metal layer region corresponding with each groove so that in each groove
The top of the first metal layer is covered with the second metal layer accordingly.
Wherein, the first metal layer is single layer structure or multilayered structure；The second metal layer is single layer structure or more
Layer structure.
Wherein, the first metal layer is single layer structure, and the metal of sputter is Cu or Al；The second metal layer is single
The metal of layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is single layer structure, and the metal of sputter is Cu or Al；The second metal layer is double-layer structure,
The metal of sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
The embodiment of the present invention additionally provides a kind of thin film transistor base plate, including：
Underlay substrate；
The insulating layer being set on the underlay substrate is formed with an at least groove on the insulating layer；
The first metal layer being set in each groove；And
The second metal layer being covered in accordingly above the first metal layer in each groove.
Wherein, the insulating layer is by its a kind of single layer structure being prepared among SiOx, SiNx, SiNO；Or by
The laminated construction that SiNx/SiOx is prepared.
Wherein, the first metal layer is single layer structure or multilayered structure；The second metal layer is single layer structure or more
Layer structure.
Wherein, the first metal layer is single layer structure, and the metal of sputter is Cu or Al；The second metal layer is single
The metal of layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is single layer structure, and the metal of sputter is Cu or Al；The second metal layer is double-layer structure,
The metal of sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
Implement the embodiment of the present invention, has the advantages that：
Compared with traditional thin film transistor base plate, the present invention in thin film transistor base plate in preparation process, by the first metal
Prepared by layer and second metal layer substep, and because second metal layer is covered in above the first metal layer so that using wet
When method etches, the first metal layer and second metal layer will not exist simultaneously in etching solution, photo resistive removing liquor and rinsing solution, from
And the primary battery Structure Phenomenon formed when can avoid using wet etching, prevent the first metal layer or second metal layer rotten
Erosion, to reduce the probability that the bad phenomenons such as undercutting or fracture occur.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, according to
These attached drawings obtain other attached drawings and still fall within scope of the invention.
Fig. 1 is the flow chart of the preparation method of the thin film transistor base plate provided in the embodiment of the present invention one；
Fig. 2 is the application scenario diagram of the preparation method of the thin film transistor base plate provided in the embodiment of the present invention one；
Fig. 3 is the sectional view of thin film transistor base plate in the embodiment of the present invention two.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, the present invention is made into one below in conjunction with attached drawing
Step ground detailed description.
As shown in Figure 1, in the embodiment of the present invention one, a kind of preparation method of the thin film transistor base plate provided, including
Following steps：
Step S1, one underlay substrate is provided；
Step S2, insulating layer is formed in the upper surface of the underlay substrate, and offers an at least groove on the insulating layer；
Step S3, the first metal layer is set to the upper surface of the insulating layer and its corresponding each groove, and pass through etching
So that being formed with the first metal layer in each groove；
Step S4, second metal layer is set to the upper surface of the insulating layer and the first metal layer, and made by etching
The top for obtaining the first metal layer in each groove is covered with the second metal layer accordingly.
It should be noted that because the second metal layer in the first metal layer and step S4 in step S3 is using substep progress
When preparing, and preparing second metal layer in step s 4, second metal layer is covered in the top of the first metal layer so that wet method
The first metal layer and second metal layer will not exist simultaneously etching liquid, photo resistive removing liquor and rinsing solution when etching（Such as acidity
Solution and alkaline solution）In, to avoid the occurrence of primary battery Structure Phenomenon, prevent the first metal layer or second metal layer rotten
Erosion, to reduce the probability that the bad phenomenons such as undercutting or fracture occur.
It is understood that being located at the first metal layer and the second gold medal prepared on each groove on thin film transistor base plate
Belong to the grid line that layer can be formed as thin film transistor base plate, the data line of thin film transistor base plate can also be formed as, specifically
Function can be designed according to actual requirement.
The preparation method of thin film transistor base plate in the embodiment of the present invention one, detailed process are：
In step sl, a underlay substrate being prepared by quartz, glass or transparent plastic is provided.
In step s 2, it smears in the upper surface of underlay substrate by CVD and covers one layer of inorganic material and form insulating layer,
And on the insulating layer after one layer photoresist of side's smearing, by using translucent light shield（Such as gray-level mask or halftone mask）So that
The photoetching offset plate figure of insulating layer turns to required photoresist pattern, and further passes through dry etching process（Such as use etching gas
SF6, Cl2, CF4, Ar and NF3 etc.）It is etched, makes to corresponding to the region not being covered by photoresist in photoresist pattern on insulating layer
It obtains and is formed with an at least groove on insulating layer；
Continue to use dry etching process（Such as use oxidizing gas O2 and N2O）Insulating layer is removed in addition to each groove
Photoresist corresponding to region.
It should be noted that inorganic material used by insulating layer includes iOx, SiNx, SiNO etc..In one embodiment
In, insulating layer is by its a kind of single layer structure being prepared among SiOx, SiNx, SiNO；Or it is prepared by SiNx/SiOx
Laminated construction.
In step s3, by PVD first is formed in the upper surface jet-plating metallization of insulating layer and its corresponding each groove
Metal layer, and by smearing photoresist on the first metal layer after, using yellow light processing procedure（Such as use transparent light shield）To the first gold medal
The photoresist for belonging to layer is exposed to form required photoresist pattern；Wherein, the region that is covered by photoresist on the first metal layer with
Each groove corresponds；
At this point, wet etching processing procedure may be used to the first metal layer, dry etching processing procedure can also be used：
（1）Wet etching processing procedure：Pass through acid solution（Such as PPC acid, ENF acid, oxalic acid）To not being photo-etched on the first metal layer
The region of glue covering is etched, and is further continued for using alkaline solution（Such as NaOH）Remove the first metal layer with it is described each recessed
Photoresist on the corresponding region of slot so that be formed with the first metal layer in each groove；
（2）Dry etching processing procedure：Pass through dry etching process（Such as use etching gas SF6, Cl2, CF4, Ar and NF3）To
The region not being covered by photoresist on one metal layer is etched, and is further continued for dry etching process（Such as use etching gas SF6,
Cl2, CF4, Ar and NF3 etc.）Remove the photoresist on the first metal layer region corresponding with each groove so that in each groove
It is formed with the first metal layer.
It is understood that since making technology is there are error, then the first metal layer can be full of in each groove and its
Periphery, but actual design requirement should be met.
In step s 4, second metal layer is formed in the upper surface jet-plating metallization of insulating layer and the first metal layer by PVD,
And by second metal layer smear photoresist after, using yellow light processing procedure（Such as use transparent light shield）To the light of second metal layer
Photoresist is exposed to form required photoresist pattern；Wherein, the region being covered by photoresist in second metal layer and each groove
In the first metal layer correspond, and the area in the region being covered by photoresist in second metal layer is corresponded and is covered
The area of the first metal layer in each groove, during thus can using wet etching processing procedure to avoid second metal layer,
The first metal layer and second metal layer simultaneously contact etching liquid, photo resistive removing liquor and rinsing solution and because there are potential differences to be formed
Primary battery Structure Phenomenon causes the first metal layer or second metal layer to be corroded and generates the risk of undercutting or fracture；
Because second metal layer covers the first metal layer, pass through acid solution at this time（Such as PPC acid, ENF acid, oxalic acid）To second
The region not being covered by photoresist on metal layer is etched, and is further continued for using alkaline solution（Such as NaOH）Remove the second gold medal
Belong to layer to cover to get to the top of the first metal layer in each groove is corresponding with the photoresist on the corresponding region of each groove
It is stamped second metal layer.
In the embodiment of the present invention one, the first metal layer is single layer structure or multilayered structure；Second metal layer is single layer structure
Or multilayered structure.
In one embodiment, the first metal layer is single layer structure, and the metal of sputter is Cu or Al；Second metal layer is
The metal of single layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn.
In another embodiment, the first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The
Two metal layers are single layer structure, and the metal of sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn.
In yet another embodiment, the first metal layer is single layer structure, and the metal of sputter is Cu or Al；Second metal layer
Metal for double-layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
In yet another embodiment, the first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The
Two metal layers are single layer structure, and the metal of sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
As shown in Fig. 2, the application scenario diagram of the preparation method for the thin film transistor base plate in the embodiment of the present invention one；Its
In, 1- underlay substrates, 2- insulating layers, 21- grooves, 3- the first metal layers, 4- second metal layers, 5- photoresists.
In Fig. 2 a, corresponding step S2 prepares insulating layer and its corresponding groove；In Fig. 2 b, corresponding step S3 is prepared often
It is formed with the first metal layer in one groove, which is formed by Ni metal；In Fig. 2 c, in corresponding step S4, by metal
The photoetching offset plate figure above second metal layer that Mo is formed is melted into photoresist pattern so that is covered by photoresist in second metal layer
Region is corresponded with the first metal layer in each groove, and the area in the region being covered by photoresist in second metal layer is equal
Correspond the area for covering the first metal layer in each groove；In figure 2d, corresponding step S4 prepares each groove
In the top of the first metal layer be covered with second metal layer accordingly.
As shown in figure 3, in the embodiment of the present invention two, a kind of thin film transistor base plate provided, including：
Underlay substrate 1；
The insulating layer 2 being set on underlay substrate 1 is formed with an at least groove 21 on the insulating layer 2；
The first metal layer 3 being set in each groove 21；And
It is covered in the second metal layer 4 of 3 top of the first metal layer in each groove 21 accordingly.
Wherein, insulating layer 2 is by its a kind of single layer structure being prepared among SiOx, SiNx, SiNO；Or by SiNx/
The laminated construction that SiOx is prepared.
Wherein, the first metal layer 3 is single layer structure or multilayered structure；Second metal layer 4 is single layer structure or multilayered structure.
Wherein, the first metal layer 3 is single layer structure, and the metal of sputter is Cu or Al；Second metal layer 4 is single layer knot
The metal of structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn..
Wherein, the first metal layer 3 is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；Second metal layer 4 is
The metal of single layer structure, sputter is its a kind of among Mo, Nb, Ni, Nb, Ta, Mn
Wherein, the first metal layer 3 is single layer structure, and the metal of sputter is Cu or Al；Second metal layer 4 is double-layer structure,
The metal of sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
Wherein, the first metal layer 3 is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；Second metal layer 4 is
The metal of single layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
Implement the embodiment of the present invention, has the advantages that：
Compared with traditional thin film transistor base plate, the present invention in thin film transistor base plate in preparation process, by the first metal
Prepared by layer and second metal layer substep, and because second metal layer is covered in above the first metal layer so that using wet
When method etches, the first metal layer and second metal layer will not exist simultaneously in etching solution, photo resistive removing liquor and rinsing solution, from
And the primary battery Structure Phenomenon formed when can avoid using wet etching, prevent the first metal layer or second metal layer rotten
Erosion, to reduce the probability that the bad phenomenons such as undercutting or fracture occur.
It is above disclosed to be only a preferred embodiment of the present invention, the power of the present invention cannot be limited with this certainly
Sharp range, therefore equivalent changes made in accordance with the claims of the present invention, are still within the scope of the present invention.
Claims (10)
1. a kind of preparation method of thin film transistor base plate, which is characterized in that include the following steps：
Step S1, one underlay substrate is provided；
Step S2, insulating layer is formed in the upper surface of the underlay substrate, and offers an at least groove on the insulating layer；
Step S3, the first metal layer is set to the upper surface of the insulating layer and its corresponding each groove, and pass through etching
So that being formed with the first metal layer in each groove；
Step S4, second metal layer is set to the upper surface of the insulating layer and the first metal layer, and made by etching
The top for obtaining the first metal layer in each groove is covered with the second metal layer accordingly.
2. the preparation method of thin film transistor base plate as described in claim 1, which is characterized in that the step S2 is specifically wrapped
It includes：
It smears in the upper surface of the underlay substrate by chemical vapour deposition technique CVD and covers one layer of inorganic material and form insulation
Layer, and after smearing a layer photoresist above the insulating layer, the photoetching of the insulating layer is made by using translucent light shield
Glue pattern turns to required photoresist pattern, and further by dry etching process to corresponding to the photoresist figure on the insulating layer
The region not being covered by photoresist in case is etched so that an at least groove is formed on the insulating layer；
Continue to remove the photoresist corresponding to region of the insulating layer in addition to each groove using dry etching process.
3. the preparation method of thin film transistor base plate as described in claim 1, which is characterized in that the step S3 is specifically wrapped
It includes：
By physical vaporous deposition PVD the is formed in the upper surface jet-plating metallization of the insulating layer and its corresponding each groove
One metal layer, and by the first metal layer smear photoresist after, using yellow light processing procedure to the first metal layer
Photoresist is exposed to form required photoresist pattern；Wherein, the region being covered by photoresist on the first metal layer and institute
Each groove is stated to correspond；
The region not being covered by photoresist on the first metal layer is etched by acid solution, is further continued for using alkalinity
Solution removes the photoresist on the first metal layer region corresponding with each groove so that shape in each groove
At there is the first metal layer；Or
The region not being covered by photoresist on the first metal layer is etched by dry etching process, is further continued for dry method
Etch process removes the photoresist on the first metal layer region corresponding with each groove so that each groove
In be formed with the first metal layer.
4. the preparation method of thin film transistor base plate as described in claim 1, which is characterized in that the step S4 is specifically wrapped
It includes：
By physical vaporous deposition PVD second is formed in the upper surface jet-plating metallization of the insulating layer and the first metal layer
Metal layer, and by the second metal layer smear photoresist after, using yellow light processing procedure to the light of the second metal layer
Photoresist is exposed to form required photoresist pattern；Wherein, the region being covered by photoresist in the second metal layer with it is described
The first metal layer in each groove corresponds, and the area in the region being covered by photoresist in the second metal layer is uniform
One corresponds to the area for covering the first metal layer in each groove；
The region not being covered by photoresist in the second metal layer is etched by acid solution, is further continued for using alkalinity
Solution removes the photoresist on second metal layer region corresponding with each groove so that in each groove
The top of the first metal layer is covered with the second metal layer accordingly.
5. the preparation method of the thin film transistor base plate as described in any one of claim 1-4, which is characterized in that described first
Metal layer is single layer structure or multilayered structure；The second metal layer is single layer structure or multilayered structure.
6. the preparation method of thin film transistor base plate as claimed in claim 5, which is characterized in that the first metal layer is single
The metal of layer structure, sputter is Cu or Al；The second metal layer is single layer structure, the metal of sputter is Mo, Nb, Ni,
It is a kind of among Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is single layer structure, and the metal of sputter is Cu or Al；The second metal layer is double-layer structure,
The metal of sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer is double-layer structure, and the metal of sputter is Cu and two kinds of superpositions of Al；The second metal layer is single
The metal of layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
7. a kind of thin film transistor base plate, which is characterized in that including：
Underlay substrate（1）；
It is set to the underlay substrate（1）On insulating layer（2）, the insulating layer（2）On be formed with an at least groove（21）；
It is set to each groove（21）In the first metal layer（3）；And
It is covered in each groove accordingly（21）In the first metal layer（3）The second metal layer of top（4）.
8. thin film transistor base plate as claimed in claim 7, which is characterized in that the insulating layer（2）For by SiOx, SiNx,
Its a kind of single layer structure being prepared among SiNO；Or the laminated construction being prepared by SiNx/SiOx.
9. thin film transistor base plate as claimed in claim 8, which is characterized in that the first metal layer（3）For single layer structure
Or multilayered structure；The second metal layer（4）For single layer structure or multilayered structure.
10. thin film transistor base plate as claimed in claim 9, which is characterized in that the first metal layer（3）For single layer knot
The metal of structure, sputter is Cu or Al；The second metal layer（4）For single layer structure, the metal of sputter is Mo, Nb, Ni,
It is a kind of among Nb, Ta, Mn；Or
The first metal layer（3）Metal for double-layer structure, sputter is Cu and two kinds of superpositions of Al；The second metal layer
（4）Metal for single layer structure, sputter is its one kind among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer（3）Metal for single layer structure, sputter is Cu or Al；The second metal layer（4）For bilayer
The metal of structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn；Or
The first metal layer（3）Metal for double-layer structure, sputter is Cu and two kinds of superpositions of Al；The second metal layer
（4）Metal for single layer structure, sputter is its two kinds superpositions among Mo, Nb, Ni, Nb, Ta, Mn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810344736.9A CN108666265B (en) | 2018-04-17 | 2018-04-17 | Thin film transistor substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810344736.9A CN108666265B (en) | 2018-04-17 | 2018-04-17 | Thin film transistor substrate and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108666265A true CN108666265A (en) | 2018-10-16 |
| CN108666265B CN108666265B (en) | 2021-01-15 |
Family
ID=63783580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810344736.9A Active CN108666265B (en) | 2018-04-17 | 2018-04-17 | Thin film transistor substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108666265B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211874A (en) * | 2019-05-13 | 2019-09-06 | 深圳市华星光电半导体显示技术有限公司 | The preparation method and thin film transistor (TFT) of thin film transistor (TFT) |
| CN111916463A (en) * | 2020-08-20 | 2020-11-10 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183308A (en) * | 1998-12-15 | 2000-06-30 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US20020058401A1 (en) * | 1997-12-26 | 2002-05-16 | Lg Semicon Co., Ltd. | Metal line of semiconductor device and method for fabricating the same |
| US20120112309A1 (en) * | 2009-01-12 | 2012-05-10 | International Business Machines Corporation | Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| CN105637649A (en) * | 2013-10-15 | 2016-06-01 | 原子能和代替能源委员会 | Method for producing a photovoltaic cell |
| CN106356380A (en) * | 2016-11-11 | 2017-01-25 | 深圳市华星光电技术有限公司 | Flexible TFT base plate and production method thereof |
| CN107026121A (en) * | 2017-05-17 | 2017-08-08 | 京东方科技集团股份有限公司 | Preparation method, array base palte and the display device of array base palte |
| CN107482021A (en) * | 2017-08-21 | 2017-12-15 | 京东方科技集团股份有限公司 | Array base palte and display device |
-
2018
- 2018-04-17 CN CN201810344736.9A patent/CN108666265B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020058401A1 (en) * | 1997-12-26 | 2002-05-16 | Lg Semicon Co., Ltd. | Metal line of semiconductor device and method for fabricating the same |
| JP2000183308A (en) * | 1998-12-15 | 2000-06-30 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US20120112309A1 (en) * | 2009-01-12 | 2012-05-10 | International Business Machines Corporation | Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| CN105637649A (en) * | 2013-10-15 | 2016-06-01 | 原子能和代替能源委员会 | Method for producing a photovoltaic cell |
| CN106356380A (en) * | 2016-11-11 | 2017-01-25 | 深圳市华星光电技术有限公司 | Flexible TFT base plate and production method thereof |
| CN107026121A (en) * | 2017-05-17 | 2017-08-08 | 京东方科技集团股份有限公司 | Preparation method, array base palte and the display device of array base palte |
| CN107482021A (en) * | 2017-08-21 | 2017-12-15 | 京东方科技集团股份有限公司 | Array base palte and display device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211874A (en) * | 2019-05-13 | 2019-09-06 | 深圳市华星光电半导体显示技术有限公司 | The preparation method and thin film transistor (TFT) of thin film transistor (TFT) |
| CN111916463A (en) * | 2020-08-20 | 2020-11-10 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN111916463B (en) * | 2020-08-20 | 2023-03-24 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108666265B (en) | 2021-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8735976B2 (en) | TFT-LCD array substrate | |
| KR101154488B1 (en) | Tft-lcd array substrate and manufacturing method thereof | |
| KR100865451B1 (en) | TFT LCD pixel unit and manufacturing method thereof | |
| JP5804538B2 (en) | Method of forming burr at edge of photoresist and method of manufacturing array substrate | |
| US8497966B2 (en) | FFS type TFT-LCD array substrate and manufacturing method thereof | |
| US8633066B2 (en) | Thin film transistor with reduced edge slope angle, array substrate and having the thin film transistor and manufacturing method thereof | |
| JP4486554B2 (en) | LIQUID CRYSTAL DISPLAY DEVICE USING LOW MOLECULAR ORGANIC SEMICONDUCTOR MATERIAL AND ITS MANUFACTURING METHOD | |
| CN101825815B (en) | TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) array baseplate and manufacturing method thereof | |
| US20070272926A1 (en) | Tft lcd array substrate and manufacturing method thereof | |
| KR101212554B1 (en) | TFT-LCD array substrate and manufacturing method thereof | |
| US10381382B2 (en) | Array substrate, method for manufacturing the same and display device | |
| US10504943B2 (en) | Method for manufacturing an array substrate motherboard | |
| US20140273362A1 (en) | Method for manufacturing thin film transistor and array substrate | |
| WO2017012306A1 (en) | Method for manufacturing array substrate, array substrate, and display device | |
| WO2015096312A1 (en) | Array substrate and manufacturing method thereof, and display device | |
| US7256076B2 (en) | Manufacturing method of liquid crystal display device | |
| CN103489874B (en) | Array base palte and preparation method thereof, display unit | |
| JP2001221992A (en) | Method of manufacturing fringe field-drive liquid crystal display device | |
| US9716117B2 (en) | Method for producing a via, a method for producing an array substrate, an array substrate, and a display device | |
| US9659975B2 (en) | Fabrication methods of transparent conductive electrode and array substrate | |
| CN108666265A (en) | A kind of thin film transistor base plate and preparation method thereof | |
| CN105446037B (en) | Display base plate and preparation method thereof, display device | |
| CN109037241B (en) | LTPS array substrate, manufacturing method thereof and display panel | |
| US10497724B2 (en) | Manufacturing method of a thin film transistor and manufacturing method of an array substrate | |
| CN102655114B (en) | Manufacturing method for TFT-LCD (thin film transistor-liquid crystal display) array substrate, as well as array substrate and related devices thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Applicant after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |