CN113224013A - 半导体装置封装和其制造方法 - Google Patents
半导体装置封装和其制造方法 Download PDFInfo
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- CN113224013A CN113224013A CN202110074534.9A CN202110074534A CN113224013A CN 113224013 A CN113224013 A CN 113224013A CN 202110074534 A CN202110074534 A CN 202110074534A CN 113224013 A CN113224013 A CN 113224013A
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Abstract
提供了一种半导体装置封装和其制造方法。所述半导体装置封装包含第一半导体元件、第一重布层、第二重布层和导电通孔。所述第一半导体元件具有第一主动表面和与所述第一主动表面相对的第一背面。所述第一重布层安置在所述第一半导体元件的所述第一背面附近。所述第二重布层安置在所述第一半导体元件的所述第一主动表面附近。所述导电通孔安置在所述第一重布层与所述第二重布层之间,其中所述导电通孔从所述第二重布层到所述第一重布层向内倾斜。
Description
技术领域
本公开涉及一种半导体装置封装和其制造方法,并且更具体地涉及可以提高电连接的信号传输速度的半导体装置封装。
背景技术
如今,正逐步开发用于将一个以上半导体元件结合到单个半导体封装中以最小化封装尺寸的技术。倒装芯片接合技术是一种将一个半导体元件堆叠到另一个半导体元件上并且将所述半导体元件电连接的方法。通常,倒装芯片接合需要焊料电连接。然而,将焊料用于电连接可能不可避免地引起RC延迟问题,这可能降低信号传输速度。此外,在焊接材料与其它金属之间可能形成金属互化物(IMC),这还可能使导电性变差。
鉴于上述内容,期望提供具有电连接的半导体封装,所述电连接提供更快的传输速度并且同时满足小型化的工业需求。
发明内容
一方面,一种半导体装置封装包含第一半导体元件、第一重布层、第二重布层和导电通孔。所述第一半导体元件具有第一主动表面和与所述第一主动表面相对的第一背面。所述第一重布层安置在所述第一半导体元件的所述第一背面附近。所述第二重布层安置在所述第一半导体元件的所述第一主动表面附近。所述导电通孔安置在所述第一重布层与所述第二重布层之间,其中所述导电通孔从所述第二重布层到所述第一重布层向内倾斜。
一方面,一种半导体装置封装包含第一半导体元件、第一重布层、第二重布层和第二半导体元件。所述第一半导体元件具有第一主动表面和与所述第一主动表面相对的第一背面。所述第一重布层安置在所述第一半导体元件的所述第一背面附近。所述第二重布层安置在所述第一半导体元件的所述第一主动表面附近。所述第二半导体元件具有第二主动表面和与所述第二主动表面相对的第二背面,其中所述第二主动表面直接接合到所述第一重布层。
一方面,一种制造半导体装置封装的方法包含:提供第一半导体元件,所述第一半导体元件具有第一主动表面和与所述第一主动表面相对的第一背面;在所述第一半导体元件的所述第一主动表面附近安置第一重布层;在所述第一重布层附近安置第二半导体元件,其中所述第二半导体元件具有第二有主动表面和与所述第二主动表面相对的第二背面,并且所述第二背面面对所述第一重布层;模制所述第二半导体元件以形成围绕所述第二半导体元件的第一密封料;在所述第一密封料中形成导电通孔;以及在所述第二半导体元件的所述第二主动表面附近安置第二重布层。
附图说明
图1A展示了根据本公开的一些实施例的半导体装置封装的截面视图。
图1B展示了根据本公开的一些实施例的图1A所展示的半导体装置封装的区域A的放大视图。
图1C展示了根据本公开的一些实施例的图1A的半导体装置封装的区域A的放大视图。
图1D展示了根据本公开的一些实施例的图1A的半导体装置封装的区域A的放大视图。
图2A展示了根据本公开的一些实施例的图1A的半导体装置封装的区域B的放大视图。
图2B展示了根据本公开的一些实施例的图1A的半导体装置封装的区域B的放大视图。
截面图3展示了根据本公开的一些实施例的半导体装置封装的截面视图。
图4展示了根据本公开的一些实施例的半导体装置封装的截面视图。
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H、图5I、图5J、图5K、图5L、图5M、图5N、图5O、图5P和图5Q展示了制造如图1A的半导体装置封装等半导体装置封装的方法。
图6A、图6B、图6C、图6D、图6E、图6F、图6G、图6H、图6I、图6J、图6K、图6L、图6M、图6N和图6O展示了制造如图3的半导体装置封装等半导体装置封装的方法。
具体实施方式
除非另有说明,否则如“上方”、“顶部”和“底部”等空间描述是关于附图所示朝向而指示的。应当理解,本文所使用的空间描述仅仅是出于说明的目的,并且本文所描述的结构的实际实施方案可以在空间上以任何朝向或方式布置,条件是此类布置不偏离本公开的实施例的优点。
在一些实施例中,本公开提供了一种半导体装置封装,所述半导体装置封装包含第一半导体元件、第一重布层、第二重布层和导电通孔。导电通孔安置在第一重布层与第二重布层之间,因此电信号可以从第一重布层的一侧传输到第二重布层的另一侧。另外,由于导电通孔是通过激光钻孔技术或机械钻孔技术以及随后的镀覆技术形成的,因此与通过拾取和放置(picking and placing)预成型导电通孔安置的导电通孔相比,所述导电通孔可以具有更高的纵横比(aspect ratio),这进而可以产生更大数量的电连接(即,更高的I/O数),因为与传统的导电通孔相比,所述导电通孔需要的表面积更小。
在一些实施例中,本公开提供了一种半导体装置封装,所述半导体装置封装包含第一半导体元件、第一重布层、第二重布层和第二半导体元件。所述第二半导体元件具有第二主动表面和与所述第二主动表面相对的第二背面,其中所述第二主动表面直接接合到所述第一重布层。通过本公开中提供的技术,将第二半导体元件直接接合到第一重布层成为可能,并且无焊料倒装芯片技术也是。因此,根据本公开的半导体装置封装,可以实现倒装芯片技术的优良优势(包含更高的I/O数、实现进一步改善的优良散热效果和灵活性以及减小封装大小)以及无焊料技术的优势(包含减少焊料污染可能性)。
图1A展示了根据本公开的一些实施例的半导体装置封装的截面视图。图1A的半导体装置封装100包含第一半导体元件101、第一重布层(redistribution layer)103、第二重布层105和导电通孔107。
第一半导体元件101具有第一主动表面101a和与第一主动表面101a相对的第一背面101b。第一半导体元件101可以是管芯(die)、芯片(chip)、封装(package)、***件(interposer)或其组合。在一些实施例中,第一半导体元件101是管芯。可以在第一半导体元件101的第一主动表面101a附近安置至少一个第一导电端子102a以实现外部电连接。
第一重布层(RDL)103安置在第一半导体元件101的第一背面101b附近。在一些实施例中,第一RDL 103安置在(例如,物理接触)第一半导体元件101的第一背面101b上。第一RDL 103可以包含单个层,所述单个层含有介电层和安置在其上(或嵌入其中)的至少一条导电迹线,或者可以包含多个层,所述多个层具有堆叠在一起的多个介电层,其中每个层均具有安置在其上(或嵌入其中)以将电信号重新分配给外部电连接器或另一个RDL的至少一条导电迹线。在一些实施例(如图1A所展示的实施例)中,第一RDL 103包含第一底部RDL103a、第一中间RDL 103b和第一顶部RDL 103c,所述第一底部RDL103a、第一中间RDL103b和第一顶部RDL103c可以包含彼此竖直电连接的导电迹线的一部分、彼此水平电连接的导电迹线的一部分或两者。
第一底部RDL 103a可以是第一RDL 103的最外层,并且可以安置在第一半导体元件101的第一背面101b附近。第一底部RDL 103a可以包含第一底部RDL介电层104a和安置在第一底部RDL介电层104a上(例如,物理接触或嵌入其中并且由其暴露)的第一底部RDL导电迹线104b。第一底部RDL导电迹线104b可以电连接到第一中间RDL 103b的第一中间RDL导电迹线106b。第一底部RDL介电层104a可以包含例如以下之一或以下的组合:感光材料(例如,聚酰亚胺(PI)、聚酰胺(PA)或其它合适的材料)、环氧树脂材料、树脂材料(例如,味之素增层膜(ABF))、环戊二烯(CPD)、聚对苯撑苯并二噁唑(PBO)、阻焊层材料、纤维和无机材料(例如,Ta2O5、SiO2、Si3N4或其它合适的材料)。在一些实施例中,第一底部RDL介电层104a包含聚酰亚胺。在一些实施例中,第一底部RDL导电迹线104b可以包含例如以下之一或以下的组合:铜、金、铟、锡、银、钯、锇、铱、钌、钛、镁、铝、钴、镍或锌或其它金属或金属合金。
第一顶部RDL 103c可以是第一RDL 103的最外层,并且可以安置在第一中间RDL103b附近。第一顶部RDL 103c可以包含第一顶部RDL介电层118a和安置在第一顶部RDL介电层118a上(例如,物理接触或嵌入其中并且由其暴露)的第一顶部RDL导电迹线118b。第一顶部RDL导电迹线118b可以电连接到第一中间RDL 103b。第一顶部RDL介电层118a可以包含例如以下之一或以下的组合:感光材料(例如,聚酰亚胺(PI)、聚酰胺(PA)或其它合适的材料)、环氧树脂材料、树脂材料(例如味之素增层膜(ABF))、环戊二烯(CPD)、聚对苯撑苯并二噁唑(PBO)、阻焊层材料、纤维和无机材料(例如,Ta2O5、SiO2、Si3N4或其它合适的材料)。在一些实施例中,第一顶部RDL介电层118a包含聚酰亚胺。在一些实施例中,第一顶部RDL导电迹线118b可以包含例如以下之一或以下的组合:铜、金、铟、锡、银、钯、锇、铱、钌、钛、镁、铝、钴、镍或锌或其它金属或金属合金。
可以在第一顶部RDL 103c的表面附近安置至少一个第二导电端子132以实现外部电连接。
第二重布层(RDL)105安置在第一半导体元件101的第一主动表面101a附近。在一些实施例中,第二RDL 105安置在第一半导体元件101的第一主动表面101a上方。在一些实施例中,第二RDL 105电连接到第一半导体元件101的第一主动表面101a。
第二RDL 105可以包含单个层,所述单个层含有介电层和安置在其上(或嵌入其中)的至少一条导电迹线,或者可以包含多个层,所述多个层具有堆叠在一起的介电层,其中每个层均具有安置在其上(或嵌入其中)以将电信号重新分配给外部电连接器或另一个RDL的至少一条导电迹线。在一些实施例(如图1A中所展示的实施例)中,第二RDL 105仅包含单个层,所述单个层含有第二RDL介电层105a和安置在其上(或嵌入其中并由其暴露)的至少一条第二RDL导电迹线124b。在一些实施例中,第二RDL 105电连接到第一半导体元件101的第一主动表面101a并且为第一半导体元件101提供外部电连接。第二RDL介电层105a可以包含例如以下之一或以下的组合:感光材料(例如,聚酰亚胺(PI)、聚酰胺(PA)或其它合适的材料)、环氧树脂材料、树脂材料(例如味之素增层膜(ABF))、环戊二烯(CPD)、聚对苯撑苯并二噁唑(PBO)、阻焊层材料、纤维和无机材料(例如,Ta2O5、SiO2、Si3N4或其它合适的材料)。在一些实施例中,第二RDL介电层105a包含聚酰亚胺。在一些实施例中,第二RDL导电迹线124b可以包含例如以下之一或以下的组合:铜、金、铟、锡、银、钯、锇、铱、钌、钛、镁、铝、钴、镍或锌或其它金属或金属合金。
可以在第二RDL 105的表面附近安置至少一个第三导电端子120a、120b以实现外部电连接。在一些实施例中,第二RDL 105通过第三导电端子120b电连接到第一半导体元件101的第一主动表面101a并且通过第三导电端子120a电连接到导电通孔107。
导电通孔107安置在第一RDL 103与第二RDL 105之间。导电通孔107从第二RDL105到第一RDL 103向内倾斜(inclines inwardly)。亦即,导电通孔107从第二RDL 105到第一RDL 103逐渐变窄(tapers)。导电通孔107可以电连接到第一RDL 103、第二RDL 105或两者。在一些实施例中,导电通孔107将第一RDL 103电连接到第二RDL 105,因此电信号可以从第一RDL 103的一侧传输到第二RDL 105的另一侧。在一些实施例中,导电通孔107通过连接到第一底部RDL 103a的第一底部RDL导电迹线104b而电连接到第一RDL 103并且通过连接到第三导电端子120a而电连接到第二RDL 105。由于导电通孔107是通过激光钻孔技术或机械钻孔技术以及随后的镀覆技术形成的,因此与可以通过拾取和放置预成型导电柱来安置的导电通孔相比,导电通孔107可以具有更高的纵横比,这进而可以产生更大数量的电连接(即,更高的I/O数),因为相比本公开的导电通孔107,导电柱需要的表面积更大。导电通孔107的纵横比的范围可以为1:1到1:10、1:2.5到1:10、1:5到1:10或1:7到1:10。在一些实施例中,导电通孔107的纵横比的范围为1:5到1:10。
在一些实施例中,可以在第一RDL 103与第二RDL 105之间安置第一密封料(encapsulant)111。第一密封料111具有第一密封料上表面111a和与第一密封料上表面111a相对的第一密封料下表面111b。在一些实施例中,第一密封料上表面111a和导电通孔107的通孔上表面107a基本上处于同一平面。在一些实施例中,第一密封料下表面111b和导电通孔107的通孔下表面107b基本上处于同一平面。在一些实施例中,第一密封料上表面111a和导电通孔107的通孔上表面107a以及第一半导体元件101的第一背面101b基本上处于同一平面。
第一密封料111可以围绕导电通孔107。在一些实施例中,第一密封料111和导电通孔107在第一界面107c处连接。第一密封料111可以围绕第一半导体元件101。在一些实施例中,第一密封料111围绕导电通孔107和第一半导体元件101。在一些实施例中,第一密封料111围绕导电通孔107和第一半导体元件101,并且覆盖第一半导体元件101的第一主动表面101a的至少一部分。在一些实施例中,第一密封料111围绕安置在第一半导体元件101的第一主动表面101a附近的第一导电端子102a和/或安置在第二RDL 105的表面附近的第三导电端子120b以使这些导电端子免受氧化、潮湿和其它环境条件的影响,从而满足封装应用要求。第一密封料111可以是例如阻焊层(其材料为例如聚酰亚胺(PI))、钝化层(其材料为例如金属氧化物)或底部填料(underfill)。第一密封料111可以包含填料,所述填料的材料是例如二氧化硅和/或碳,其用于减少管芯上的应力和所得的半导体封装的翘曲。
在一些实施例中,可以在导电通孔107中进一步包含第一晶种层108。第一晶种层108可以安置在第一密封料111的凹部119中。在一些实施例中,第一晶种层108安置在第一密封料111的凹部119的侧壁107c上。在一些实施例中,第一晶种层108被安置成与第一密封料111的侧壁107c相符。第一晶种层108的上表面108a的至少一部分可以由第一密封料111的第一密封料上表面111a暴露并且可以与第一RDL 103接触。下表面108b的至少一部分可以由第一密封料111的第一密封料下表面111b暴露并且可以与第二RDL 105接触。第一晶种层108的上表面108a的至少一部分可以与第一密封料111的第一密封料上表面111a基本上处于同一平面。下表面108b的至少一部分可以与第一密封料111的第一密封料下表面111b基本上处于同一平面。
在一些实施例中,可以在第一RDL 103附近安置至少一个第二半导体元件109。第二半导体元件109可以电连接到第一RDL 103。在一些实施例中,第二半导体元件109通过安置在第二半导体元件109的第二主动表面109a附近的第四导电端子110和安置在第一顶部RDL 103c的表面附近的第二导电端子132电连接到第一RDL 103。第二半导体元件109可以是管芯、芯片、封装、***件或其组合。在一些实施例中,第二半导体元件109是管芯。
在一些实施例中,可以在第一RDL 103的第一上表面103e附近安置第二密封料113。第二密封料113具有第二密封料上表面113a和与第二密封料上表面113a相对的第二密封料下表面113b。在一些实施例中,第二密封料上表面113a暴露第二半导体元件109的第二背面109b的至少一部分。通过暴露第二半导体元件109的第二背面109b的至少一部分,可以提高第二半导体元件109的散热效果。在一些实施例中,可以进一步在第二半导体元件109的第二背面109b的暴露部分附近安置散热器,以进一步提高散热效果。在一些实施例中,第二密封料上表面113a完全覆盖第二半导体元件109的第二背面109b(例如,第二半导体元件109嵌入在第二密封料113中)。在一些实施例中,第二密封料113的第二密封料上表面113a和第二半导体元件109的第二背面109b基本上处于同一平面。
第二密封料113可以围绕安置在第二半导体元件109的第二主动表面109a附近的第四导电端子110和/或安置在第一顶部RDL 103c的表面附近的第二导电端子132以使这些导电端子免受氧化、潮湿和其它环境条件的影响,从而满足封装应用要求。第二密封料113可以是例如阻焊层(其材料为例如聚酰亚胺(PI))、钝化层(其材料为例如金属氧化物)或底部填料。第二密封料113可以包含填料,所述填料的材料是例如二氧化硅和/或碳,其用于减少管芯上的应力和所得的半导体封装的翘曲。
在一些实施例中,可以在第二RDL 105的第二下表面105f附近安置至少一个电连接器123。在一些实施例中,电连接器123电连接到第二RDL 105。在一些实施例中,电连接器123通过连接到接合衬垫(bonding pad)122b而电连接到第二RDL 105,所述接合衬垫122b安置在第二RDL 105的第二下表面105f附近。电连接器123可以是柱(pillar)或焊料凸块(solder bump)/柱状凸块(stud bump)。在一些实施例中,电连接器123是焊料凸块,并且接合衬垫122b是接球衬垫(ball pad)。
图1B展示了根据本公开的一些实施例的图1A的半导体装置封装的导电通孔107和第一密封料111的区域A的放大视图。在一些实施例中,第一密封料111和导电通孔107在第一界面107c处连接。如果应用激光钻孔技术在第一密封料111中形成用于导电通孔107的通孔,则第一界面107c可以是不平的表面。由于高功率激光钻孔的影响,当激光穿过第一密封料111时,激光钻孔技术可以使表面粗糙或不平。第一密封料111的表面粗糙或不平可以通过在表面上提供更多的反应位点来改善第一密封料111与沉积在其上的第一晶种层108之间的接合效果。第一密封料111可以包含填料。在应用激光钻孔并且第一密封料111包含填料112的一些实施例中,第一界面107c处的填料的形状不完整,因为激光钻孔损坏所述填料。
图1C展示了根据本公开的一些实施例的图1A的半导体装置封装的导电通孔107和第一密封料111的区域A的放大视图。图1C所展示的实施例与图1B所展示的实施例的不同之处在于,图1C中利用的激光功率比图1B中利用的激光功率高(例如,波长较小),因此这种功率可能使第一界面107c处的填料蒸发,并且在第一界面107c处可能仅留下凹部114。由于激光钻孔使表面不平,所以可以出于上述原因提高第一密封料111与沉积在其上的第一晶种层108之间的接合效果。
图1D展示了根据本公开的一些实施例的图1A的半导体装置封装的导电通孔107和第一密封料111的区域A的放大视图。图1D所展示的实施例与图1A所展示的实施例的不同之处在于,第一密封料111是通过机械钻孔技术而不是激光钻孔技术来钻取的,所以填料116可以在第一界面107c处保持完整。与那些因为被用于形成导电通孔的激光钻孔工艺损坏而无法保持完整形状的填料112相反,填料116的作用(例如减少所得到的半导体封装的应力或翘曲)可以保持。
图2A展示了根据本公开的一些实施例的图1A的半导体装置封装100的第四导电端子110和第二导电端子132的区域B的放大视图。第四导电端子110可以电连接到第二导电端子132。在一些实施例(如图2A中所展示的实施例)中,第四导电端子110通过混合接合(hybrid bonding)技术电连接到第二导电端子132。
第四导电端子110安置在第二半导体元件109的第二主动表面109a附近。在一些实施例中,第四导电端子110电连接到第二半导体元件109的第二主动表面109a。第四导电端子110可以包含第四接合衬垫110a、第四绝缘层110b、第四电连接器110c和第四金属层110d。
第四接合衬垫110a安置在第二半导体元件109的第二主动表面109a附近。在一些实施例中,第四接合衬垫110a安置在第二半导体元件109的第二主动表面109a上(例如,物理接触或嵌入其中并且由其暴露)。
第四绝缘层110b安置在第二半导体元件109的第二主动表面109a附近。在一些实施例中,第四绝缘层110b安置在第四接合衬垫110a附近。第四绝缘层110b可以界定开口并且暴露第四接合衬垫110a的至少一部分。
第四金属层110d安置在第二半导体元件109的第二主动表面109a附近。在一些实施例中,第四金属层110d安置在第四接合衬垫110a附近。在一些实施例中,第四金属层110d安置在由第四绝缘层110b界定的开口内。第四金属层110d可以界定用于容纳第四电连接器110c的开口。在一些实施例中,第四金属层110d围绕第四电连接器110c。第四金属层110d可以覆盖第四电连接器110c的第四连接器下表面126b的至少一部分。
第四金属层110d具有第四金属上表面128a和与第四金属上表面128a相对的第四金属下表面128b。在一些实施例中,第四金属层110d的第四金属上表面128a与第四绝缘层110b的第四绝缘上表面130a基本上共面。在一些实施例中,第四金属层110d的第四金属上表面128a与第四电连接器110c的第四连接器上表面126a基本上共面。在一些实施例中,第四金属层110d的第四金属上表面128a与第四绝缘层110b的第四绝缘上表面130a和第四电连接器110c的第四连接器上表面126a基本上共面。第四金属层110d可以是金属晶种层。
第四电连接器110c安置在第四接合衬垫110a附近。第四电连接器110c具有第四连接器上表面126a和与第四连接器上表面126a相对的第四连接器下表面126b。在一些实施例中,第四电连接器110c安置在由第四绝缘层110b界定的开口内。在一些实施例中,第四电连接器110c安置在由第四金属层110d界定的开口内。在一些实施例中,第四电连接器110c安置在第四接合衬垫110a上方。第四电连接器110c可以是导电柱结构,例如,铜柱。
通过将第四金属层110d安置为具有与第四绝缘层110b的第四绝缘上表面130a基本上共面的第四金属上表面128a,可以提高第四导电端子110的接合效果,因为第四金属上表面128a和第四绝缘上表面130a将构成混合接合界面,当接合到对应的接合结构(例如,对应的混合接合结构,如第二导电端子132)时,与仅由一种材料组成的界面相比,所述混合接合界面可以更大程度地提高接合强度。另外,第四金属层110d可以增强第四电连接器110c抵抗在结构形成期间(如在接合退火(bonding annealing)工艺期间)发生的侧向应力的能力,因为第四金属层110d的热膨胀系数(CTE)通常由于材料的差异而高于第四绝缘层110b的CTE。
第二导电端子132可以嵌入在第一顶部RDL介电层118a中并且由所述第一顶部RDL介电层118a暴露。第二导电端子132可以对应于第四导电端子110。第二导电端子132可以包含第二接合衬垫132a、第二绝缘层132b、第二电连接器132c和第二金属层132d。第二接合衬垫132a、第二绝缘层132b、第二电连接器132c和第二金属层132d与针对第四导电端子110描述的组件类似,为简洁起见,未对其进行重复描述。同样的第四导电端子110可以应用于图1A所展示的第一导电端子102a并且同样的第二导电端子132可以应用于图1A所展示的第三导电端子120b。
图2B展示了根据本公开的一些实施例的图1A的半导体装置封装的第四导电端子110和第二导电端子132的区域B的放大视图。图2B所展示的接合结构与图2A所展示的接合结构类似,不同之处包含图2B所展示的接合结构应用铜-铜接合技术(copper to copperbonding technique),而不是混合接合技术。图2B中所展示的第四导电端子110和第二导电端子132与图2A所展示的导电端子类似,不同之处包含第四金属层110d不围绕第四电连接器110c,而是第四绝缘层110b围绕第四电连接器110c。另外,第四绝缘层110b的第四绝缘上表面130a和第四电连接器110c的第四连接器上表面126a不处于同一平面;并且第四电连接器110c和第二电连接器132c可以被第二密封料113围绕。
图2B中所展示的第二导电端子132可以对应于图2B所展示的第四导电端子110,为了简洁起见,未对其组件进行重复描述。同样的第四导电端子110可以应用于图1A所展示的第一导电端子102a并且同样的第二导电端子132可以应用于图1A所展示的第三导电端子120b。
第二半导体元件109可以通过如上所述的混合接合技术或铜-铜接合技术电连接到并直接接合到第一RDL 103。通过此类技术,第二半导体元件109可以通过倒装芯片技术成功地直接接合到第一RDL 103,而无需利用焊料凸块/焊钉。因此,信号速度可以更快,这是因为混合接合技术允许第二半导体元件109直接接合到第一RDL 103,这相比通过引线接合技术接合到RDL的半导体元件提供了更短的传输路径。另外,混合接合技术可以避免使用焊钉/焊料凸块可能引起的问题,如由于焊料溢出而引起的焊料污染问题或由焊接材料与其它材料之间的金属互化物(intermetallic coverage or intermetallic compound)引起的RC延迟问题。
此外,由于第二半导体元件109可以通过倒装芯片技术通过混合接合成功地接合到第一RDL 103,因此可以通过第二半导体元件109的第二背面109b减小第二半导体元件109和第二密封料113的厚度来使第二半导体元件109和第二密封料113更薄,这可以进一步减小整个封装的大小。因此,与通过引线接合技术接合到RDL的半导体元件相比,本公开的半导体装置封装可以更薄。
另外,第二半导体元件109的暴露的第二背面109b可以改善散热效果,并且可以灵活地进一步附接散热器以更大程度地改善散热效果。此外,由于混合接合所需的表面积小于引线接合所需的表面积,因此可以通过混合接合增加每单位表面积的电连接。
图3展示了根据本公开的一些实施例的半导体装置封装300的截面视图。半导体装置封装300与图1A所展示的半导体装置封装类似,不同之处包含导电通孔307从第二密封料113的第二密封料上表面113a延伸到第一密封料111的第一密封料下表面111b,因此电信号可以从第二密封料113的一侧传输到第一密封料111的一侧。另外,第一晶种层308覆盖第一密封料111与导电通孔307之间的第一界面307c的至少一部分。在一些实施例中,第一晶种层308被安置成与第一界面307c相符。
图4展示了根据本公开的一些实施例的半导体装置封装400的截面视图。半导体装置封装400与图1A所展示的半导体装置封装类似,不同之处包含第二密封料113的第二密封料上表面113a与第二半导体元件109的第二背面109b不处于同一平面,这使第二半导体元件109的侧表面109c的至少一部分暴露。此类暴露可以改善散热效果。在一些实施例中,第二半导体元件109的第二背面109b从第二密封料113的第二密封料上表面113a凸出。
在一些实施例中,本公开提供了一种制造半导体装置封装的方法,所述方法包含:提供第一半导体元件;在所述第一半导体元件的第一主动表面附近安置第一重布层;在所述第一重布层附近安置第二半导体元件,其中所述第二半导体元件的第二背面面对所述第一重布层;模制所述第二半导体元件以形成第一密封料;在所述第一密封料中形成导电通孔;以及在所述第二半导体元件的第二主动表面附近安置第二重布层。根据本公开的方法,可以成功获得可以包含纵横比相比常规的导电通孔更高(这进而产生更高的I/O数)的导电通孔的半导体装置封装,以及可以实现倒装芯片技术的优良优势(包含更高的I/O数、实现进一步改善的优良散热效果和灵活性以及减小封装大小)以及无焊料技术的优势(包含减少焊料污染可能性)的半导体装置封装。
图5A-5Q展示了制造如图1A的半导体装置封装等半导体装置封装的方法。
参照图5A,提供载体515。载体515具有第一载体表面515a和与第一载体表面515a相对的第二载体表面515b。
参照图5B,在载体515的第一载体表面515a附近安置释放层517。释放层517可以通过层压技术、涂覆技术或其它合适的工艺安置。
参照图5C,在释放层517的释放上表面517a附近安置至少一个第一半导体元件509。在第一半导体元件509的第一主动表面509a上安置至少一个第一导电端子510。第一导电端子510可以是混合接合结构或铜-铜接合结构。在一些实施例中,第一导电端子510通过例如物理气相沉积、镀覆、光刻、蚀刻、层压(或沉积)或其它合适的工艺的组合形成。
参照图5D,在释放层517的释放上表面517a附近安置第一密封料513。第一密封料513可以覆盖释放层517的释放上表面517a的至少一部分、第一导电端子510的至少一部分以及第一半导体元件509的第一主动表面509a的至少一部分。在一些实施例中,第一密封料513完全覆盖第一导电端子510和第一半导体元件509(例如,第一半导体元件509嵌入在第一密封料513中)。第一密封料513可以通过例如模制技术形成。
参照图5E,去除第一密封料513的一部分,直到第一导电端子510的第一导电上表面510a的至少一部分暴露。第一密封料513可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图5F,在第一密封料513的第一密封料下表面513b附近安置第一RDL 503。第一RDL 503可以通过层压技术、光刻技术、镀覆技术和蚀刻技术的组合安置。在第一RDL 503的第一上表面503e附近安置至少一个第二导电端子518b以实现外部电连接。第二导电端子518b可以是混合接合结构或铜-铜接合结构。
参照图5G,在第一RDL 503的第一下表面503f附近安置至少一个第二半导体元件501。在第二半导体元件501的第二主动表面501a上安置至少一个第三导电端子502。第三导电端子502可以是混合接合结构或铜-铜接合结构。在一些实施例中,第三导电端子502通过例如物理气相沉积、镀覆、光刻、蚀刻、层压(或沉积)或其它合适的工艺的组合形成。
参照图5H,在第一RDL 503的第一上表面503f附近安置第二密封料511。第二密封料511可以覆盖第二半导体端子502的至少一部分和第二半导体元件501的第二主动表面501a的至少一部分。在一些实施例中,第二密封料511完全覆盖第二导电端子502和第二半导体元件501(例如,第二半导体元件501嵌入在第二密封料511中)。第二密封料511可以通过例如模制技术形成。
参照图5I,完全去除载体515,这应当暴露释放层517的释放背面517b。载体515可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图5J,完全去除释放层517,这应当暴露第一半导体元件509的第一背面509b和第一密封料513的第一密封料上表面513a。释放层517可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图5K,从第二密封料511的第二密封料下表面511b朝向第一RDL 503的第一下表面503f执行激光钻孔工艺,以形成通孔519,所述通孔暴露第一RDL 503的第一底部RDL导电迹线504b的至少一部分。
参照图5L,安置第一晶种层508在第二密封料511的通孔519的侧壁507c上并且在第一RDL 503的第一底部RDL导电迹线504b的暴露部分的至少一部分上。在一些实施例中,第一晶种层508被安置成与通孔519的形状相符。第一晶种层508可以通过镀覆技术、物理气相沉积技术或其它合适的工艺安置。
参照图5M,安置导电层521在由第一晶种层508界定的开口520中并且在第二密封料511的第二密封料下表面511b的至少一部分上。导电层521可以填充开口520并且覆盖第一晶种层508。导电层521可以通过例如镀覆技术(如电镀)或其它合适的工艺安置。
参照图5N,可以从第一密封料513的第一密封料上表面513a和第一半导体元件509的第一背面509b减薄第一密封料513和第一半导体元件509。减薄工艺可以通过例如研磨技术、抛光技术或其它合适的工艺执行。
参照图5O,去除导电层521的一部分,直到第二导电端子502的至少一部分暴露。另外,可以形成导电通孔507。导电层521可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图5P,在第二密封料511的第二密封料下表面511b附近安置第二RDL 505。第二RDL 505可以通过层压技术、光刻技术、镀覆技术和蚀刻技术的组合安置。在第二密封料511的第二密封料下表面511b附近安置至少一个第四导电端子520b以实现外部电连接。第四导电端子520b可以是混合接合结构或铜-铜接合结构。在一些实施例中,第二RDL 505通过第四导电端子520b与第三导电端子502之间的混合接合或铜-铜接合电连接到或直接接合到第二半导体元件501。在一些实施例中,第四导电端子520b通过例如物理气相沉积、镀覆、光刻、蚀刻、层压(或沉积)或其它合适的工艺的组合形成。
参照图5Q,在第二RDL 505的第二下表面505f附近安置至少一个电连接器523。在一些实施例中,电连接器523安置在接合衬垫522b的从第二RDL 505的第二下表面505f暴露的部分上(例如,物理接触或嵌入其中并且由其暴露),以实现外部电连接。电连接器523可以是焊球,所述焊球可以通过例如焊球放置技术或焊膏印刷技术以及随后的回流技术形成。随后,可以获得半导体装置封装(例如,如图1A所展示的半导体封装100)。
图6A-6O展示了制造如图3的半导体装置封装300等半导体装置封装的方法。
参照图6A-6H,图6A-6H所展示的用于提供载体615、释放层617、第一半导体元件609、第一密封料613、第一RDL 603、第二半导体元件601和第二密封料611的工艺类似于图5A-5H所展示的工艺,为了简洁起见,未对其进行重复描述。
参照图6I,从第二密封料611的第二密封料下表面611b朝向释放层617的释放上表面617a执行激光钻孔工艺,以形成通孔619,所述通孔619暴露释放层617的释放上表面617a的至少一部分。
参照图6J,安置第一晶种层608在通孔619的侧壁607c上并且在释放层617的释放上表面617a的暴露部分的至少一部分上。在一些实施例中,第一晶种层608被安置成与通孔619的形状相符。第一晶种层608可以通过镀覆技术、物理气相沉积技术或其它合适的工艺安置。
参照图6K,安置导电层621在由第一晶种层608界定的开口620中并且在第二密封料611的第二密封料下表面611b的至少一部分上。导电层621可以填充开口620并且覆盖第一晶种层608的至少一部分。导电层621可以通过例如镀覆技术(如电镀)或其它合适的工艺安置。
参照图6L,去除导电层621的一部分,直到第二导电端子602的至少一部分暴露。另外,可以形成导电通孔607。导电层621可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图6M,在第二密封料611的第二密封料下表面611b附近安置第二RDL 605。第二RDL 605可以与针对图5P描述的RDL以类似方式安置,为了简洁起见,未对其进行重复描述。
参照图6N,完全去除载体615和释放层617,这应当暴露第一半导体元件609的第一背面609b和第一密封料613的第一密封料上表面613a。载体615和释放层617可以通过例如研磨技术、抛光技术、蚀刻技术或其它合适的工艺去除。
参照图6O,在第二RDL 605的第二下表面605f附近安置至少一个电连接器623。电连接器623可以与针对图5Q描述的电连接器以类似方式安置,为简洁起见,未对其进行重复描述。随后,可以获得半导体装置封装(例如,如图3所展示的半导体封装300)。
如本文所使用的并且未另外定义的,术语“基本上”和“约”被用来描述和解释小的变化。当结合事件或情形使用时,所述术语可以涵盖事件或情形精确发生的实例以及事件或情形接近发生的实例。例如,当结合数值使用时,所述术语可以涵盖小于或等于所述数值的±10%,如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%或者小于或等于±0.05%的变化范围。作为另一个实例,如果线或平面的峰部或凹部不大于5μm、不大于1μm或不大于0.5μm,则线或平面可以是基本上平坦的。
如本文所使用的,除非上下文另有明确指示,否则单数术语“一个/种(a/an)”和“所述(the)”可以包含复数指代物。在一些实施例的描述中,设置在一个组件“上”或“之上”的另一个组件可以涵盖前一组件直接位于后一组件上(例如,与其物理接触)的情况以及在前一组件与后一组件之间定位有一或多个中间组件的情况。
虽然已经参考本公开的具体实施例描述和展示了本公开,但是这些描述和图示并非限制性的。本领域的技术人员应当理解,在不脱离如由权利要求限定的本公开的精神和范围的情况下,可以作出各种改变并且可以取代等同物。图示可能不一定按比例绘制。由于制造工艺和公差,本公开中的工艺再现与实际装置之间可能存在区别。可能存在未具体展示的本公开的其它实施例。说明书和附图应被认为是说明性而非限制性的。可以作出修改以使特定情况、材料、物质构成、方法或工艺适于本公开的目标、精神和范围。所有此类修改均旨在落入所附权利要求的范围内。虽然已经参考以特定顺序执行的特定操作描述了本文所公开的方法,但是应理解,可以在不脱离本公开的教导的情况下对这些操作进行组合、细分或重新排列以形成等效方法。因此,除非本文中另有明确指示,否则操作的顺序和分组并非限制。
Claims (20)
1.一种半导体装置封装,其包括:
第一半导体元件,其具有第一主动表面和与所述第一主动表面相对的第一背面;
第一重布层,其安置在所述第一半导体元件的所述第一背面附近;
第二重布层,其安置在所述第一半导体元件的所述第一主动表面附近;以及
导电通孔,其安置在所述第一重布层与所述第二重布层之间,其中所述导电通孔从所述第二重布层到所述第一重布层向内倾斜。
2.根据权利要求1所述的半导体装置封装,其中所述第一半导体元件被第一密封料围绕,并且所述导电通孔安置在所述第一密封料中。
3.根据权利要求2所述的半导体装置封装,其中所述导电通孔和所述第一密封料在第一界面处连接,其中所述第一界面具有不平的表面。
4.根据权利要求3所述的半导体装置封装,其中所述第一密封料包括填料,其中所述填料的形状在所述第一界面处不完整。
5.根据权利要求3所述的半导体装置封装,其中所述第一界面具有至少一个凹部。
6.根据权利要求1所述的半导体装置封装,其进一步包括第二半导体元件,所述第二半导体元件安置在所述第一重布层附近,其中所述第二半导体元件具有第二主动表面和与所述第二主动表面相对的第二背面,并且所述第二主动表面面对所述第一重布层,其中所述第二半导体元件被第二密封料围绕,并且所述第二半导体元件的所述第二背面由所述第二密封料暴露。
7.根据权利要求6所述的半导体装置封装,其中所述第二半导体元件包括安置在所述第二半导体元件的所述第二主动表面附近的至少一个第二接合衬垫,其中所述第二接合衬垫被所述第二密封料围绕。
8.根据权利要求6所述的半导体装置封装,其中所述导电通孔从所述第一密封料延伸到所述第二密封料。
9.一种半导体装置封装,其包括:
第一半导体元件,其具有第一主动表面和与所述第一主动表面相对的第一背面;
第一重布层,其安置在所述第一半导体元件的所述第一背面附近;
第二重布层,其安置在所述第一半导体元件的所述第一主动表面附近;以及
第二半导体元件,其具有第二主动表面和与所述第二主动表面相对的第二背面,其中所述第二主动表面直接接合到所述第一重布层。
10.根据权利要求9所述的半导体装置封装,其中所述第二半导体元件被第二密封料围绕。
11.根据权利要求10所述的半导体装置封装,其中所述第二半导体元件的所述第二背面由所述第二密封料暴露。
12.根据权利要求10所述的半导体装置封装,其中所述第二半导体元件包括安置在所述第二半导体元件的所述第二主动表面附近的至少一个第二接合衬垫,其中所述第二接合衬垫被所述第二密封料围绕。
13.根据权利要求10所述的半导体装置封装,其中所述第二半导体元件的所述第二背面从所述第二密封料的表面凸出。
14.根据权利要求9所述的半导体装置封装,其中所述第二主动表面通过混合接合或铜-铜接合直接接合到所述第一重布层。
15.根据权利要求9所述的半导体装置封装,其中所述第一半导体元件通过所述第一主动表面直接接合到所述第二重布层。
16.一种用于制造半导体装置封装的方法,包括:
提供第一半导体元件,所述第一半导体元件具有第一主动表面和与所述第一主动表面相对的第一背面;
在所述第一半导体元件的所述第一主动表面附近安置第一重布层;
在所述第一重布层附近安置第二半导体元件,其中所述第二半导体元件具有第二有主动表面和与所述第二主动表面相对的第二背面,并且所述第二背面面对所述第一重布层;
模制所述第二半导体元件以形成围绕所述第二半导体元件的第一密封料;
在所述第一密封料中形成导电通孔;以及
在所述第二半导体元件的所述第二主动表面附近安置第二重布层。
17.根据权利要求16所述的方法,其进一步包括在安置所述第一重布层的所述步骤之前模制所述第一半导体元件以形成围绕所述第一半导体元件的第二密封料。
18.根据权利要求17所述的方法,其中所述导电通孔被形成为从所述第一密封料延伸到所述第二密封料。
19.根据权利要求16所述的方法,其中形成所述导电通孔的所述步骤包括:
执行钻孔工艺以在所述第一密封料中形成通孔;以及
镀覆所述通孔。
20.根据权利要求18所述的方法,其中形成所述导电通孔的所述步骤包括:
执行钻孔工艺以形成从所述第一密封料延伸到所述第二密封料的通孔;以及
镀覆所述通孔。
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